[linux-2.6-block.git] / drivers / spi / spi-mpc52xx-psc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC52xx PSC in SPI mode driver.
 *
 * Maintainer: Dragos Carp
 *
 * Copyright (C) 2006 TOPTICA Photonics AG.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/workqueue.h>
#include <linux/completion.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/fsl_devices.h>
#include <linux/slab.h>

#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>

#define MCLK 20000000 /* PSC port MClk in hz */

struct mpc52xx_psc_spi {
	/* fsl_spi_platform data */
	void (*cs_control)(struct spi_device *spi, bool on);
	u32 sysclk;

	/* driver internal data */
	struct mpc52xx_psc __iomem *psc;
	struct mpc52xx_psc_fifo __iomem *fifo;
	unsigned int irq;
	u8 bits_per_word;
	u8 busy;

	struct work_struct work;

	struct list_head queue;
	spinlock_t lock;

	struct completion done;
};

/* controller state */
struct mpc52xx_psc_spi_cs {
	int bits_per_word;
	int speed_hz;
};

/* set clock freq, clock ramp, bits per work
 * if t is NULL then reset the values to the default values
 */
static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;

	cs->speed_hz = (t && t->speed_hz)
			? t->speed_hz : spi->max_speed_hz;
	cs->bits_per_word = (t && t->bits_per_word)
			? t->bits_per_word : spi->bits_per_word;
	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
	return 0;
}

static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
{
	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	struct mpc52xx_psc __iomem *psc = mps->psc;
	u32 sicr;
	u16 ccr;

	sicr = in_be32(&psc->sicr);

	/* Set clock phase and polarity */
	if (spi->mode & SPI_CPHA)
		sicr |= 0x00001000;
	else
		sicr &= ~0x00001000;
	if (spi->mode & SPI_CPOL)
		sicr |= 0x00002000;
	else
		sicr &= ~0x00002000;

	if (spi->mode & SPI_LSB_FIRST)
		sicr |= 0x10000000;
	else
		sicr &= ~0x10000000;
	out_be32(&psc->sicr, sicr);

	/* Set clock frequency and bits per word
	 * Because psc->ccr is defined as 16bit register instead of 32bit
	 * just set the lower byte of BitClkDiv
	 */
	ccr = in_be16((u16 __iomem *)&psc->ccr);
	ccr &= 0xFF00;
	if (cs->speed_hz)
		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
	else /* by default SPI Clk 1MHz */
		ccr |= (MCLK / 1000000 - 1) & 0xFF;
	out_be16((u16 __iomem *)&psc->ccr, ccr);
	mps->bits_per_word = cs->bits_per_word;

	if (mps->cs_control)
		mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
}

static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);

	if (mps->cs_control)
		mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
}

#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
/* wake up when 80% fifo full */
#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)

static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
						struct spi_transfer *t)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	struct mpc52xx_psc __iomem *psc = mps->psc;
	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
	unsigned rb = 0;	/* number of bytes receieved */
	unsigned sb = 0;	/* number of bytes sent */
	unsigned char *rx_buf = (unsigned char *)t->rx_buf;
	unsigned char *tx_buf = (unsigned char *)t->tx_buf;
	unsigned rfalarm;
	unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
	unsigned recv_at_once;
	int last_block = 0;

	if (!t->tx_buf && !t->rx_buf && t->len)
		return -EINVAL;

	/* enable transmiter/receiver */
	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
	while (rb < t->len) {
		if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
			rfalarm = MPC52xx_PSC_RFALARM;
			last_block = 0;
		} else {
			send_at_once = t->len - sb;
			rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
			last_block = 1;
		}

		dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
		for (; send_at_once; sb++, send_at_once--) {
			/* set EOF flag before the last word is sent */
			if (send_at_once == 1 && last_block)
				out_8(&psc->ircr2, 0x01);

			if (tx_buf)
				out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
			else
				out_8(&psc->mpc52xx_psc_buffer_8, 0);
		}


		/* enable interrupts and wait for wake up
		 * if just one byte is expected the Rx FIFO genererates no
		 * FFULL interrupt, so activate the RxRDY interrupt
		 */
		out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
		if (t->len - rb == 1) {
			out_8(&psc->mode, 0);
		} else {
			out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
			out_be16(&fifo->rfalarm, rfalarm);
		}
		out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
		wait_for_completion(&mps->done);
		recv_at_once = in_be16(&fifo->rfnum);
		dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);

		send_at_once = recv_at_once;
		if (rx_buf) {
			for (; recv_at_once; rb++, recv_at_once--)
				rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
		} else {
			for (; recv_at_once; rb++, recv_at_once--)
				in_8(&psc->mpc52xx_psc_buffer_8);
		}
	}
	/* disable transmiter/receiver */
	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);

	return 0;
}

static void mpc52xx_psc_spi_work(struct work_struct *work)
{
	struct mpc52xx_psc_spi *mps =
		container_of(work, struct mpc52xx_psc_spi, work);

	spin_lock_irq(&mps->lock);
	mps->busy = 1;
	while (!list_empty(&mps->queue)) {
		struct spi_message *m;
		struct spi_device *spi;
		struct spi_transfer *t = NULL;
		unsigned cs_change;
		int status;

		m = container_of(mps->queue.next, struct spi_message, queue);
		list_del_init(&m->queue);
		spin_unlock_irq(&mps->lock);

		spi = m->spi;
		cs_change = 1;
		status = 0;
		list_for_each_entry (t, &m->transfers, transfer_list) {
			if (t->bits_per_word || t->speed_hz) {
				status = mpc52xx_psc_spi_transfer_setup(spi, t);
				if (status < 0)
					break;
			}

			if (cs_change)
				mpc52xx_psc_spi_activate_cs(spi);
			cs_change = t->cs_change;

			status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
			if (status)
				break;
			m->actual_length += t->len;

			spi_transfer_delay_exec(t);

			if (cs_change)
				mpc52xx_psc_spi_deactivate_cs(spi);
		}

		m->status = status;
		if (m->complete)
			m->complete(m->context);

		if (status || !cs_change)
			mpc52xx_psc_spi_deactivate_cs(spi);

		mpc52xx_psc_spi_transfer_setup(spi, NULL);

		spin_lock_irq(&mps->lock);
	}
	mps->busy = 0;
	spin_unlock_irq(&mps->lock);
}

static int mpc52xx_psc_spi_setup(struct spi_device *spi)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	unsigned long flags;

	if (spi->bits_per_word%8)
		return -EINVAL;

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	cs->bits_per_word = spi->bits_per_word;
	cs->speed_hz = spi->max_speed_hz;

	spin_lock_irqsave(&mps->lock, flags);
	if (!mps->busy)
		mpc52xx_psc_spi_deactivate_cs(spi);
	spin_unlock_irqrestore(&mps->lock, flags);

	return 0;
}

static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
		struct spi_message *m)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	unsigned long flags;

	m->actual_length = 0;
	m->status = -EINPROGRESS;

	spin_lock_irqsave(&mps->lock, flags);
	list_add_tail(&m->queue, &mps->queue);
	schedule_work(&mps->work);
	spin_unlock_irqrestore(&mps->lock, flags);

	return 0;
}

static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
{
	struct mpc52xx_psc __iomem *psc = mps->psc;
	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
	u32 mclken_div;
	int ret;

	/* default sysclk is 512MHz */
	mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
	ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
	if (ret)
		return ret;

	/* Reset the PSC into a known state */
	out_8(&psc->command, MPC52xx_PSC_RST_RX);
	out_8(&psc->command, MPC52xx_PSC_RST_TX);
	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);

	/* Disable interrupts, interrupts are based on alarm level */
	out_be16(&psc->mpc52xx_psc_imr, 0);
	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
	out_8(&fifo->rfcntl, 0);
	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);

	/* Configure 8bit codec mode as a SPI master and use EOF flags */
	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
	out_be32(&psc->sicr, 0x0180C800);
	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */

	/* Set 2ms DTL delay */
	out_8(&psc->ctur, 0x00);
	out_8(&psc->ctlr, 0x84);

	mps->bits_per_word = 8;

	return 0;
}

static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
{
	struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
	struct mpc52xx_psc __iomem *psc = mps->psc;

	/* disable interrupt and wake up the work queue */
	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
		out_be16(&psc->mpc52xx_psc_imr, 0);
		complete(&mps->done);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

/* bus_num is used only for the case dev->platform_data == NULL */
static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
				u32 size, unsigned int irq, s16 bus_num)
{
	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
	struct mpc52xx_psc_spi *mps;
	struct spi_master *master;
	int ret;

	master = spi_alloc_master(dev, sizeof *mps);
	if (master == NULL)
		return -ENOMEM;

	dev_set_drvdata(dev, master);
	mps = spi_master_get_devdata(master);

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;

	mps->irq = irq;
	if (pdata == NULL) {
		dev_warn(dev,
			 "probe called without platform data, no cs_control function will be called\n");
		mps->cs_control = NULL;
		mps->sysclk = 0;
		master->bus_num = bus_num;
		master->num_chipselect = 255;
	} else {
		mps->cs_control = pdata->cs_control;
		mps->sysclk = pdata->sysclk;
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->max_chipselect;
	}
	master->setup = mpc52xx_psc_spi_setup;
	master->transfer = mpc52xx_psc_spi_transfer;
	master->cleanup = mpc52xx_psc_spi_cleanup;
	master->dev.of_node = dev->of_node;

	mps->psc = ioremap(regaddr, size);
	if (!mps->psc) {
		dev_err(dev, "could not ioremap I/O port range\n");
		ret = -EFAULT;
		goto free_master;
	}
	/* On the 5200, fifo regs are immediately ajacent to the psc regs */
	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);

	ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
				mps);
	if (ret)
		goto free_master;

	ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
	if (ret < 0) {
		dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
		goto free_irq;
	}

	spin_lock_init(&mps->lock);
	init_completion(&mps->done);
	INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
	INIT_LIST_HEAD(&mps->queue);

	ret = spi_register_master(master);
	if (ret < 0)
		goto free_irq;

	return ret;

free_irq:
	free_irq(mps->irq, mps);
free_master:
	if (mps->psc)
		iounmap(mps->psc);
	spi_master_put(master);

	return ret;
}

static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
{
	const u32 *regaddr_p;
	u64 regaddr64, size64;
	s16 id = -1;

	regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
	if (!regaddr_p) {
		dev_err(&op->dev, "Invalid PSC address\n");
		return -EINVAL;
	}
	regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);

	/* get PSC id (1..6, used by port_config) */
	if (op->dev.platform_data == NULL) {
		const u32 *psc_nump;

		psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
		if (!psc_nump || *psc_nump > 5) {
			dev_err(&op->dev, "Invalid cell-index property\n");
			return -EINVAL;
		}
		id = *psc_nump + 1;
	}

	return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
				irq_of_parse_and_map(op->dev.of_node, 0), id);
}

static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);

	flush_work(&mps->work);
	spi_unregister_master(master);
	free_irq(mps->irq, mps);
	if (mps->psc)
		iounmap(mps->psc);
	spi_master_put(master);

	return 0;
}

static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
	{ .compatible = "fsl,mpc5200-psc-spi", },
	{ .compatible = "mpc5200-psc-spi", }, /* old */
	{}
};

MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);

static struct platform_driver mpc52xx_psc_spi_of_driver = {
	.probe = mpc52xx_psc_spi_of_probe,
	.remove = mpc52xx_psc_spi_of_remove,
	.driver = {
		.name = "mpc52xx-psc-spi",
		.of_match_table = mpc52xx_psc_spi_of_match,
	},
};
module_platform_driver(mpc52xx_psc_spi_of_driver);

MODULE_AUTHOR("Dragos Carp");
MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
00b8fd23	2	/*
57cc0979	3	* MPC52xx PSC in SPI mode driver.
00b8fd23 DC	4	*
	5	* Maintainer: Dragos Carp
	6	*
	7	* Copyright (C) 2006 TOPTICA Photonics AG.
00b8fd23 DC	8	*/
	9
	10	#include <linux/module.h>
73902842	11	#include <linux/types.h>
00b8fd23 DC	12	#include <linux/errno.h>
00b8fd23 DC	13	#include <linux/interrupt.h>
22ae782f	14	#include <linux/of_address.h>
76ef7dd0	15	#include <linux/of_platform.h>
00b8fd23 DC	16	#include <linux/workqueue.h>
	17	#include <linux/completion.h>
	18	#include <linux/io.h>
	19	#include <linux/delay.h>
	20	#include <linux/spi/spi.h>
	21	#include <linux/fsl_devices.h>
5a0e3ad6	22	#include <linux/slab.h>
00b8fd23 DC	23
	24	#include <asm/mpc52xx.h>
	25	#include <asm/mpc52xx_psc.h>
	26
	27	#define MCLK 20000000 /* PSC port MClk in hz */
	28
	29	struct mpc52xx_psc_spi {
	30	/* fsl_spi_platform data */
73902842	31	void (cs_control)(struct spi_device spi, bool on);
00b8fd23 DC	32	u32 sysclk;
	33
	34	/* driver internal data */
	35	struct mpc52xx_psc __iomem *psc;
4874cc1b	36	struct mpc52xx_psc_fifo __iomem *fifo;
00b8fd23 DC	37	unsigned int irq;
	38	u8 bits_per_word;
	39	u8 busy;
	40
00b8fd23 DC	41	struct work_struct work;
	42
	43	struct list_head queue;
	44	spinlock_t lock;
	45
	46	struct completion done;
	47	};
	48
	49	/* controller state */
	50	struct mpc52xx_psc_spi_cs {
	51	int bits_per_word;
	52	int speed_hz;
	53	};
	54
	55	/* set clock freq, clock ramp, bits per work
	56	* if t is NULL then reset the values to the default values
	57	*/
	58	static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
	59	struct spi_transfer *t)
	60	{
	61	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	62
	63	cs->speed_hz = (t && t->speed_hz)
	64	? t->speed_hz : spi->max_speed_hz;
	65	cs->bits_per_word = (t && t->bits_per_word)
	66	? t->bits_per_word : spi->bits_per_word;
	67	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
	68	return 0;
	69	}
	70
	71	static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
	72	{
	73	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	74	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	75	struct mpc52xx_psc __iomem *psc = mps->psc;
	76	u32 sicr;
	77	u16 ccr;
	78
	79	sicr = in_be32(&psc->sicr);
	80
	81	/* Set clock phase and polarity */
	82	if (spi->mode & SPI_CPHA)
	83	sicr \|= 0x00001000;
	84	else
	85	sicr &= ~0x00001000;
	86	if (spi->mode & SPI_CPOL)
	87	sicr \|= 0x00002000;
	88	else
	89	sicr &= ~0x00002000;
	90
	91	if (spi->mode & SPI_LSB_FIRST)
	92	sicr \|= 0x10000000;
	93	else
	94	sicr &= ~0x10000000;
	95	out_be32(&psc->sicr, sicr);
	96
	97	/* Set clock frequency and bits per word
	98	* Because psc->ccr is defined as 16bit register instead of 32bit
	99	* just set the lower byte of BitClkDiv
	100	*/
a897ea13	101	ccr = in_be16((u16 __iomem *)&psc->ccr);
00b8fd23 DC	102	ccr &= 0xFF00;
	103	if (cs->speed_hz)
	104	ccr \|= (MCLK / cs->speed_hz - 1) & 0xFF;
	105	else /* by default SPI Clk 1MHz */
	106	ccr \|= (MCLK / 1000000 - 1) & 0xFF;
a897ea13	107	out_be16((u16 __iomem *)&psc->ccr, ccr);
00b8fd23 DC	108	mps->bits_per_word = cs->bits_per_word;
00b8fd23 DC	109
73902842 AV	110	if (mps->cs_control)
73902842 AV	111	mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
00b8fd23 DC	112	}
	113
	114	static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
	115	{
	116	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	117
73902842 AV	118	if (mps->cs_control)
73902842 AV	119	mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
00b8fd23 DC	120	}
	121
	122	#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
	123	/* wake up when 80% fifo full */
	124	#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
	125
	126	static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
	127	struct spi_transfer *t)
	128	{
	129	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	130	struct mpc52xx_psc __iomem *psc = mps->psc;
4874cc1b	131	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
00b8fd23 DC	132	unsigned rb = 0; /* number of bytes receieved */
	133	unsigned sb = 0; /* number of bytes sent */
	134	unsigned char rx_buf = (unsigned char )t->rx_buf;
	135	unsigned char tx_buf = (unsigned char )t->tx_buf;
	136	unsigned rfalarm;
	137	unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
	138	unsigned recv_at_once;
b7d271df	139	int last_block = 0;
00b8fd23 DC	140
	141	if (!t->tx_buf && !t->rx_buf && t->len)
	142	return -EINVAL;
	143
	144	/* enable transmiter/receiver */
	145	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE \| MPC52xx_PSC_RX_ENABLE);
	146	while (rb < t->len) {
	147	if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
	148	rfalarm = MPC52xx_PSC_RFALARM;
b7d271df	149	last_block = 0;
00b8fd23 DC	150	} else {
	151	send_at_once = t->len - sb;
	152	rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
b7d271df	153	last_block = 1;
00b8fd23 DC	154	}
	155
	156	dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
9a7867e1 LF	157	for (; send_at_once; sb++, send_at_once--) {
9a7867e1 LF	158	/* set EOF flag before the last word is sent */
b7d271df	159	if (send_at_once == 1 && last_block)
9a7867e1 LF	160	out_8(&psc->ircr2, 0x01);
	161
	162	if (tx_buf)
00b8fd23	163	out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
9a7867e1	164	else
00b8fd23	165	out_8(&psc->mpc52xx_psc_buffer_8, 0);
00b8fd23 DC	166	}
	167
	168
3a4fa0a2	169	/* enable interrupts and wait for wake up
00b8fd23 DC	170	* if just one byte is expected the Rx FIFO genererates no
	171	* FFULL interrupt, so activate the RxRDY interrupt
	172	*/
	173	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
	174	if (t->len - rb == 1) {
	175	out_8(&psc->mode, 0);
	176	} else {
	177	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
4874cc1b	178	out_be16(&fifo->rfalarm, rfalarm);
00b8fd23 DC	179	}
	180	out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
	181	wait_for_completion(&mps->done);
4874cc1b	182	recv_at_once = in_be16(&fifo->rfnum);
00b8fd23 DC	183	dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
	184
	185	send_at_once = recv_at_once;
	186	if (rx_buf) {
	187	for (; recv_at_once; rb++, recv_at_once--)
	188	rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
	189	} else {
	190	for (; recv_at_once; rb++, recv_at_once--)
	191	in_8(&psc->mpc52xx_psc_buffer_8);
	192	}
	193	}
	194	/* disable transmiter/receiver */
	195	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE \| MPC52xx_PSC_RX_DISABLE);
	196
	197	return 0;
	198	}
	199
	200	static void mpc52xx_psc_spi_work(struct work_struct *work)
	201	{
	202	struct mpc52xx_psc_spi *mps =
	203	container_of(work, struct mpc52xx_psc_spi, work);
	204
	205	spin_lock_irq(&mps->lock);
	206	mps->busy = 1;
	207	while (!list_empty(&mps->queue)) {
	208	struct spi_message *m;
	209	struct spi_device *spi;
	210	struct spi_transfer *t = NULL;
	211	unsigned cs_change;
	212	int status;
	213
	214	m = container_of(mps->queue.next, struct spi_message, queue);
	215	list_del_init(&m->queue);
	216	spin_unlock_irq(&mps->lock);
	217
	218	spi = m->spi;
	219	cs_change = 1;
	220	status = 0;
	221	list_for_each_entry (t, &m->transfers, transfer_list) {
	222	if (t->bits_per_word \|\| t->speed_hz) {
	223	status = mpc52xx_psc_spi_transfer_setup(spi, t);
	224	if (status < 0)
	225	break;
	226	}
	227
	228	if (cs_change)
	229	mpc52xx_psc_spi_activate_cs(spi);
	230	cs_change = t->cs_change;
	231
	232	status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
	233	if (status)
	234	break;
	235	m->actual_length += t->len;
	236
e74dc5c7	237	spi_transfer_delay_exec(t);
00b8fd23 DC	238
	239	if (cs_change)
	240	mpc52xx_psc_spi_deactivate_cs(spi);
	241	}
	242
	243	m->status = status;
0a6d3879 AL	244	if (m->complete)
0a6d3879 AL	245	m->complete(m->context);
00b8fd23 DC	246
	247	if (status \|\| !cs_change)
	248	mpc52xx_psc_spi_deactivate_cs(spi);
	249
	250	mpc52xx_psc_spi_transfer_setup(spi, NULL);
	251
	252	spin_lock_irq(&mps->lock);
	253	}
	254	mps->busy = 0;
	255	spin_unlock_irq(&mps->lock);
	256	}
	257
	258	static int mpc52xx_psc_spi_setup(struct spi_device *spi)
	259	{
	260	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	261	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	262	unsigned long flags;
	263
	264	if (spi->bits_per_word%8)
	265	return -EINVAL;
	266
	267	if (!cs) {
	268	cs = kzalloc(sizeof *cs, GFP_KERNEL);
	269	if (!cs)
	270	return -ENOMEM;
	271	spi->controller_state = cs;
	272	}
	273
	274	cs->bits_per_word = spi->bits_per_word;
	275	cs->speed_hz = spi->max_speed_hz;
	276
	277	spin_lock_irqsave(&mps->lock, flags);
	278	if (!mps->busy)
	279	mpc52xx_psc_spi_deactivate_cs(spi);
	280	spin_unlock_irqrestore(&mps->lock, flags);
	281
	282	return 0;
	283	}
	284
	285	static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
	286	struct spi_message *m)
	287	{
	288	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	289	unsigned long flags;
	290
	291	m->actual_length = 0;
	292	m->status = -EINPROGRESS;
	293
	294	spin_lock_irqsave(&mps->lock, flags);
	295	list_add_tail(&m->queue, &mps->queue);
ac96b737	296	schedule_work(&mps->work);
00b8fd23 DC	297	spin_unlock_irqrestore(&mps->lock, flags);
	298
	299	return 0;
	300	}
	301
	302	static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
	303	{
	304	kfree(spi->controller_state);
	305	}
	306
	307	static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
	308	{
00b8fd23	309	struct mpc52xx_psc __iomem *psc = mps->psc;
4874cc1b	310	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
00b8fd23	311	u32 mclken_div;
f856cf01	312	int ret;
00b8fd23	313
00b8fd23	314	/* default sysclk is 512MHz */
4fb4c558	315	mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
f856cf01 WS	316	ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
	317	if (ret)
	318	return ret;
00b8fd23 DC	319
	320	/* Reset the PSC into a known state */
	321	out_8(&psc->command, MPC52xx_PSC_RST_RX);
	322	out_8(&psc->command, MPC52xx_PSC_RST_TX);
	323	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE \| MPC52xx_PSC_RX_DISABLE);
	324
	325	/* Disable interrupts, interrupts are based on alarm level */
	326	out_be16(&psc->mpc52xx_psc_imr, 0);
	327	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
4874cc1b	328	out_8(&fifo->rfcntl, 0);
00b8fd23 DC	329	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
	330
	331	/* Configure 8bit codec mode as a SPI master and use EOF flags */
	332	/* SICR_SIM_CODEC8\|SICR_GENCLK\|SICR_SPI\|SICR_MSTR\|SICR_USEEOF */
	333	out_be32(&psc->sicr, 0x0180C800);
a897ea13	334	out_be16((u16 __iomem )&psc->ccr, 0x070F); / default SPI Clk 1MHz */
00b8fd23 DC	335
	336	/* Set 2ms DTL delay */
	337	out_8(&psc->ctur, 0x00);
	338	out_8(&psc->ctlr, 0x84);
	339
	340	mps->bits_per_word = 8;
	341
f856cf01	342	return 0;
00b8fd23 DC	343	}
	344
	345	static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
	346	{
	347	struct mpc52xx_psc_spi mps = (struct mpc52xx_psc_spi )dev_id;
	348	struct mpc52xx_psc __iomem *psc = mps->psc;
	349
	350	/* disable interrupt and wake up the work queue */
	351	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
	352	out_be16(&psc->mpc52xx_psc_imr, 0);
	353	complete(&mps->done);
	354	return IRQ_HANDLED;
	355	}
	356	return IRQ_NONE;
	357	}
	358
	359	/* bus_num is used only for the case dev->platform_data == NULL */
fd4a319b	360	static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
00b8fd23 DC	361	u32 size, unsigned int irq, s16 bus_num)
00b8fd23 DC	362	{
8074cf06	363	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
00b8fd23 DC	364	struct mpc52xx_psc_spi *mps;
	365	struct spi_master *master;
	366	int ret;
	367
00b8fd23 DC	368	master = spi_alloc_master(dev, sizeof *mps);
	369	if (master == NULL)
	370	return -ENOMEM;
	371
	372	dev_set_drvdata(dev, master);
	373	mps = spi_master_get_devdata(master);
	374
e7db06b5 DB	375	/* the spi->mode bits understood by this driver: */
	376	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST;
	377
00b8fd23 DC	378	mps->irq = irq;
00b8fd23 DC	379	if (pdata == NULL) {
f6bd03a7 JN	380	dev_warn(dev,
f6bd03a7 JN	381	"probe called without platform data, no cs_control function will be called\n");
73902842	382	mps->cs_control = NULL;
00b8fd23 DC	383	mps->sysclk = 0;
	384	master->bus_num = bus_num;
	385	master->num_chipselect = 255;
	386	} else {
73902842	387	mps->cs_control = pdata->cs_control;
00b8fd23 DC	388	mps->sysclk = pdata->sysclk;
	389	master->bus_num = pdata->bus_num;
	390	master->num_chipselect = pdata->max_chipselect;
	391	}
	392	master->setup = mpc52xx_psc_spi_setup;
	393	master->transfer = mpc52xx_psc_spi_transfer;
	394	master->cleanup = mpc52xx_psc_spi_cleanup;
12b15e83	395	master->dev.of_node = dev->of_node;
00b8fd23 DC	396
	397	mps->psc = ioremap(regaddr, size);
	398	if (!mps->psc) {
	399	dev_err(dev, "could not ioremap I/O port range\n");
	400	ret = -EFAULT;
	401	goto free_master;
	402	}
4874cc1b GL	403	/* On the 5200, fifo regs are immediately ajacent to the psc regs */
4874cc1b GL	404	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
00b8fd23 DC	405
	406	ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
	407	mps);
	408	if (ret)
	409	goto free_master;
	410
	411	ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
f856cf01 WS	412	if (ret < 0) {
f856cf01 WS	413	dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
00b8fd23	414	goto free_irq;
f856cf01	415	}
00b8fd23 DC	416
	417	spin_lock_init(&mps->lock);
	418	init_completion(&mps->done);
	419	INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
	420	INIT_LIST_HEAD(&mps->queue);
	421
00b8fd23 DC	422	ret = spi_register_master(master);
00b8fd23 DC	423	if (ret < 0)
ac96b737	424	goto free_irq;
00b8fd23 DC	425
	426	return ret;
	427
00b8fd23 DC	428	free_irq:
	429	free_irq(mps->irq, mps);
	430	free_master:
	431	if (mps->psc)
	432	iounmap(mps->psc);
	433	spi_master_put(master);
	434
	435	return ret;
	436	}
	437
fd4a319b	438	static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
00b8fd23 DC	439	{
	440	const u32 *regaddr_p;
	441	u64 regaddr64, size64;
	442	s16 id = -1;
	443
61c7a080	444	regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
00b8fd23	445	if (!regaddr_p) {
5cc17d7e	446	dev_err(&op->dev, "Invalid PSC address\n");
00b8fd23 DC	447	return -EINVAL;
00b8fd23 DC	448	}
61c7a080	449	regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
00b8fd23	450
8888735f	451	/* get PSC id (1..6, used by port_config) */
00b8fd23	452	if (op->dev.platform_data == NULL) {
8888735f	453	const u32 *psc_nump;
00b8fd23	454
61c7a080	455	psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
8888735f	456	if (!psc_nump \|\| *psc_nump > 5) {
5cc17d7e	457	dev_err(&op->dev, "Invalid cell-index property\n");
8888735f	458	return -EINVAL;
00b8fd23	459	}
8888735f	460	id = *psc_nump + 1;
00b8fd23 DC	461	}
00b8fd23 DC	462
12b15e83	463	return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
61c7a080	464	irq_of_parse_and_map(op->dev.of_node, 0), id);
00b8fd23 DC	465	}
00b8fd23 DC	466
fd4a319b	467	static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
00b8fd23	468	{
24b5a82c	469	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
5aa68b85 WS	470	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
5aa68b85 WS	471
ac96b737	472	flush_work(&mps->work);
5aa68b85 WS	473	spi_unregister_master(master);
	474	free_irq(mps->irq, mps);
	475	if (mps->psc)
	476	iounmap(mps->psc);
c8c87c65	477	spi_master_put(master);
5aa68b85 WS	478
5aa68b85 WS	479	return 0;
00b8fd23 DC	480	}
00b8fd23 DC	481
631e61b7	482	static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
66ffbe49 GL	483	{ .compatible = "fsl,mpc5200-psc-spi", },
	484	{ .compatible = "mpc5200-psc-spi", }, /* old */
	485	{}
00b8fd23 DC	486	};
	487
	488	MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
	489
18d306d1	490	static struct platform_driver mpc52xx_psc_spi_of_driver = {
00b8fd23	491	.probe = mpc52xx_psc_spi_of_probe,
fd4a319b	492	.remove = mpc52xx_psc_spi_of_remove,
00b8fd23 DC	493	.driver = {
00b8fd23 DC	494	.name = "mpc52xx-psc-spi",
4018294b	495	.of_match_table = mpc52xx_psc_spi_of_match,
00b8fd23 DC	496	},
00b8fd23 DC	497	};
940ab889	498	module_platform_driver(mpc52xx_psc_spi_of_driver);
00b8fd23	499
00b8fd23 DC	500	MODULE_AUTHOR("Dragos Carp");
	501	MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
	502	MODULE_LICENSE("GPL");