[linux-2.6-block.git] / drivers / spi / spi-mpc512x-psc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC512x PSC in SPI mode driver.
 *
 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
 * Original port from 52xx driver:
 *	Hongjun Chen <hong-jun.chen@freescale.com>
 *
 * Fork of mpc52xx_psc_spi.c:
 *	Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/spi/spi.h>
#include <asm/mpc52xx_psc.h>

enum {
	TYPE_MPC5121,
	TYPE_MPC5125,
};

/*
 * This macro abstracts the differences in the PSC register layout between
 * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
 */
#define psc_addr(mps, regname) ({					\
	void *__ret = NULL;						\
	switch (mps->type) {						\
	case TYPE_MPC5121: {						\
			struct mpc52xx_psc __iomem *psc = mps->psc;	\
			__ret = &psc->regname;				\
		};							\
		break;							\
	case TYPE_MPC5125: {						\
			struct mpc5125_psc __iomem *psc = mps->psc;	\
			__ret = &psc->regname;				\
		};							\
		break;							\
	}								\
	__ret; })

struct mpc512x_psc_spi {
	/* driver internal data */
	int type;
	void __iomem *psc;
	struct mpc512x_psc_fifo __iomem *fifo;
	int irq;
	u8 bits_per_word;
	u32 mclk_rate;

	struct completion txisrdone;
};

/* controller state */
struct mpc512x_psc_spi_cs {
	int bits_per_word;
	int speed_hz;
};

/* set clock freq, clock ramp, bits per work
 * if t is NULL then reset the values to the default values
 */
static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
					  struct spi_transfer *t)
{
	struct mpc512x_psc_spi_cs *cs = spi->controller_state;

	cs->speed_hz = (t && t->speed_hz)
	    ? t->speed_hz : spi->max_speed_hz;
	cs->bits_per_word = (t && t->bits_per_word)
	    ? t->bits_per_word : spi->bits_per_word;
	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
	return 0;
}

static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
{
	struct mpc512x_psc_spi_cs *cs = spi->controller_state;
	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller);
	u32 sicr;
	u32 ccr;
	int speed;
	u16 bclkdiv;

	sicr = in_be32(psc_addr(mps, sicr));

	/* Set clock phase and polarity */
	if (spi->mode & SPI_CPHA)
		sicr |= 0x00001000;
	else
		sicr &= ~0x00001000;

	if (spi->mode & SPI_CPOL)
		sicr |= 0x00002000;
	else
		sicr &= ~0x00002000;

	if (spi->mode & SPI_LSB_FIRST)
		sicr |= 0x10000000;
	else
		sicr &= ~0x10000000;
	out_be32(psc_addr(mps, sicr), sicr);

	ccr = in_be32(psc_addr(mps, ccr));
	ccr &= 0xFF000000;
	speed = cs->speed_hz;
	if (!speed)
		speed = 1000000;	/* default 1MHz */
	bclkdiv = (mps->mclk_rate / speed) - 1;

	ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
	out_be32(psc_addr(mps, ccr), ccr);
	mps->bits_per_word = cs->bits_per_word;

	if (spi_get_csgpiod(spi, 0)) {
		/* gpiolib will deal with the inversion */
		gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
	}
}

static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
{
	if (spi_get_csgpiod(spi, 0)) {
		/* gpiolib will deal with the inversion */
		gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
	}
}

/* extract and scale size field in txsz or rxsz */
#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);

#define EOFBYTE 1

static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
					 struct spi_transfer *t)
{
	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller);
	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
	size_t tx_len = t->len;
	size_t rx_len = t->len;
	u8 *tx_buf = (u8 *)t->tx_buf;
	u8 *rx_buf = (u8 *)t->rx_buf;

	if (!tx_buf && !rx_buf && t->len)
		return -EINVAL;

	while (rx_len || tx_len) {
		size_t txcount;
		u8 data;
		size_t fifosz;
		size_t rxcount;
		int rxtries;

		/*
		 * send the TX bytes in as large a chunk as possible
		 * but neither exceed the TX nor the RX FIFOs
		 */
		fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
		txcount = min(fifosz, tx_len);
		fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
		fifosz -= in_be32(&fifo->rxcnt) + 1;
		txcount = min(fifosz, txcount);
		if (txcount) {

			/* fill the TX FIFO */
			while (txcount-- > 0) {
				data = tx_buf ? *tx_buf++ : 0;
				if (tx_len == EOFBYTE && t->cs_change)
					setbits32(&fifo->txcmd,
						  MPC512x_PSC_FIFO_EOF);
				out_8(&fifo->txdata_8, data);
				tx_len--;
			}

			/* have the ISR trigger when the TX FIFO is empty */
			reinit_completion(&mps->txisrdone);
			out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
			out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
			wait_for_completion(&mps->txisrdone);
		}

		/*
		 * consume as much RX data as the FIFO holds, while we
		 * iterate over the transfer's TX data length
		 *
		 * only insist in draining all the remaining RX bytes
		 * when the TX bytes were exhausted (that's at the very
		 * end of this transfer, not when still iterating over
		 * the transfer's chunks)
		 */
		rxtries = 50;
		do {

			/*
			 * grab whatever was in the FIFO when we started
			 * looking, don't bother fetching what was added to
			 * the FIFO while we read from it -- we'll return
			 * here eventually and prefer sending out remaining
			 * TX data
			 */
			fifosz = in_be32(&fifo->rxcnt);
			rxcount = min(fifosz, rx_len);
			while (rxcount-- > 0) {
				data = in_8(&fifo->rxdata_8);
				if (rx_buf)
					*rx_buf++ = data;
				rx_len--;
			}

			/*
			 * come back later if there still is TX data to send,
			 * bail out of the RX drain loop if all of the TX data
			 * was sent and all of the RX data was received (i.e.
			 * when the transmission has completed)
			 */
			if (tx_len)
				break;
			if (!rx_len)
				break;

			/*
			 * TX data transmission has completed while RX data
			 * is still pending -- that's a transient situation
			 * which depends on wire speed and specific
			 * hardware implementation details (buffering) yet
			 * should resolve very quickly
			 *
			 * just yield for a moment to not hog the CPU for
			 * too long when running SPI at low speed
			 *
			 * the timeout range is rather arbitrary and tries
			 * to balance throughput against system load; the
			 * chosen values result in a minimal timeout of 50
			 * times 10us and thus work at speeds as low as
			 * some 20kbps, while the maximum timeout at the
			 * transfer's end could be 5ms _if_ nothing else
			 * ticks in the system _and_ RX data still wasn't
			 * received, which only occurs in situations that
			 * are exceptional; removing the unpredictability
			 * of the timeout either decreases throughput
			 * (longer timeouts), or puts more load on the
			 * system (fixed short timeouts) or requires the
			 * use of a timeout API instead of a counter and an
			 * unknown inner delay
			 */
			usleep_range(10, 100);

		} while (--rxtries > 0);
		if (!tx_len && rx_len && !rxtries) {
			/*
			 * not enough RX bytes even after several retries
			 * and the resulting rather long timeout?
			 */
			rxcount = in_be32(&fifo->rxcnt);
			dev_warn(&spi->dev,
				 "short xfer, missing %zd RX bytes, FIFO level %zd\n",
				 rx_len, rxcount);
		}

		/*
		 * drain and drop RX data which "should not be there" in
		 * the first place, for undisturbed transmission this turns
		 * into a NOP (except for the FIFO level fetch)
		 */
		if (!tx_len && !rx_len) {
			while (in_be32(&fifo->rxcnt))
				in_8(&fifo->rxdata_8);
		}

	}
	return 0;
}

static int mpc512x_psc_spi_msg_xfer(struct spi_controller *host,
				    struct spi_message *m)
{
	struct spi_device *spi;
	unsigned cs_change;
	int status;
	struct spi_transfer *t;

	spi = m->spi;
	cs_change = 1;
	status = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		status = mpc512x_psc_spi_transfer_setup(spi, t);
		if (status < 0)
			break;

		if (cs_change)
			mpc512x_psc_spi_activate_cs(spi);
		cs_change = t->cs_change;

		status = mpc512x_psc_spi_transfer_rxtx(spi, t);
		if (status)
			break;
		m->actual_length += t->len;

		spi_transfer_delay_exec(t);

		if (cs_change)
			mpc512x_psc_spi_deactivate_cs(spi);
	}

	m->status = status;
	if (m->complete)
		m->complete(m->context);

	if (status || !cs_change)
		mpc512x_psc_spi_deactivate_cs(spi);

	mpc512x_psc_spi_transfer_setup(spi, NULL);

	spi_finalize_current_message(host);
	return status;
}

static int mpc512x_psc_spi_prep_xfer_hw(struct spi_controller *host)
{
	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host);

	dev_dbg(&host->dev, "%s()\n", __func__);

	/* Zero MR2 */
	in_8(psc_addr(mps, mr2));
	out_8(psc_addr(mps, mr2), 0x0);

	/* enable transmitter/receiver */
	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);

	return 0;
}

static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_controller *host)
{
	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host);
	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;

	dev_dbg(&host->dev, "%s()\n", __func__);

	/* disable transmitter/receiver and fifo interrupt */
	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
	out_be32(&fifo->tximr, 0);

	return 0;
}

static int mpc512x_psc_spi_setup(struct spi_device *spi)
{
	struct mpc512x_psc_spi_cs *cs = spi->controller_state;

	if (spi->bits_per_word % 8)
		return -EINVAL;

	if (!cs) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;

		spi->controller_state = cs;
	}

	cs->bits_per_word = spi->bits_per_word;
	cs->speed_hz = spi->max_speed_hz;

	return 0;
}

static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static int mpc512x_psc_spi_port_config(struct spi_controller *host,
				       struct mpc512x_psc_spi *mps)
{
	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
	u32 sicr;
	u32 ccr;
	int speed;
	u16 bclkdiv;

	/* Reset the PSC into a known state */
	out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
	out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);

	/* Disable psc interrupts all useful interrupts are in fifo */
	out_be16(psc_addr(mps, isr_imr.imr), 0);

	/* Disable fifo interrupts, will be enabled later */
	out_be32(&fifo->tximr, 0);
	out_be32(&fifo->rximr, 0);

	/* Setup fifo slice address and size */
	/*out_be32(&fifo->txsz, 0x0fe00004);*/
	/*out_be32(&fifo->rxsz, 0x0ff00004);*/

	sicr =	0x01000000 |	/* SIM = 0001 -- 8 bit */
		0x00800000 |	/* GenClk = 1 -- internal clk */
		0x00008000 |	/* SPI = 1 */
		0x00004000 |	/* MSTR = 1   -- SPI host */
		0x00000800;	/* UseEOF = 1 -- SS low until EOF */

	out_be32(psc_addr(mps, sicr), sicr);

	ccr = in_be32(psc_addr(mps, ccr));
	ccr &= 0xFF000000;
	speed = 1000000;	/* default 1MHz */
	bclkdiv = (mps->mclk_rate / speed) - 1;
	ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
	out_be32(psc_addr(mps, ccr), ccr);

	/* Set 2ms DTL delay */
	out_8(psc_addr(mps, ctur), 0x00);
	out_8(psc_addr(mps, ctlr), 0x82);

	/* we don't use the alarms */
	out_be32(&fifo->rxalarm, 0xfff);
	out_be32(&fifo->txalarm, 0);

	/* Enable FIFO slices for Rx/Tx */
	out_be32(&fifo->rxcmd,
		 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
	out_be32(&fifo->txcmd,
		 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);

	mps->bits_per_word = 8;

	return 0;
}

static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
{
	struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;

	/* clear interrupt and wake up the rx/tx routine */
	if (in_be32(&fifo->txisr) &
	    in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
		out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
		out_be32(&fifo->tximr, 0);
		complete(&mps->txisrdone);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static int mpc512x_psc_spi_of_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct mpc512x_psc_spi *mps;
	struct spi_controller *host;
	int ret;
	void *tempp;
	struct clk *clk;

	host = devm_spi_alloc_host(dev, sizeof(*mps));
	if (host == NULL)
		return -ENOMEM;

	dev_set_drvdata(dev, host);
	mps = spi_controller_get_devdata(host);
	mps->type = (int)device_get_match_data(dev);

	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
	host->setup = mpc512x_psc_spi_setup;
	host->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
	host->transfer_one_message = mpc512x_psc_spi_msg_xfer;
	host->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
	host->use_gpio_descriptors = true;
	host->cleanup = mpc512x_psc_spi_cleanup;

	device_set_node(&host->dev, dev_fwnode(dev));

	tempp = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
	if (IS_ERR(tempp))
		return dev_err_probe(dev, PTR_ERR(tempp), "could not ioremap I/O port range\n");
	mps->psc = tempp;
	mps->fifo =
		(struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));

	mps->irq = platform_get_irq(pdev, 0);
	if (mps->irq < 0)
		return mps->irq;

	ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
				"mpc512x-psc-spi", mps);
	if (ret)
		return ret;
	init_completion(&mps->txisrdone);

	clk = devm_clk_get_enabled(dev, "mclk");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	mps->mclk_rate = clk_get_rate(clk);

	clk = devm_clk_get_enabled(dev, "ipg");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = mpc512x_psc_spi_port_config(host, mps);
	if (ret < 0)
		return ret;

	return devm_spi_register_controller(dev, host);
}

static const struct of_device_id mpc512x_psc_spi_of_match[] = {
	{ .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
	{ .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
	{},
};

MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);

static struct platform_driver mpc512x_psc_spi_of_driver = {
	.probe = mpc512x_psc_spi_of_probe,
	.driver = {
		.name = "mpc512x-psc-spi",
		.of_match_table = mpc512x_psc_spi_of_match,
	},
};
module_platform_driver(mpc512x_psc_spi_of_driver);

MODULE_AUTHOR("John Rigby");
MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
6e27388f AG	2	/*
	3	* MPC512x PSC in SPI mode driver.
	4	*
	5	* Copyright (C) 2007,2008 Freescale Semiconductor Inc.
	6	* Original port from 52xx driver:
	7	* Hongjun Chen <hong-jun.chen@freescale.com>
	8	*
	9	* Fork of mpc52xx_psc_spi.c:
	10	* Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
6e27388f AG	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
6e27388f AG	15	#include <linux/errno.h>
6e27388f AG	16	#include <linux/interrupt.h>
6e27388f AG	17	#include <linux/completion.h>
6e27388f AG	18	#include <linux/io.h>
60a6c825	19	#include <linux/platform_device.h>
289c084d	20	#include <linux/property.h>
6e27388f AG	21	#include <linux/delay.h>
	22	#include <linux/clk.h>
	23	#include <linux/spi/spi.h>
6e27388f AG	24	#include <asm/mpc52xx_psc.h>
6e27388f AG	25
8bf96098 UKK	26	enum {
	27	TYPE_MPC5121,
	28	TYPE_MPC5125,
	29	};
	30
	31	/*
	32	* This macro abstracts the differences in the PSC register layout between
	33	* MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
	34	*/
	35	#define psc_addr(mps, regname) ({ \
1f2112af UKK	36	void *__ret = NULL; \
1f2112af UKK	37	switch (mps->type) { \
8bf96098 UKK	38	case TYPE_MPC5121: { \
	39	struct mpc52xx_psc __iomem *psc = mps->psc; \
	40	__ret = &psc->regname; \
	41	}; \
	42	break; \
	43	case TYPE_MPC5125: { \
	44	struct mpc5125_psc __iomem *psc = mps->psc; \
	45	__ret = &psc->regname; \
	46	}; \
	47	break; \
	48	} \
	49	__ret; })
	50
6e27388f	51	struct mpc512x_psc_spi {
6e27388f	52	/* driver internal data */
8bf96098 UKK	53	int type;
8bf96098 UKK	54	void __iomem *psc;
6e27388f	55	struct mpc512x_psc_fifo __iomem *fifo;
de5e92cb	56	int irq;
6e27388f	57	u8 bits_per_word;
a81a5094	58	u32 mclk_rate;
6e27388f	59
c36e93a0	60	struct completion txisrdone;
6e27388f AG	61	};
	62
	63	/* controller state */
	64	struct mpc512x_psc_spi_cs {
	65	int bits_per_word;
	66	int speed_hz;
	67	};
	68
	69	/* set clock freq, clock ramp, bits per work
	70	* if t is NULL then reset the values to the default values
	71	*/
	72	static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
	73	struct spi_transfer *t)
	74	{
	75	struct mpc512x_psc_spi_cs *cs = spi->controller_state;
	76
	77	cs->speed_hz = (t && t->speed_hz)
	78	? t->speed_hz : spi->max_speed_hz;
	79	cs->bits_per_word = (t && t->bits_per_word)
	80	? t->bits_per_word : spi->bits_per_word;
	81	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
	82	return 0;
	83	}
	84
	85	static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
	86	{
	87	struct mpc512x_psc_spi_cs *cs = spi->controller_state;
a21db739	88	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller);
6e27388f AG	89	u32 sicr;
6e27388f AG	90	u32 ccr;
a81a5094	91	int speed;
6e27388f AG	92	u16 bclkdiv;
6e27388f AG	93
8bf96098	94	sicr = in_be32(psc_addr(mps, sicr));
6e27388f AG	95
	96	/* Set clock phase and polarity */
	97	if (spi->mode & SPI_CPHA)
	98	sicr \|= 0x00001000;
	99	else
	100	sicr &= ~0x00001000;
	101
	102	if (spi->mode & SPI_CPOL)
	103	sicr \|= 0x00002000;
	104	else
	105	sicr &= ~0x00002000;
	106
	107	if (spi->mode & SPI_LSB_FIRST)
	108	sicr \|= 0x10000000;
	109	else
	110	sicr &= ~0x10000000;
8bf96098	111	out_be32(psc_addr(mps, sicr), sicr);
6e27388f	112
8bf96098	113	ccr = in_be32(psc_addr(mps, ccr));
6e27388f	114	ccr &= 0xFF000000;
a81a5094 GS	115	speed = cs->speed_hz;
	116	if (!speed)
	117	speed = 1000000; /* default 1MHz */
	118	bclkdiv = (mps->mclk_rate / speed) - 1;
6e27388f AG	119
6e27388f AG	120	ccr \|= (((bclkdiv & 0xff) << 16) \| (((bclkdiv >> 8) & 0xff) << 8));
8bf96098	121	out_be32(psc_addr(mps, ccr), ccr);
6e27388f AG	122	mps->bits_per_word = cs->bits_per_word;
6e27388f AG	123
9e264f3f	124	if (spi_get_csgpiod(spi, 0)) {
04725901	125	/* gpiolib will deal with the inversion */
9e264f3f	126	gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
2818824c	127	}
6e27388f AG	128	}
	129
	130	static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
	131	{
9e264f3f	132	if (spi_get_csgpiod(spi, 0)) {
04725901	133	/* gpiolib will deal with the inversion */
9e264f3f	134	gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
2818824c	135	}
6e27388f AG	136	}
	137
	138	/* extract and scale size field in txsz or rxsz */
	139	#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
	140
	141	#define EOFBYTE 1
	142
	143	static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
	144	struct spi_transfer *t)
	145	{
a21db739	146	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller);
6e27388f	147	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
c36e93a0	148	size_t tx_len = t->len;
5df24ea6	149	size_t rx_len = t->len;
6e27388f AG	150	u8 tx_buf = (u8 )t->tx_buf;
	151	u8 rx_buf = (u8 )t->rx_buf;
	152
	153	if (!tx_buf && !rx_buf && t->len)
	154	return -EINVAL;
	155
5df24ea6	156	while (rx_len \|\| tx_len) {
c36e93a0	157	size_t txcount;
6e27388f AG	158	u8 data;
6e27388f AG	159	size_t fifosz;
c36e93a0	160	size_t rxcount;
5df24ea6	161	int rxtries;
6e27388f AG	162
6e27388f AG	163	/*
5df24ea6 GS	164	* send the TX bytes in as large a chunk as possible
5df24ea6 GS	165	* but neither exceed the TX nor the RX FIFOs
6e27388f AG	166	*/
6e27388f AG	167	fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
c36e93a0	168	txcount = min(fifosz, tx_len);
5df24ea6 GS	169	fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
	170	fifosz -= in_be32(&fifo->rxcnt) + 1;
	171	txcount = min(fifosz, txcount);
	172	if (txcount) {
	173
	174	/* fill the TX FIFO */
	175	while (txcount-- > 0) {
	176	data = tx_buf ? *tx_buf++ : 0;
	177	if (tx_len == EOFBYTE && t->cs_change)
	178	setbits32(&fifo->txcmd,
	179	MPC512x_PSC_FIFO_EOF);
	180	out_8(&fifo->txdata_8, data);
	181	tx_len--;
	182	}
6e27388f	183
5df24ea6	184	/* have the ISR trigger when the TX FIFO is empty */
16735d02	185	reinit_completion(&mps->txisrdone);
5df24ea6 GS	186	out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
	187	out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
	188	wait_for_completion(&mps->txisrdone);
6e27388f AG	189	}
6e27388f AG	190
5df24ea6 GS	191	/*
	192	* consume as much RX data as the FIFO holds, while we
	193	* iterate over the transfer's TX data length
	194	*
	195	* only insist in draining all the remaining RX bytes
	196	* when the TX bytes were exhausted (that's at the very
	197	* end of this transfer, not when still iterating over
	198	* the transfer's chunks)
	199	*/
	200	rxtries = 50;
	201	do {
	202
	203	/*
	204	* grab whatever was in the FIFO when we started
	205	* looking, don't bother fetching what was added to
	206	* the FIFO while we read from it -- we'll return
	207	* here eventually and prefer sending out remaining
	208	* TX data
	209	*/
	210	fifosz = in_be32(&fifo->rxcnt);
	211	rxcount = min(fifosz, rx_len);
	212	while (rxcount-- > 0) {
	213	data = in_8(&fifo->rxdata_8);
	214	if (rx_buf)
	215	*rx_buf++ = data;
	216	rx_len--;
	217	}
6e27388f	218
5df24ea6 GS	219	/*
	220	* come back later if there still is TX data to send,
	221	* bail out of the RX drain loop if all of the TX data
	222	* was sent and all of the RX data was received (i.e.
	223	* when the transmission has completed)
	224	*/
	225	if (tx_len)
	226	break;
	227	if (!rx_len)
	228	break;
	229
	230	/*
	231	* TX data transmission has completed while RX data
	232	* is still pending -- that's a transient situation
	233	* which depends on wire speed and specific
	234	* hardware implementation details (buffering) yet
	235	* should resolve very quickly
	236	*
	237	* just yield for a moment to not hog the CPU for
	238	* too long when running SPI at low speed
	239	*
	240	* the timeout range is rather arbitrary and tries
	241	* to balance throughput against system load; the
	242	* chosen values result in a minimal timeout of 50
	243	* times 10us and thus work at speeds as low as
	244	* some 20kbps, while the maximum timeout at the
	245	* transfer's end could be 5ms _if_ nothing else
	246	* ticks in the system _and_ RX data still wasn't
	247	* received, which only occurs in situations that
	248	* are exceptional; removing the unpredictability
	249	* of the timeout either decreases throughput
	250	* (longer timeouts), or puts more load on the
	251	* system (fixed short timeouts) or requires the
	252	* use of a timeout API instead of a counter and an
	253	* unknown inner delay
	254	*/
	255	usleep_range(10, 100);
	256
	257	} while (--rxtries > 0);
	258	if (!tx_len && rx_len && !rxtries) {
	259	/*
	260	* not enough RX bytes even after several retries
	261	* and the resulting rather long timeout?
	262	*/
	263	rxcount = in_be32(&fifo->rxcnt);
	264	dev_warn(&spi->dev,
	265	"short xfer, missing %zd RX bytes, FIFO level %zd\n",
	266	rx_len, rxcount);
6e27388f AG	267	}
6e27388f AG	268
5df24ea6 GS	269	/*
	270	* drain and drop RX data which "should not be there" in
	271	* the first place, for undisturbed transmission this turns
	272	* into a NOP (except for the FIFO level fetch)
	273	*/
	274	if (!tx_len && !rx_len) {
	275	while (in_be32(&fifo->rxcnt))
	276	in_8(&fifo->rxdata_8);
6e27388f	277	}
5df24ea6	278
6e27388f	279	}
6e27388f AG	280	return 0;
	281	}
	282
a21db739	283	static int mpc512x_psc_spi_msg_xfer(struct spi_controller *host,
85085898	284	struct spi_message *m)
6e27388f	285	{
85085898 GS	286	struct spi_device *spi;
	287	unsigned cs_change;
	288	int status;
	289	struct spi_transfer *t;
	290
	291	spi = m->spi;
	292	cs_change = 1;
	293	status = 0;
	294	list_for_each_entry(t, &m->transfers, transfer_list) {
85c1912d JN	295	status = mpc512x_psc_spi_transfer_setup(spi, t);
	296	if (status < 0)
	297	break;
6e27388f	298
85085898 GS	299	if (cs_change)
	300	mpc512x_psc_spi_activate_cs(spi);
	301	cs_change = t->cs_change;
6e27388f	302
85085898 GS	303	status = mpc512x_psc_spi_transfer_rxtx(spi, t);
	304	if (status)
	305	break;
	306	m->actual_length += t->len;
6e27388f	307
e74dc5c7	308	spi_transfer_delay_exec(t);
6e27388f	309
85085898	310	if (cs_change)
6e27388f	311	mpc512x_psc_spi_deactivate_cs(spi);
85085898	312	}
6e27388f	313
85085898	314	m->status = status;
0a6d3879 AL	315	if (m->complete)
0a6d3879 AL	316	m->complete(m->context);
6e27388f	317
85085898 GS	318	if (status \|\| !cs_change)
	319	mpc512x_psc_spi_deactivate_cs(spi);
	320
	321	mpc512x_psc_spi_transfer_setup(spi, NULL);
	322
a21db739	323	spi_finalize_current_message(host);
85085898 GS	324	return status;
	325	}
	326
a21db739	327	static int mpc512x_psc_spi_prep_xfer_hw(struct spi_controller *host)
85085898	328	{
a21db739	329	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host);
85085898	330
a21db739	331	dev_dbg(&host->dev, "%s()\n", __func__);
85085898 GS	332
85085898 GS	333	/* Zero MR2 */
8bf96098 UKK	334	in_8(psc_addr(mps, mr2));
8bf96098 UKK	335	out_8(psc_addr(mps, mr2), 0x0);
85085898 GS	336
85085898 GS	337	/* enable transmitter/receiver */
8bf96098	338	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE \| MPC52xx_PSC_RX_ENABLE);
85085898 GS	339
	340	return 0;
	341	}
	342
a21db739	343	static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_controller *host)
85085898	344	{
a21db739	345	struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host);
85085898 GS	346	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
85085898 GS	347
a21db739	348	dev_dbg(&host->dev, "%s()\n", __func__);
85085898 GS	349
85085898 GS	350	/* disable transmitter/receiver and fifo interrupt */
8bf96098	351	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE \| MPC52xx_PSC_RX_DISABLE);
85085898 GS	352	out_be32(&fifo->tximr, 0);
	353
	354	return 0;
6e27388f AG	355	}
	356
	357	static int mpc512x_psc_spi_setup(struct spi_device *spi)
	358	{
6e27388f	359	struct mpc512x_psc_spi_cs *cs = spi->controller_state;
6e27388f AG	360
	361	if (spi->bits_per_word % 8)
	362	return -EINVAL;
	363
	364	if (!cs) {
722cb2b1	365	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
6e27388f AG	366	if (!cs)
6e27388f AG	367	return -ENOMEM;
86e98743	368
6e27388f AG	369	spi->controller_state = cs;
	370	}
	371
	372	cs->bits_per_word = spi->bits_per_word;
	373	cs->speed_hz = spi->max_speed_hz;
	374
6e27388f AG	375	return 0;
	376	}
	377
	378	static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
	379	{
	380	kfree(spi->controller_state);
	381	}
	382
a21db739	383	static int mpc512x_psc_spi_port_config(struct spi_controller *host,
6e27388f AG	384	struct mpc512x_psc_spi *mps)
6e27388f AG	385	{
6e27388f	386	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
6e27388f AG	387	u32 sicr;
6e27388f AG	388	u32 ccr;
a81a5094	389	int speed;
6e27388f AG	390	u16 bclkdiv;
6e27388f AG	391
6e27388f	392	/* Reset the PSC into a known state */
8bf96098 UKK	393	out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
	394	out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
	395	out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE \| MPC52xx_PSC_RX_DISABLE);
6e27388f AG	396
6e27388f AG	397	/* Disable psc interrupts all useful interrupts are in fifo */
8bf96098	398	out_be16(psc_addr(mps, isr_imr.imr), 0);
6e27388f AG	399
	400	/* Disable fifo interrupts, will be enabled later */
	401	out_be32(&fifo->tximr, 0);
	402	out_be32(&fifo->rximr, 0);
	403
	404	/* Setup fifo slice address and size */
	405	/out_be32(&fifo->txsz, 0x0fe00004);/
	406	/out_be32(&fifo->rxsz, 0x0ff00004);/
	407
	408	sicr = 0x01000000 \| /* SIM = 0001 -- 8 bit */
	409	0x00800000 \| /* GenClk = 1 -- internal clk */
	410	0x00008000 \| /* SPI = 1 */
a21db739	411	0x00004000 \| /* MSTR = 1 -- SPI host */
6e27388f AG	412	0x00000800; /* UseEOF = 1 -- SS low until EOF */
6e27388f AG	413
8bf96098	414	out_be32(psc_addr(mps, sicr), sicr);
6e27388f	415
8bf96098	416	ccr = in_be32(psc_addr(mps, ccr));
6e27388f	417	ccr &= 0xFF000000;
a81a5094 GS	418	speed = 1000000; /* default 1MHz */
a81a5094 GS	419	bclkdiv = (mps->mclk_rate / speed) - 1;
6e27388f	420	ccr \|= (((bclkdiv & 0xff) << 16) \| (((bclkdiv >> 8) & 0xff) << 8));
8bf96098	421	out_be32(psc_addr(mps, ccr), ccr);
6e27388f AG	422
6e27388f AG	423	/* Set 2ms DTL delay */
8bf96098 UKK	424	out_8(psc_addr(mps, ctur), 0x00);
8bf96098 UKK	425	out_8(psc_addr(mps, ctlr), 0x82);
6e27388f AG	426
	427	/* we don't use the alarms */
	428	out_be32(&fifo->rxalarm, 0xfff);
	429	out_be32(&fifo->txalarm, 0);
	430
	431	/* Enable FIFO slices for Rx/Tx */
	432	out_be32(&fifo->rxcmd,
	433	MPC512x_PSC_FIFO_ENABLE_SLICE \| MPC512x_PSC_FIFO_ENABLE_DMA);
	434	out_be32(&fifo->txcmd,
	435	MPC512x_PSC_FIFO_ENABLE_SLICE \| MPC512x_PSC_FIFO_ENABLE_DMA);
	436
	437	mps->bits_per_word = 8;
	438
a81a5094	439	return 0;
6e27388f AG	440	}
	441
	442	static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
	443	{
	444	struct mpc512x_psc_spi mps = (struct mpc512x_psc_spi )dev_id;
	445	struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
	446
85085898	447	/* clear interrupt and wake up the rx/tx routine */
6e27388f AG	448	if (in_be32(&fifo->txisr) &
	449	in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
	450	out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
	451	out_be32(&fifo->tximr, 0);
c36e93a0	452	complete(&mps->txisrdone);
6e27388f AG	453	return IRQ_HANDLED;
	454	}
	455	return IRQ_NONE;
	456	}
	457
60a6c825	458	static int mpc512x_psc_spi_of_probe(struct platform_device *pdev)
6e27388f	459	{
60a6c825	460	struct device *dev = &pdev->dev;
6e27388f	461	struct mpc512x_psc_spi *mps;
a21db739	462	struct spi_controller *host;
6e27388f AG	463	int ret;
6e27388f AG	464	void *tempp;
a81a5094	465	struct clk *clk;
6e27388f	466
a21db739 YY	467	host = devm_spi_alloc_host(dev, sizeof(*mps));
a21db739 YY	468	if (host == NULL)
6e27388f AG	469	return -ENOMEM;
6e27388f AG	470
a21db739 YY	471	dev_set_drvdata(dev, host);
a21db739 YY	472	mps = spi_controller_get_devdata(host);
60a6c825	473	mps->type = (int)device_get_match_data(dev);
6e27388f	474
a21db739 YY	475	host->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST;
	476	host->setup = mpc512x_psc_spi_setup;
	477	host->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
	478	host->transfer_one_message = mpc512x_psc_spi_msg_xfer;
	479	host->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
	480	host->use_gpio_descriptors = true;
	481	host->cleanup = mpc512x_psc_spi_cleanup;
289c084d	482
a21db739	483	device_set_node(&host->dev, dev_fwnode(dev));
6e27388f	484
60a6c825	485	tempp = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
ee493fa5 AS	486	if (IS_ERR(tempp))
ee493fa5 AS	487	return dev_err_probe(dev, PTR_ERR(tempp), "could not ioremap I/O port range\n");
6e27388f AG	488	mps->psc = tempp;
	489	mps->fifo =
	490	(struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
60a6c825 RH	491
60a6c825 RH	492	mps->irq = platform_get_irq(pdev, 0);
208ee586 AS	493	if (mps->irq < 0)
	494	return mps->irq;
	495
e1d0cd47 JH	496	ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
e1d0cd47 JH	497	"mpc512x-psc-spi", mps);
6e27388f	498	if (ret)
01602336	499	return ret;
85085898	500	init_completion(&mps->txisrdone);
6e27388f	501
9e21720a	502	clk = devm_clk_get_enabled(dev, "mclk");
01602336 RH	503	if (IS_ERR(clk))
	504	return PTR_ERR(clk);
	505
a81a5094 GS	506	mps->mclk_rate = clk_get_rate(clk);
a81a5094 GS	507
9e21720a AS	508	clk = devm_clk_get_enabled(dev, "ipg");
	509	if (IS_ERR(clk))
	510	return PTR_ERR(clk);
dff148ad	511
a21db739	512	ret = mpc512x_psc_spi_port_config(host, mps);
6e27388f	513	if (ret < 0)
21d19e60	514	return ret;
6e27388f	515
a21db739	516	return devm_spi_register_controller(dev, host);
6e27388f AG	517	}
6e27388f AG	518
09355402	519	static const struct of_device_id mpc512x_psc_spi_of_match[] = {
8bf96098 UKK	520	{ .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
8bf96098 UKK	521	{ .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
6e27388f AG	522	{},
	523	};
	524
	525	MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
	526
18d306d1	527	static struct platform_driver mpc512x_psc_spi_of_driver = {
6e27388f	528	.probe = mpc512x_psc_spi_of_probe,
6e27388f AG	529	.driver = {
6e27388f AG	530	.name = "mpc512x-psc-spi",
ef7f2e83	531	.of_match_table = mpc512x_psc_spi_of_match,
6e27388f AG	532	},
6e27388f AG	533	};
940ab889	534	module_platform_driver(mpc512x_psc_spi_of_driver);
6e27388f AG	535
	536	MODULE_AUTHOR("John Rigby");
	537	MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
	538	MODULE_LICENSE("GPL");