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79650597 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | // Copyright (C) 2008 Juergen Beisert | |
b5f3294f SH |
4 | |
5 | #include <linux/clk.h> | |
6 | #include <linux/completion.h> | |
7 | #include <linux/delay.h> | |
f62caccd RG |
8 | #include <linux/dmaengine.h> |
9 | #include <linux/dma-mapping.h> | |
b5f3294f | 10 | #include <linux/err.h> |
b5f3294f SH |
11 | #include <linux/interrupt.h> |
12 | #include <linux/io.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
525c9e5a | 16 | #include <linux/pinctrl/consumer.h> |
b5f3294f | 17 | #include <linux/platform_device.h> |
525c9e5a | 18 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
b5f3294f | 20 | #include <linux/spi/spi.h> |
b5f3294f | 21 | #include <linux/types.h> |
22a85e4c | 22 | #include <linux/of.h> |
8cdcd8ae | 23 | #include <linux/property.h> |
b5f3294f | 24 | |
c6547c2e | 25 | #include <linux/dma/imx-dma.h> |
b5f3294f SH |
26 | |
27 | #define DRIVER_NAME "spi_imx" | |
28 | ||
0a9c8998 TP |
29 | static bool use_dma = true; |
30 | module_param(use_dma, bool, 0644); | |
31 | MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); | |
32 | ||
07e75938 MKB |
33 | /* define polling limits */ |
34 | static unsigned int polling_limit_us = 30; | |
35 | module_param(polling_limit_us, uint, 0664); | |
36 | MODULE_PARM_DESC(polling_limit_us, | |
37 | "time in us to run a transfer in polling mode\n"); | |
38 | ||
525c9e5a CW |
39 | #define MXC_RPM_TIMEOUT 2000 /* 2000ms */ |
40 | ||
b5f3294f SH |
41 | #define MXC_CSPIRXDATA 0x00 |
42 | #define MXC_CSPITXDATA 0x04 | |
43 | #define MXC_CSPICTRL 0x08 | |
44 | #define MXC_CSPIINT 0x0c | |
45 | #define MXC_RESET 0x1c | |
46 | ||
47 | /* generic defines to abstract from the different register layouts */ | |
48 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
49 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
71abd290 | 50 | #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ |
b5f3294f | 51 | |
30d67142 UKK |
52 | /* The maximum bytes that a sdma BD can transfer. */ |
53 | #define MAX_SDMA_BD_BYTES (1 << 15) | |
1673c81d | 54 | #define MX51_ECSPI_CTRL_MAX_BURST 512 |
756d5bf0 | 55 | /* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/ |
71abd290 | 56 | #define MX53_MAX_TRANSFER_BYTES 512 |
b5f3294f | 57 | |
f4ba6315 | 58 | enum spi_imx_devtype { |
04ee5854 SG |
59 | IMX1_CSPI, |
60 | IMX21_CSPI, | |
61 | IMX27_CSPI, | |
62 | IMX31_CSPI, | |
63 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
26e4bb86 | 64 | IMX51_ECSPI, /* ECSPI on i.mx51 */ |
65 | IMX53_ECSPI, /* ECSPI on i.mx53 and later */ | |
f4ba6315 UKK |
66 | }; |
67 | ||
68 | struct spi_imx_data; | |
69 | ||
70 | struct spi_imx_devtype_data { | |
f7b87871 MKB |
71 | void (*intctrl)(struct spi_imx_data *spi_imx, int enable); |
72 | int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg); | |
73 | int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi); | |
74 | void (*trigger)(struct spi_imx_data *spi_imx); | |
75 | int (*rx_available)(struct spi_imx_data *spi_imx); | |
76 | void (*reset)(struct spi_imx_data *spi_imx); | |
77 | void (*setup_wml)(struct spi_imx_data *spi_imx); | |
78 | void (*disable)(struct spi_imx_data *spi_imx); | |
fd8d4e2d | 79 | bool has_dmamode; |
756d5bf0 | 80 | bool has_targetmode; |
fd8d4e2d | 81 | unsigned int fifo_size; |
1673c81d | 82 | bool dynamic_burst; |
8eb1252b RG |
83 | /* |
84 | * ERR009165 fixed or not: | |
85 | * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf | |
86 | */ | |
87 | bool tx_glitch_fixed; | |
04ee5854 | 88 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
89 | }; |
90 | ||
6cdeb002 | 91 | struct spi_imx_data { |
307c897d | 92 | struct spi_controller *controller; |
6aa800ca | 93 | struct device *dev; |
b5f3294f SH |
94 | |
95 | struct completion xfer_done; | |
cc4d22ae | 96 | void __iomem *base; |
f12ae171 AB |
97 | unsigned long base_phys; |
98 | ||
aa29d840 SH |
99 | struct clk *clk_per; |
100 | struct clk *clk_ipg; | |
b5f3294f | 101 | unsigned long spi_clk; |
4bfe927a | 102 | unsigned int spi_bus_clk; |
b5f3294f | 103 | |
d52345b6 | 104 | unsigned int bits_per_word; |
f72efa7e | 105 | unsigned int spi_drctl; |
f12ae171 | 106 | |
1673c81d | 107 | unsigned int count, remainder; |
f7b87871 MKB |
108 | void (*tx)(struct spi_imx_data *spi_imx); |
109 | void (*rx)(struct spi_imx_data *spi_imx); | |
b5f3294f SH |
110 | void *rx_buf; |
111 | const void *tx_buf; | |
112 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
2ca300ac | 113 | unsigned int dynamic_burst; |
79422ed9 | 114 | bool rx_only; |
b5f3294f | 115 | |
756d5bf0 YY |
116 | /* Target mode */ |
117 | bool target_mode; | |
118 | bool target_aborted; | |
119 | unsigned int target_burst; | |
71abd290 | 120 | |
f62caccd | 121 | /* DMA */ |
f62caccd | 122 | bool usedma; |
0dfbaa89 | 123 | u32 wml; |
f62caccd RG |
124 | struct completion dma_rx_completion; |
125 | struct completion dma_tx_completion; | |
126 | ||
80023cb3 | 127 | const struct spi_imx_devtype_data *devtype_data; |
b5f3294f SH |
128 | }; |
129 | ||
04ee5854 SG |
130 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
131 | { | |
132 | return d->devtype_data->devtype == IMX27_CSPI; | |
133 | } | |
134 | ||
135 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
136 | { | |
137 | return d->devtype_data->devtype == IMX35_CSPI; | |
138 | } | |
139 | ||
f8a87617 AB |
140 | static inline int is_imx51_ecspi(struct spi_imx_data *d) |
141 | { | |
142 | return d->devtype_data->devtype == IMX51_ECSPI; | |
143 | } | |
144 | ||
26e4bb86 | 145 | static inline int is_imx53_ecspi(struct spi_imx_data *d) |
146 | { | |
147 | return d->devtype_data->devtype == IMX53_ECSPI; | |
148 | } | |
149 | ||
b5f3294f | 150 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 151 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 152 | { \ |
6cdeb002 | 153 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 154 | \ |
6cdeb002 UKK |
155 | if (spi_imx->rx_buf) { \ |
156 | *(type *)spi_imx->rx_buf = val; \ | |
157 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f | 158 | } \ |
2ca300ac MC |
159 | \ |
160 | spi_imx->remainder -= sizeof(type); \ | |
b5f3294f SH |
161 | } |
162 | ||
163 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 164 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
165 | { \ |
166 | type val = 0; \ | |
167 | \ | |
6cdeb002 UKK |
168 | if (spi_imx->tx_buf) { \ |
169 | val = *(type *)spi_imx->tx_buf; \ | |
170 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
171 | } \ |
172 | \ | |
6cdeb002 | 173 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 174 | \ |
6cdeb002 | 175 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
176 | } |
177 | ||
178 | MXC_SPI_BUF_RX(u8) | |
179 | MXC_SPI_BUF_TX(u8) | |
180 | MXC_SPI_BUF_RX(u16) | |
181 | MXC_SPI_BUF_TX(u16) | |
182 | MXC_SPI_BUF_RX(u32) | |
183 | MXC_SPI_BUF_TX(u32) | |
184 | ||
185 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
186 | * (which is currently not the case in this driver) | |
187 | */ | |
188 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
189 | 256, 384, 512, 768, 1024}; | |
190 | ||
191 | /* MX21, MX27 */ | |
6cdeb002 | 192 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
32df9ff2 | 193 | unsigned int fspi, unsigned int max, unsigned int *fres) |
b5f3294f | 194 | { |
04ee5854 | 195 | int i; |
b5f3294f SH |
196 | |
197 | for (i = 2; i < max; i++) | |
198 | if (fspi * mxc_clkdivs[i] >= fin) | |
32df9ff2 | 199 | break; |
b5f3294f | 200 | |
32df9ff2 RB |
201 | *fres = fin / mxc_clkdivs[i]; |
202 | return i; | |
b5f3294f SH |
203 | } |
204 | ||
0b599603 | 205 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 206 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
2636ba8f | 207 | unsigned int fspi, unsigned int *fres) |
b5f3294f SH |
208 | { |
209 | int i, div = 4; | |
210 | ||
211 | for (i = 0; i < 7; i++) { | |
212 | if (fspi * div >= fin) | |
2636ba8f | 213 | goto out; |
b5f3294f SH |
214 | div <<= 1; |
215 | } | |
216 | ||
2636ba8f MK |
217 | out: |
218 | *fres = fin / div; | |
219 | return i; | |
b5f3294f SH |
220 | } |
221 | ||
2e312f6c | 222 | static int spi_imx_bytes_per_word(const int bits_per_word) |
f12ae171 | 223 | { |
afb27208 MC |
224 | if (bits_per_word <= 8) |
225 | return 1; | |
226 | else if (bits_per_word <= 16) | |
227 | return 2; | |
228 | else | |
229 | return 4; | |
f12ae171 AB |
230 | } |
231 | ||
63cd96b7 | 232 | static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi, |
f62caccd RG |
233 | struct spi_transfer *transfer) |
234 | { | |
63cd96b7 | 235 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); |
f12ae171 | 236 | |
63cd96b7 | 237 | if (!use_dma || controller->fallback) |
0a9c8998 TP |
238 | return false; |
239 | ||
63cd96b7 | 240 | if (!controller->dma_rx) |
f12ae171 AB |
241 | return false; |
242 | ||
756d5bf0 | 243 | if (spi_imx->target_mode) |
71abd290 | 244 | return false; |
245 | ||
133eb8e3 RG |
246 | if (transfer->len < spi_imx->devtype_data->fifo_size) |
247 | return false; | |
248 | ||
1673c81d | 249 | spi_imx->dynamic_burst = 0; |
66459c5a | 250 | |
f12ae171 | 251 | return true; |
f62caccd RG |
252 | } |
253 | ||
87c61417 KG |
254 | /* |
255 | * Note the number of natively supported chip selects for MX51 is 4. Some | |
256 | * devices may have less actual SS pins but the register map supports 4. When | |
257 | * using gpio chip selects the cs values passed into the macros below can go | |
258 | * outside the range 0 - 3. We therefore need to limit the cs value to avoid | |
259 | * corrupting bits outside the allocated locations. | |
260 | * | |
261 | * The simplest way to do this is to just mask the cs bits to 2 bits. This | |
262 | * still allows all 4 native chip selects to work as well as gpio chip selects | |
263 | * (which can use any of the 4 chip select configurations). | |
264 | */ | |
265 | ||
66de757c SG |
266 | #define MX51_ECSPI_CTRL 0x08 |
267 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
268 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
f62caccd | 269 | #define MX51_ECSPI_CTRL_SMC (1 << 3) |
66de757c | 270 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) |
f72efa7e | 271 | #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) |
66de757c SG |
272 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 |
273 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
87c61417 | 274 | #define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18) |
66de757c | 275 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 |
1673c81d | 276 | #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) |
66de757c SG |
277 | |
278 | #define MX51_ECSPI_CONFIG 0x0c | |
87c61417 KG |
279 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0)) |
280 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) | |
281 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) | |
282 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) | |
6a983ff5 | 283 | #define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16)) |
87c61417 | 284 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) |
66de757c SG |
285 | |
286 | #define MX51_ECSPI_INT 0x10 | |
287 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
288 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
71abd290 | 289 | #define MX51_ECSPI_INT_RDREN (1 << 4) |
66de757c | 290 | |
30d67142 | 291 | #define MX51_ECSPI_DMA 0x14 |
d629c2a0 SH |
292 | #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) |
293 | #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) | |
294 | #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) | |
f62caccd | 295 | |
2b0fd069 SH |
296 | #define MX51_ECSPI_DMA_TEDEN (1 << 7) |
297 | #define MX51_ECSPI_DMA_RXDEN (1 << 23) | |
298 | #define MX51_ECSPI_DMA_RXTDEN (1 << 31) | |
f62caccd | 299 | |
66de757c SG |
300 | #define MX51_ECSPI_STAT 0x18 |
301 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 | 302 | |
9f6aa42b FE |
303 | #define MX51_ECSPI_TESTREG 0x20 |
304 | #define MX51_ECSPI_TESTREG_LBC BIT(31) | |
305 | ||
1673c81d | 306 | static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) |
307 | { | |
308 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); | |
1673c81d | 309 | |
310 | if (spi_imx->rx_buf) { | |
311 | #ifdef __LITTLE_ENDIAN | |
baaadffe MKB |
312 | unsigned int bytes_per_word; |
313 | ||
1673c81d | 314 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); |
315 | if (bytes_per_word == 1) | |
dae336d0 | 316 | swab32s(&val); |
1673c81d | 317 | else if (bytes_per_word == 2) |
baaadffe | 318 | swahw32s(&val); |
1673c81d | 319 | #endif |
1673c81d | 320 | *(u32 *)spi_imx->rx_buf = val; |
321 | spi_imx->rx_buf += sizeof(u32); | |
322 | } | |
2ca300ac MC |
323 | |
324 | spi_imx->remainder -= sizeof(u32); | |
1673c81d | 325 | } |
326 | ||
327 | static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) | |
328 | { | |
2ca300ac MC |
329 | int unaligned; |
330 | u32 val; | |
1673c81d | 331 | |
2ca300ac MC |
332 | unaligned = spi_imx->remainder % 4; |
333 | ||
334 | if (!unaligned) { | |
1673c81d | 335 | spi_imx_buf_rx_swap_u32(spi_imx); |
336 | return; | |
337 | } | |
338 | ||
2ca300ac | 339 | if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { |
1673c81d | 340 | spi_imx_buf_rx_u16(spi_imx); |
2ca300ac MC |
341 | return; |
342 | } | |
343 | ||
344 | val = readl(spi_imx->base + MXC_CSPIRXDATA); | |
345 | ||
346 | while (unaligned--) { | |
347 | if (spi_imx->rx_buf) { | |
348 | *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; | |
349 | spi_imx->rx_buf++; | |
350 | } | |
351 | spi_imx->remainder--; | |
352 | } | |
1673c81d | 353 | } |
354 | ||
355 | static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) | |
356 | { | |
357 | u32 val = 0; | |
5904c9d3 | 358 | #ifdef __LITTLE_ENDIAN |
1673c81d | 359 | unsigned int bytes_per_word; |
5904c9d3 | 360 | #endif |
1673c81d | 361 | |
362 | if (spi_imx->tx_buf) { | |
363 | val = *(u32 *)spi_imx->tx_buf; | |
1673c81d | 364 | spi_imx->tx_buf += sizeof(u32); |
365 | } | |
366 | ||
367 | spi_imx->count -= sizeof(u32); | |
368 | #ifdef __LITTLE_ENDIAN | |
369 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
370 | ||
371 | if (bytes_per_word == 1) | |
dae336d0 | 372 | swab32s(&val); |
1673c81d | 373 | else if (bytes_per_word == 2) |
baaadffe | 374 | swahw32s(&val); |
1673c81d | 375 | #endif |
376 | writel(val, spi_imx->base + MXC_CSPITXDATA); | |
377 | } | |
378 | ||
379 | static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) | |
380 | { | |
2ca300ac MC |
381 | int unaligned; |
382 | u32 val = 0; | |
1673c81d | 383 | |
2ca300ac | 384 | unaligned = spi_imx->count % 4; |
1673c81d | 385 | |
2ca300ac MC |
386 | if (!unaligned) { |
387 | spi_imx_buf_tx_swap_u32(spi_imx); | |
388 | return; | |
1673c81d | 389 | } |
390 | ||
2ca300ac MC |
391 | if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { |
392 | spi_imx_buf_tx_u16(spi_imx); | |
1673c81d | 393 | return; |
394 | } | |
395 | ||
2ca300ac MC |
396 | while (unaligned--) { |
397 | if (spi_imx->tx_buf) { | |
398 | val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); | |
399 | spi_imx->tx_buf++; | |
400 | } | |
401 | spi_imx->count--; | |
402 | } | |
1673c81d | 403 | |
2ca300ac | 404 | writel(val, spi_imx->base + MXC_CSPITXDATA); |
1673c81d | 405 | } |
406 | ||
756d5bf0 | 407 | static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx) |
71abd290 | 408 | { |
409 | u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); | |
410 | ||
411 | if (spi_imx->rx_buf) { | |
756d5bf0 | 412 | int n_bytes = spi_imx->target_burst % sizeof(val); |
71abd290 | 413 | |
414 | if (!n_bytes) | |
415 | n_bytes = sizeof(val); | |
416 | ||
417 | memcpy(spi_imx->rx_buf, | |
418 | ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); | |
419 | ||
420 | spi_imx->rx_buf += n_bytes; | |
756d5bf0 | 421 | spi_imx->target_burst -= n_bytes; |
71abd290 | 422 | } |
2ca300ac MC |
423 | |
424 | spi_imx->remainder -= sizeof(u32); | |
71abd290 | 425 | } |
426 | ||
756d5bf0 | 427 | static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx) |
71abd290 | 428 | { |
429 | u32 val = 0; | |
430 | int n_bytes = spi_imx->count % sizeof(val); | |
431 | ||
432 | if (!n_bytes) | |
433 | n_bytes = sizeof(val); | |
434 | ||
435 | if (spi_imx->tx_buf) { | |
436 | memcpy(((u8 *)&val) + sizeof(val) - n_bytes, | |
437 | spi_imx->tx_buf, n_bytes); | |
438 | val = cpu_to_be32(val); | |
439 | spi_imx->tx_buf += n_bytes; | |
440 | } | |
441 | ||
442 | spi_imx->count -= n_bytes; | |
443 | ||
444 | writel(val, spi_imx->base + MXC_CSPITXDATA); | |
445 | } | |
446 | ||
0b599603 | 447 | /* MX51 eCSPI */ |
6aa800ca SH |
448 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
449 | unsigned int fspi, unsigned int *fres) | |
0b599603 UKK |
450 | { |
451 | /* | |
452 | * there are two 4-bit dividers, the pre-divider divides by | |
453 | * $pre, the post-divider by 2^$post | |
454 | */ | |
455 | unsigned int pre, post; | |
6aa800ca | 456 | unsigned int fin = spi_imx->spi_clk; |
0b599603 | 457 | |
db2d2dc9 | 458 | fspi = min(fspi, fin); |
0b599603 UKK |
459 | |
460 | post = fls(fin) - fls(fspi); | |
461 | if (fin > fspi << post) | |
462 | post++; | |
463 | ||
464 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
465 | ||
466 | post = max(4U, post) - 4; | |
467 | if (unlikely(post > 0xf)) { | |
6aa800ca SH |
468 | dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", |
469 | fspi, fin); | |
0b599603 UKK |
470 | return 0xff; |
471 | } | |
472 | ||
473 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
474 | ||
6aa800ca | 475 | dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", |
0b599603 | 476 | __func__, fin, fspi, post, pre); |
6fd8b850 MV |
477 | |
478 | /* Resulting frequency for the SCLK line. */ | |
479 | *fres = (fin / (pre + 1)) >> post; | |
480 | ||
66de757c SG |
481 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
482 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
483 | } |
484 | ||
f989bc69 | 485 | static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 | 486 | { |
1a23461a | 487 | unsigned int val = 0; |
0b599603 UKK |
488 | |
489 | if (enable & MXC_INT_TE) | |
66de757c | 490 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
491 | |
492 | if (enable & MXC_INT_RR) | |
66de757c | 493 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 494 | |
71abd290 | 495 | if (enable & MXC_INT_RDR) |
496 | val |= MX51_ECSPI_INT_RDREN; | |
497 | ||
66de757c | 498 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
499 | } |
500 | ||
f989bc69 | 501 | static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 | 502 | { |
b03c3884 | 503 | u32 reg; |
f62caccd | 504 | |
b03c3884 SH |
505 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
506 | reg |= MX51_ECSPI_CTRL_XCH; | |
66de757c | 507 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); |
0b599603 UKK |
508 | } |
509 | ||
71abd290 | 510 | static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) |
511 | { | |
512 | u32 ctrl; | |
513 | ||
514 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | |
515 | ctrl &= ~MX51_ECSPI_CTRL_ENABLE; | |
516 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
517 | } | |
518 | ||
a34e0353 RV |
519 | static int mx51_ecspi_channel(const struct spi_device *spi) |
520 | { | |
521 | if (!spi_get_csgpiod(spi, 0)) | |
522 | return spi_get_chipselect(spi, 0); | |
523 | return spi->controller->unused_native_cs; | |
524 | } | |
525 | ||
e697271c UKK |
526 | static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, |
527 | struct spi_message *msg) | |
528 | { | |
00b80ac9 | 529 | struct spi_device *spi = msg->spi; |
53ca18ac | 530 | struct spi_transfer *xfer; |
793c7f92 | 531 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE; |
53ca18ac | 532 | u32 min_speed_hz = ~0U; |
135cbd37 | 533 | u32 testreg, delay; |
793c7f92 | 534 | u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); |
184434fc | 535 | u32 current_cfg = cfg; |
a34e0353 | 536 | int channel = mx51_ecspi_channel(spi); |
0b599603 | 537 | |
756d5bf0 YY |
538 | /* set Host or Target mode */ |
539 | if (spi_imx->target_mode) | |
71abd290 | 540 | ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; |
541 | else | |
542 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; | |
0b599603 | 543 | |
f72efa7e LM |
544 | /* |
545 | * Enable SPI_RDY handling (falling edge/level triggered). | |
546 | */ | |
547 | if (spi->mode & SPI_READY) | |
548 | ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); | |
549 | ||
0b599603 | 550 | /* set chip select to use */ |
a34e0353 | 551 | ctrl |= MX51_ECSPI_CTRL_CS(channel); |
0b599603 | 552 | |
00b80ac9 UKK |
553 | /* |
554 | * The ctrl register must be written first, with the EN bit set other | |
555 | * registers must not be written to. | |
556 | */ | |
557 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
558 | ||
559 | testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); | |
560 | if (spi->mode & SPI_LOOP) | |
561 | testreg |= MX51_ECSPI_TESTREG_LBC; | |
71abd290 | 562 | else |
00b80ac9 UKK |
563 | testreg &= ~MX51_ECSPI_TESTREG_LBC; |
564 | writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); | |
0b599603 | 565 | |
71abd290 | 566 | /* |
756d5bf0 | 567 | * eCSPI burst completion by Chip Select signal in Target mode |
71abd290 | 568 | * is not functional for imx53 Soc, config SPI burst completed when |
569 | * BURST_LENGTH + 1 bits are received | |
570 | */ | |
756d5bf0 | 571 | if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) |
a34e0353 | 572 | cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel); |
71abd290 | 573 | else |
a34e0353 | 574 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel); |
0b599603 | 575 | |
c0c7a5d7 | 576 | if (spi->mode & SPI_CPOL) { |
a34e0353 RV |
577 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel); |
578 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel); | |
793c7f92 | 579 | } else { |
a34e0353 RV |
580 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel); |
581 | cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel); | |
c09b890b | 582 | } |
00b80ac9 | 583 | |
6a983ff5 | 584 | if (spi->mode & SPI_MOSI_IDLE_LOW) |
a34e0353 | 585 | cfg |= MX51_ECSPI_CONFIG_DATACTL(channel); |
6a983ff5 | 586 | else |
a34e0353 | 587 | cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel); |
6a983ff5 | 588 | |
c0c7a5d7 | 589 | if (spi->mode & SPI_CS_HIGH) |
a34e0353 | 590 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel); |
793c7f92 | 591 | else |
a34e0353 | 592 | cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel); |
0b599603 | 593 | |
184434fc MKB |
594 | if (cfg == current_cfg) |
595 | return 0; | |
596 | ||
00b80ac9 | 597 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); |
b03c3884 | 598 | |
135cbd37 MV |
599 | /* |
600 | * Wait until the changes in the configuration register CONFIGREG | |
601 | * propagate into the hardware. It takes exactly one tick of the | |
602 | * SCLK clock, but we will wait two SCLK clock just to be sure. The | |
603 | * effect of the delay it takes for the hardware to apply changes | |
604 | * is noticable if the SCLK clock run very slow. In such a case, if | |
605 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might | |
606 | * be asserted before the SCLK polarity changes, which would disrupt | |
607 | * the SPI communication as the device on the other end would consider | |
608 | * the change of SCLK polarity as a clock tick already. | |
53ca18ac | 609 | * |
307c897d | 610 | * Because spi_imx->spi_bus_clk is only set in prepare_message |
53ca18ac MV |
611 | * callback, iterate over all the transfers in spi_message, find the |
612 | * one with lowest bus frequency, and use that bus frequency for the | |
613 | * delay calculation. In case all transfers have speed_hz == 0, then | |
614 | * min_speed_hz is ~0 and the resulting delay is zero. | |
135cbd37 | 615 | */ |
53ca18ac MV |
616 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
617 | if (!xfer->speed_hz) | |
618 | continue; | |
619 | min_speed_hz = min(xfer->speed_hz, min_speed_hz); | |
620 | } | |
621 | ||
622 | delay = (2 * 1000000) / min_speed_hz; | |
36c2530e | 623 | if (likely(delay < 10)) /* SCLK is faster than 200 kHz */ |
135cbd37 MV |
624 | udelay(delay); |
625 | else /* SCLK is _very_ slow */ | |
626 | usleep_range(delay, delay + 10); | |
627 | ||
00b80ac9 UKK |
628 | return 0; |
629 | } | |
f677f17c | 630 | |
79422ed9 BS |
631 | static void mx51_configure_cpha(struct spi_imx_data *spi_imx, |
632 | struct spi_device *spi) | |
633 | { | |
634 | bool cpha = (spi->mode & SPI_CPHA); | |
635 | bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; | |
636 | u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); | |
a34e0353 | 637 | int channel = mx51_ecspi_channel(spi); |
79422ed9 BS |
638 | |
639 | /* Flip cpha logical value iff flip_cpha */ | |
640 | cpha ^= flip_cpha; | |
641 | ||
642 | if (cpha) | |
a34e0353 | 643 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel); |
79422ed9 | 644 | else |
a34e0353 | 645 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel); |
79422ed9 BS |
646 | |
647 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); | |
648 | } | |
649 | ||
1d374703 | 650 | static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, |
4df2f5e1 | 651 | struct spi_device *spi) |
00b80ac9 | 652 | { |
00b80ac9 | 653 | u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); |
135cbd37 | 654 | u32 clk; |
00b80ac9 UKK |
655 | |
656 | /* Clear BL field and set the right value */ | |
657 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | |
756d5bf0 YY |
658 | if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) |
659 | ctrl |= (spi_imx->target_burst * 8 - 1) | |
00b80ac9 | 660 | << MX51_ECSPI_CTRL_BL_OFFSET; |
15a6af94 | 661 | else { |
e9b220ae BB |
662 | if (spi_imx->usedma) { |
663 | ctrl |= (spi_imx->bits_per_word * | |
664 | spi_imx_bytes_per_word(spi_imx->bits_per_word) - 1) | |
15a6af94 | 665 | << MX51_ECSPI_CTRL_BL_OFFSET; |
e9b220ae BB |
666 | } else { |
667 | if (spi_imx->count >= MX51_ECSPI_CTRL_MAX_BURST) | |
668 | ctrl |= (MX51_ECSPI_CTRL_MAX_BURST - 1) | |
669 | << MX51_ECSPI_CTRL_BL_OFFSET; | |
670 | else | |
671 | ctrl |= (spi_imx->count * spi_imx->bits_per_word - 1) | |
672 | << MX51_ECSPI_CTRL_BL_OFFSET; | |
673 | } | |
15a6af94 | 674 | } |
9f6aa42b | 675 | |
00b80ac9 UKK |
676 | /* set clock speed */ |
677 | ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | | |
678 | 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); | |
4df2f5e1 | 679 | ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); |
00b80ac9 UKK |
680 | spi_imx->spi_bus_clk = clk; |
681 | ||
79422ed9 BS |
682 | mx51_configure_cpha(spi_imx, spi); |
683 | ||
8eb1252b RG |
684 | /* |
685 | * ERR009165: work in XHC mode instead of SMC as PIO on the chips | |
686 | * before i.mx6ul. | |
687 | */ | |
688 | if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) | |
00b80ac9 | 689 | ctrl |= MX51_ECSPI_CTRL_SMC; |
8eb1252b RG |
690 | else |
691 | ctrl &= ~MX51_ECSPI_CTRL_SMC; | |
00b80ac9 UKK |
692 | |
693 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
0b599603 | 694 | |
987a2dfe RG |
695 | return 0; |
696 | } | |
697 | ||
698 | static void mx51_setup_wml(struct spi_imx_data *spi_imx) | |
699 | { | |
8eb1252b RG |
700 | u32 tx_wml = 0; |
701 | ||
702 | if (spi_imx->devtype_data->tx_glitch_fixed) | |
703 | tx_wml = spi_imx->wml; | |
f62caccd RG |
704 | /* |
705 | * Configure the DMA register: setup the watermark | |
706 | * and enable DMA request. | |
707 | */ | |
5ba5a373 | 708 | writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | |
8eb1252b | 709 | MX51_ECSPI_DMA_TX_WML(tx_wml) | |
d629c2a0 | 710 | MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | |
2b0fd069 SH |
711 | MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | |
712 | MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); | |
0b599603 UKK |
713 | } |
714 | ||
f989bc69 | 715 | static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 716 | { |
66de757c | 717 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
718 | } |
719 | ||
f989bc69 | 720 | static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
721 | { |
722 | /* drain receive buffer */ | |
66de757c | 723 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
724 | readl(spi_imx->base + MXC_CSPIRXDATA); |
725 | } | |
726 | ||
b5f3294f SH |
727 | #define MX31_INTREG_TEEN (1 << 0) |
728 | #define MX31_INTREG_RREN (1 << 3) | |
729 | ||
730 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
756d5bf0 | 731 | #define MX31_CSPICTRL_HOST (1 << 1) |
b5f3294f | 732 | #define MX31_CSPICTRL_XCH (1 << 2) |
2dd33f9c | 733 | #define MX31_CSPICTRL_SMC (1 << 3) |
b5f3294f SH |
734 | #define MX31_CSPICTRL_POL (1 << 4) |
735 | #define MX31_CSPICTRL_PHA (1 << 5) | |
736 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
737 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
738 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
739 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
740 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
741 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
742 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
743 | ||
2dd33f9c MK |
744 | #define MX31_CSPI_DMAREG 0x10 |
745 | #define MX31_DMAREG_RH_DEN (1<<4) | |
746 | #define MX31_DMAREG_TH_DEN (1<<1) | |
747 | ||
b5f3294f SH |
748 | #define MX31_CSPISTATUS 0x14 |
749 | #define MX31_STATUS_RR (1 << 3) | |
750 | ||
15ca9215 MK |
751 | #define MX31_CSPI_TESTREG 0x1C |
752 | #define MX31_TEST_LBC (1 << 14) | |
753 | ||
b5f3294f SH |
754 | /* These functions also work for the i.MX35, but be aware that |
755 | * the i.MX35 has a slightly different register layout for bits | |
756 | * we do not use here. | |
757 | */ | |
f989bc69 | 758 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
759 | { |
760 | unsigned int val = 0; | |
761 | ||
762 | if (enable & MXC_INT_TE) | |
763 | val |= MX31_INTREG_TEEN; | |
764 | if (enable & MXC_INT_RR) | |
765 | val |= MX31_INTREG_RREN; | |
766 | ||
6cdeb002 | 767 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
768 | } |
769 | ||
f989bc69 | 770 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
771 | { |
772 | unsigned int reg; | |
773 | ||
6cdeb002 | 774 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 775 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 776 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
777 | } |
778 | ||
e697271c UKK |
779 | static int mx31_prepare_message(struct spi_imx_data *spi_imx, |
780 | struct spi_message *msg) | |
781 | { | |
782 | return 0; | |
783 | } | |
784 | ||
1d374703 | 785 | static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, |
4df2f5e1 | 786 | struct spi_device *spi) |
1723e66b | 787 | { |
756d5bf0 | 788 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST; |
2636ba8f | 789 | unsigned int clk; |
1723e66b | 790 | |
4df2f5e1 | 791 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << |
1723e66b | 792 | MX31_CSPICTRL_DR_SHIFT; |
2636ba8f | 793 | spi_imx->spi_bus_clk = clk; |
1723e66b | 794 | |
04ee5854 | 795 | if (is_imx35_cspi(spi_imx)) { |
d52345b6 | 796 | reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; |
2a64a90a SG |
797 | reg |= MX31_CSPICTRL_SSCTL; |
798 | } else { | |
d52345b6 | 799 | reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; |
2a64a90a | 800 | } |
1723e66b | 801 | |
c0c7a5d7 | 802 | if (spi->mode & SPI_CPHA) |
1723e66b | 803 | reg |= MX31_CSPICTRL_PHA; |
c0c7a5d7 | 804 | if (spi->mode & SPI_CPOL) |
1723e66b | 805 | reg |= MX31_CSPICTRL_POL; |
c0c7a5d7 | 806 | if (spi->mode & SPI_CS_HIGH) |
1723e66b | 807 | reg |= MX31_CSPICTRL_SSPOL; |
9e264f3f AKMA |
808 | if (!spi_get_csgpiod(spi, 0)) |
809 | reg |= (spi_get_chipselect(spi, 0)) << | |
04ee5854 SG |
810 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
811 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b | 812 | |
2dd33f9c MK |
813 | if (spi_imx->usedma) |
814 | reg |= MX31_CSPICTRL_SMC; | |
815 | ||
1723e66b UKK |
816 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
817 | ||
15ca9215 MK |
818 | reg = readl(spi_imx->base + MX31_CSPI_TESTREG); |
819 | if (spi->mode & SPI_LOOP) | |
820 | reg |= MX31_TEST_LBC; | |
821 | else | |
822 | reg &= ~MX31_TEST_LBC; | |
823 | writel(reg, spi_imx->base + MX31_CSPI_TESTREG); | |
824 | ||
2dd33f9c | 825 | if (spi_imx->usedma) { |
30d67142 UKK |
826 | /* |
827 | * configure DMA requests when RXFIFO is half full and | |
828 | * when TXFIFO is half empty | |
829 | */ | |
2dd33f9c MK |
830 | writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, |
831 | spi_imx->base + MX31_CSPI_DMAREG); | |
832 | } | |
833 | ||
1723e66b UKK |
834 | return 0; |
835 | } | |
836 | ||
f989bc69 | 837 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 838 | { |
6cdeb002 | 839 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
840 | } |
841 | ||
f989bc69 | 842 | static void mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
843 | { |
844 | /* drain receive buffer */ | |
2a64a90a | 845 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
846 | readl(spi_imx->base + MXC_CSPIRXDATA); |
847 | } | |
848 | ||
3451fb15 SG |
849 | #define MX21_INTREG_RR (1 << 4) |
850 | #define MX21_INTREG_TEEN (1 << 9) | |
851 | #define MX21_INTREG_RREN (1 << 13) | |
852 | ||
853 | #define MX21_CSPICTRL_POL (1 << 5) | |
854 | #define MX21_CSPICTRL_PHA (1 << 6) | |
855 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
856 | #define MX21_CSPICTRL_XCH (1 << 9) | |
857 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
756d5bf0 | 858 | #define MX21_CSPICTRL_HOST (1 << 11) |
3451fb15 SG |
859 | #define MX21_CSPICTRL_DR_SHIFT 14 |
860 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
861 | ||
f989bc69 | 862 | static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
863 | { |
864 | unsigned int val = 0; | |
865 | ||
866 | if (enable & MXC_INT_TE) | |
3451fb15 | 867 | val |= MX21_INTREG_TEEN; |
b5f3294f | 868 | if (enable & MXC_INT_RR) |
3451fb15 | 869 | val |= MX21_INTREG_RREN; |
b5f3294f | 870 | |
6cdeb002 | 871 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
872 | } |
873 | ||
f989bc69 | 874 | static void mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
875 | { |
876 | unsigned int reg; | |
877 | ||
6cdeb002 | 878 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 879 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 880 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
881 | } |
882 | ||
e697271c UKK |
883 | static int mx21_prepare_message(struct spi_imx_data *spi_imx, |
884 | struct spi_message *msg) | |
885 | { | |
886 | return 0; | |
887 | } | |
888 | ||
1d374703 | 889 | static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, |
4df2f5e1 | 890 | struct spi_device *spi) |
b5f3294f | 891 | { |
756d5bf0 | 892 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST; |
04ee5854 | 893 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
32df9ff2 RB |
894 | unsigned int clk; |
895 | ||
4df2f5e1 | 896 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) |
32df9ff2 RB |
897 | << MX21_CSPICTRL_DR_SHIFT; |
898 | spi_imx->spi_bus_clk = clk; | |
b5f3294f | 899 | |
d52345b6 | 900 | reg |= spi_imx->bits_per_word - 1; |
b5f3294f | 901 | |
c0c7a5d7 | 902 | if (spi->mode & SPI_CPHA) |
3451fb15 | 903 | reg |= MX21_CSPICTRL_PHA; |
c0c7a5d7 | 904 | if (spi->mode & SPI_CPOL) |
3451fb15 | 905 | reg |= MX21_CSPICTRL_POL; |
c0c7a5d7 | 906 | if (spi->mode & SPI_CS_HIGH) |
3451fb15 | 907 | reg |= MX21_CSPICTRL_SSPOL; |
9e264f3f AKMA |
908 | if (!spi_get_csgpiod(spi, 0)) |
909 | reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT; | |
b5f3294f | 910 | |
6cdeb002 | 911 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
912 | |
913 | return 0; | |
914 | } | |
915 | ||
f989bc69 | 916 | static int mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 917 | { |
3451fb15 | 918 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
919 | } |
920 | ||
f989bc69 | 921 | static void mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
922 | { |
923 | writel(1, spi_imx->base + MXC_RESET); | |
924 | } | |
925 | ||
b5f3294f SH |
926 | #define MX1_INTREG_RR (1 << 3) |
927 | #define MX1_INTREG_TEEN (1 << 8) | |
928 | #define MX1_INTREG_RREN (1 << 11) | |
929 | ||
930 | #define MX1_CSPICTRL_POL (1 << 4) | |
931 | #define MX1_CSPICTRL_PHA (1 << 5) | |
932 | #define MX1_CSPICTRL_XCH (1 << 8) | |
933 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
756d5bf0 | 934 | #define MX1_CSPICTRL_HOST (1 << 10) |
b5f3294f SH |
935 | #define MX1_CSPICTRL_DR_SHIFT 13 |
936 | ||
f989bc69 | 937 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
938 | { |
939 | unsigned int val = 0; | |
940 | ||
941 | if (enable & MXC_INT_TE) | |
942 | val |= MX1_INTREG_TEEN; | |
943 | if (enable & MXC_INT_RR) | |
944 | val |= MX1_INTREG_RREN; | |
945 | ||
6cdeb002 | 946 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
947 | } |
948 | ||
f989bc69 | 949 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
950 | { |
951 | unsigned int reg; | |
952 | ||
6cdeb002 | 953 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 954 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 955 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
956 | } |
957 | ||
e697271c UKK |
958 | static int mx1_prepare_message(struct spi_imx_data *spi_imx, |
959 | struct spi_message *msg) | |
960 | { | |
961 | return 0; | |
962 | } | |
963 | ||
1d374703 | 964 | static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, |
4df2f5e1 | 965 | struct spi_device *spi) |
b5f3294f | 966 | { |
756d5bf0 | 967 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST; |
2636ba8f | 968 | unsigned int clk; |
b5f3294f | 969 | |
4df2f5e1 | 970 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << |
b5f3294f | 971 | MX1_CSPICTRL_DR_SHIFT; |
2636ba8f MK |
972 | spi_imx->spi_bus_clk = clk; |
973 | ||
d52345b6 | 974 | reg |= spi_imx->bits_per_word - 1; |
b5f3294f | 975 | |
c0c7a5d7 | 976 | if (spi->mode & SPI_CPHA) |
b5f3294f | 977 | reg |= MX1_CSPICTRL_PHA; |
c0c7a5d7 | 978 | if (spi->mode & SPI_CPOL) |
b5f3294f SH |
979 | reg |= MX1_CSPICTRL_POL; |
980 | ||
6cdeb002 | 981 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
982 | |
983 | return 0; | |
984 | } | |
985 | ||
f989bc69 | 986 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 987 | { |
6cdeb002 | 988 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
989 | } |
990 | ||
f989bc69 | 991 | static void mx1_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
992 | { |
993 | writel(1, spi_imx->base + MXC_RESET); | |
994 | } | |
995 | ||
04ee5854 SG |
996 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
997 | .intctrl = mx1_intctrl, | |
e697271c | 998 | .prepare_message = mx1_prepare_message, |
1d374703 | 999 | .prepare_transfer = mx1_prepare_transfer, |
04ee5854 SG |
1000 | .trigger = mx1_trigger, |
1001 | .rx_available = mx1_rx_available, | |
1002 | .reset = mx1_reset, | |
fd8d4e2d | 1003 | .fifo_size = 8, |
1004 | .has_dmamode = false, | |
1673c81d | 1005 | .dynamic_burst = false, |
756d5bf0 | 1006 | .has_targetmode = false, |
04ee5854 SG |
1007 | .devtype = IMX1_CSPI, |
1008 | }; | |
1009 | ||
1010 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
1011 | .intctrl = mx21_intctrl, | |
e697271c | 1012 | .prepare_message = mx21_prepare_message, |
1d374703 | 1013 | .prepare_transfer = mx21_prepare_transfer, |
04ee5854 SG |
1014 | .trigger = mx21_trigger, |
1015 | .rx_available = mx21_rx_available, | |
1016 | .reset = mx21_reset, | |
fd8d4e2d | 1017 | .fifo_size = 8, |
1018 | .has_dmamode = false, | |
1673c81d | 1019 | .dynamic_burst = false, |
756d5bf0 | 1020 | .has_targetmode = false, |
04ee5854 SG |
1021 | .devtype = IMX21_CSPI, |
1022 | }; | |
1023 | ||
1024 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
1025 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
1026 | .intctrl = mx21_intctrl, | |
e697271c | 1027 | .prepare_message = mx21_prepare_message, |
1d374703 | 1028 | .prepare_transfer = mx21_prepare_transfer, |
04ee5854 SG |
1029 | .trigger = mx21_trigger, |
1030 | .rx_available = mx21_rx_available, | |
1031 | .reset = mx21_reset, | |
fd8d4e2d | 1032 | .fifo_size = 8, |
1033 | .has_dmamode = false, | |
1673c81d | 1034 | .dynamic_burst = false, |
756d5bf0 | 1035 | .has_targetmode = false, |
04ee5854 SG |
1036 | .devtype = IMX27_CSPI, |
1037 | }; | |
1038 | ||
1039 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
1040 | .intctrl = mx31_intctrl, | |
e697271c | 1041 | .prepare_message = mx31_prepare_message, |
1d374703 | 1042 | .prepare_transfer = mx31_prepare_transfer, |
04ee5854 SG |
1043 | .trigger = mx31_trigger, |
1044 | .rx_available = mx31_rx_available, | |
1045 | .reset = mx31_reset, | |
fd8d4e2d | 1046 | .fifo_size = 8, |
1047 | .has_dmamode = false, | |
1673c81d | 1048 | .dynamic_burst = false, |
756d5bf0 | 1049 | .has_targetmode = false, |
04ee5854 SG |
1050 | .devtype = IMX31_CSPI, |
1051 | }; | |
1052 | ||
1053 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
1054 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
1055 | .intctrl = mx31_intctrl, | |
e697271c | 1056 | .prepare_message = mx31_prepare_message, |
1d374703 | 1057 | .prepare_transfer = mx31_prepare_transfer, |
04ee5854 SG |
1058 | .trigger = mx31_trigger, |
1059 | .rx_available = mx31_rx_available, | |
1060 | .reset = mx31_reset, | |
fd8d4e2d | 1061 | .fifo_size = 8, |
1062 | .has_dmamode = true, | |
1673c81d | 1063 | .dynamic_burst = false, |
756d5bf0 | 1064 | .has_targetmode = false, |
04ee5854 SG |
1065 | .devtype = IMX35_CSPI, |
1066 | }; | |
1067 | ||
1068 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
1069 | .intctrl = mx51_ecspi_intctrl, | |
e697271c | 1070 | .prepare_message = mx51_ecspi_prepare_message, |
1d374703 | 1071 | .prepare_transfer = mx51_ecspi_prepare_transfer, |
04ee5854 SG |
1072 | .trigger = mx51_ecspi_trigger, |
1073 | .rx_available = mx51_ecspi_rx_available, | |
1074 | .reset = mx51_ecspi_reset, | |
987a2dfe | 1075 | .setup_wml = mx51_setup_wml, |
fd8d4e2d | 1076 | .fifo_size = 64, |
1077 | .has_dmamode = true, | |
1673c81d | 1078 | .dynamic_burst = true, |
756d5bf0 | 1079 | .has_targetmode = true, |
71abd290 | 1080 | .disable = mx51_ecspi_disable, |
04ee5854 SG |
1081 | .devtype = IMX51_ECSPI, |
1082 | }; | |
1083 | ||
26e4bb86 | 1084 | static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { |
1085 | .intctrl = mx51_ecspi_intctrl, | |
e697271c | 1086 | .prepare_message = mx51_ecspi_prepare_message, |
1d374703 | 1087 | .prepare_transfer = mx51_ecspi_prepare_transfer, |
26e4bb86 | 1088 | .trigger = mx51_ecspi_trigger, |
1089 | .rx_available = mx51_ecspi_rx_available, | |
1090 | .reset = mx51_ecspi_reset, | |
1091 | .fifo_size = 64, | |
1092 | .has_dmamode = true, | |
756d5bf0 | 1093 | .has_targetmode = true, |
71abd290 | 1094 | .disable = mx51_ecspi_disable, |
26e4bb86 | 1095 | .devtype = IMX53_ECSPI, |
1096 | }; | |
1097 | ||
8eb1252b RG |
1098 | static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = { |
1099 | .intctrl = mx51_ecspi_intctrl, | |
1100 | .prepare_message = mx51_ecspi_prepare_message, | |
1101 | .prepare_transfer = mx51_ecspi_prepare_transfer, | |
1102 | .trigger = mx51_ecspi_trigger, | |
1103 | .rx_available = mx51_ecspi_rx_available, | |
1104 | .reset = mx51_ecspi_reset, | |
1105 | .setup_wml = mx51_setup_wml, | |
1106 | .fifo_size = 64, | |
1107 | .has_dmamode = true, | |
1108 | .dynamic_burst = true, | |
756d5bf0 | 1109 | .has_targetmode = true, |
8eb1252b RG |
1110 | .tx_glitch_fixed = true, |
1111 | .disable = mx51_ecspi_disable, | |
1112 | .devtype = IMX51_ECSPI, | |
1113 | }; | |
1114 | ||
22a85e4c SG |
1115 | static const struct of_device_id spi_imx_dt_ids[] = { |
1116 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
1117 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
1118 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
1119 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
1120 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
1121 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
26e4bb86 | 1122 | { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, |
8eb1252b | 1123 | { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, }, |
22a85e4c SG |
1124 | { /* sentinel */ } |
1125 | }; | |
27743e0b | 1126 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
22a85e4c | 1127 | |
2ca300ac MC |
1128 | static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) |
1129 | { | |
1130 | u32 ctrl; | |
1131 | ||
1132 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | |
1133 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | |
1134 | ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); | |
1135 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
1136 | } | |
1137 | ||
6cdeb002 | 1138 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 1139 | { |
bd961699 | 1140 | unsigned int burst_len; |
2ca300ac | 1141 | |
2ca300ac MC |
1142 | /* |
1143 | * Reload the FIFO when the remaining bytes to be transferred in the | |
1144 | * current burst is 0. This only applies when bits_per_word is a | |
1145 | * multiple of 8. | |
1146 | */ | |
1147 | if (!spi_imx->remainder) { | |
1148 | if (spi_imx->dynamic_burst) { | |
1149 | ||
1150 | /* We need to deal unaligned data first */ | |
1151 | burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; | |
1152 | ||
1153 | if (!burst_len) | |
1154 | burst_len = MX51_ECSPI_CTRL_MAX_BURST; | |
1155 | ||
1156 | spi_imx_set_burst_len(spi_imx, burst_len * 8); | |
1157 | ||
1158 | spi_imx->remainder = burst_len; | |
1159 | } else { | |
bd961699 | 1160 | spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); |
2ca300ac MC |
1161 | } |
1162 | } | |
1163 | ||
fd8d4e2d | 1164 | while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { |
6cdeb002 | 1165 | if (!spi_imx->count) |
b5f3294f | 1166 | break; |
2ca300ac | 1167 | if (spi_imx->dynamic_burst && |
bd961699 | 1168 | spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) |
1673c81d | 1169 | break; |
6cdeb002 UKK |
1170 | spi_imx->tx(spi_imx); |
1171 | spi_imx->txfifo++; | |
b5f3294f SH |
1172 | } |
1173 | ||
756d5bf0 | 1174 | if (!spi_imx->target_mode) |
71abd290 | 1175 | spi_imx->devtype_data->trigger(spi_imx); |
b5f3294f SH |
1176 | } |
1177 | ||
6cdeb002 | 1178 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 1179 | { |
6cdeb002 | 1180 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 1181 | |
71abd290 | 1182 | while (spi_imx->txfifo && |
1183 | spi_imx->devtype_data->rx_available(spi_imx)) { | |
6cdeb002 UKK |
1184 | spi_imx->rx(spi_imx); |
1185 | spi_imx->txfifo--; | |
b5f3294f SH |
1186 | } |
1187 | ||
6cdeb002 UKK |
1188 | if (spi_imx->count) { |
1189 | spi_imx_push(spi_imx); | |
b5f3294f SH |
1190 | return IRQ_HANDLED; |
1191 | } | |
1192 | ||
6cdeb002 | 1193 | if (spi_imx->txfifo) { |
b5f3294f SH |
1194 | /* No data left to push, but still waiting for rx data, |
1195 | * enable receive data available interrupt. | |
1196 | */ | |
edd501bb | 1197 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 1198 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
1199 | return IRQ_HANDLED; |
1200 | } | |
1201 | ||
edd501bb | 1202 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 1203 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
1204 | |
1205 | return IRQ_HANDLED; | |
1206 | } | |
1207 | ||
63cd96b7 | 1208 | static int spi_imx_dma_configure(struct spi_controller *controller) |
f12ae171 AB |
1209 | { |
1210 | int ret; | |
1211 | enum dma_slave_buswidth buswidth; | |
1212 | struct dma_slave_config rx = {}, tx = {}; | |
63cd96b7 | 1213 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); |
f12ae171 | 1214 | |
65017ee2 | 1215 | switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { |
f12ae171 AB |
1216 | case 4: |
1217 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1218 | break; | |
1219 | case 2: | |
1220 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1221 | break; | |
1222 | case 1: | |
1223 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1224 | break; | |
1225 | default: | |
1226 | return -EINVAL; | |
1227 | } | |
1228 | ||
1229 | tx.direction = DMA_MEM_TO_DEV; | |
1230 | tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; | |
1231 | tx.dst_addr_width = buswidth; | |
1232 | tx.dst_maxburst = spi_imx->wml; | |
63cd96b7 | 1233 | ret = dmaengine_slave_config(controller->dma_tx, &tx); |
f12ae171 AB |
1234 | if (ret) { |
1235 | dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); | |
1236 | return ret; | |
1237 | } | |
1238 | ||
1239 | rx.direction = DMA_DEV_TO_MEM; | |
1240 | rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; | |
1241 | rx.src_addr_width = buswidth; | |
1242 | rx.src_maxburst = spi_imx->wml; | |
63cd96b7 | 1243 | ret = dmaengine_slave_config(controller->dma_rx, &rx); |
f12ae171 AB |
1244 | if (ret) { |
1245 | dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); | |
1246 | return ret; | |
1247 | } | |
1248 | ||
f12ae171 AB |
1249 | return 0; |
1250 | } | |
1251 | ||
6cdeb002 | 1252 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
1253 | struct spi_transfer *t) |
1254 | { | |
63cd96b7 | 1255 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); |
b5f3294f | 1256 | |
abb1ff19 SH |
1257 | if (!t) |
1258 | return 0; | |
1259 | ||
4df2f5e1 CW |
1260 | if (!t->speed_hz) { |
1261 | if (!spi->max_speed_hz) { | |
1262 | dev_err(&spi->dev, "no speed_hz provided!\n"); | |
1263 | return -EINVAL; | |
1264 | } | |
1265 | dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); | |
1266 | spi_imx->spi_bus_clk = spi->max_speed_hz; | |
1267 | } else | |
1268 | spi_imx->spi_bus_clk = t->speed_hz; | |
1269 | ||
d52345b6 | 1270 | spi_imx->bits_per_word = t->bits_per_word; |
15a6af94 | 1271 | spi_imx->count = t->len; |
b5f3294f | 1272 | |
2801b2f5 MC |
1273 | /* |
1274 | * Initialize the functions for transfer. To transfer non byte-aligned | |
1275 | * words, we have to use multiple word-size bursts, we can't use | |
1276 | * dynamic_burst in that case. | |
1277 | */ | |
756d5bf0 | 1278 | if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode && |
6e95b23a | 1279 | !(spi->mode & SPI_CS_WORD) && |
2801b2f5 MC |
1280 | (spi_imx->bits_per_word == 8 || |
1281 | spi_imx->bits_per_word == 16 || | |
1282 | spi_imx->bits_per_word == 32)) { | |
1673c81d | 1283 | |
1673c81d | 1284 | spi_imx->rx = spi_imx_buf_rx_swap; |
1285 | spi_imx->tx = spi_imx_buf_tx_swap; | |
1286 | spi_imx->dynamic_burst = 1; | |
1673c81d | 1287 | |
6051426f | 1288 | } else { |
1673c81d | 1289 | if (spi_imx->bits_per_word <= 8) { |
1290 | spi_imx->rx = spi_imx_buf_rx_u8; | |
1291 | spi_imx->tx = spi_imx_buf_tx_u8; | |
1292 | } else if (spi_imx->bits_per_word <= 16) { | |
1293 | spi_imx->rx = spi_imx_buf_rx_u16; | |
1294 | spi_imx->tx = spi_imx_buf_tx_u16; | |
1295 | } else { | |
1296 | spi_imx->rx = spi_imx_buf_rx_u32; | |
1297 | spi_imx->tx = spi_imx_buf_tx_u32; | |
1298 | } | |
2ca300ac | 1299 | spi_imx->dynamic_burst = 0; |
24778be2 | 1300 | } |
e6a0a8bf | 1301 | |
307c897d | 1302 | if (spi_imx_can_dma(spi_imx->controller, spi, t)) |
e6a8b2cc | 1303 | spi_imx->usedma = true; |
c008a800 | 1304 | else |
e6a8b2cc | 1305 | spi_imx->usedma = false; |
c008a800 | 1306 | |
79422ed9 BS |
1307 | spi_imx->rx_only = ((t->tx_buf == NULL) |
1308 | || (t->tx_buf == spi->controller->dummy_tx)); | |
1309 | ||
756d5bf0 YY |
1310 | if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) { |
1311 | spi_imx->rx = mx53_ecspi_rx_target; | |
1312 | spi_imx->tx = mx53_ecspi_tx_target; | |
1313 | spi_imx->target_burst = t->len; | |
71abd290 | 1314 | } |
1315 | ||
4df2f5e1 | 1316 | spi_imx->devtype_data->prepare_transfer(spi_imx, spi); |
b5f3294f SH |
1317 | |
1318 | return 0; | |
1319 | } | |
1320 | ||
f62caccd RG |
1321 | static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) |
1322 | { | |
307c897d | 1323 | struct spi_controller *controller = spi_imx->controller; |
f62caccd | 1324 | |
63cd96b7 MKB |
1325 | if (controller->dma_rx) { |
1326 | dma_release_channel(controller->dma_rx); | |
1327 | controller->dma_rx = NULL; | |
f62caccd RG |
1328 | } |
1329 | ||
63cd96b7 MKB |
1330 | if (controller->dma_tx) { |
1331 | dma_release_channel(controller->dma_tx); | |
1332 | controller->dma_tx = NULL; | |
f62caccd | 1333 | } |
f62caccd RG |
1334 | } |
1335 | ||
1336 | static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, | |
63cd96b7 | 1337 | struct spi_controller *controller) |
f62caccd | 1338 | { |
f62caccd RG |
1339 | int ret; |
1340 | ||
fd8d4e2d | 1341 | spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; |
0dfbaa89 | 1342 | |
f62caccd | 1343 | /* Prepare for TX DMA: */ |
63cd96b7 MKB |
1344 | controller->dma_tx = dma_request_chan(dev, "tx"); |
1345 | if (IS_ERR(controller->dma_tx)) { | |
1346 | ret = PTR_ERR(controller->dma_tx); | |
3760047a | 1347 | dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); |
63cd96b7 | 1348 | controller->dma_tx = NULL; |
f62caccd RG |
1349 | goto err; |
1350 | } | |
1351 | ||
f62caccd | 1352 | /* Prepare for RX : */ |
63cd96b7 MKB |
1353 | controller->dma_rx = dma_request_chan(dev, "rx"); |
1354 | if (IS_ERR(controller->dma_rx)) { | |
1355 | ret = PTR_ERR(controller->dma_rx); | |
3760047a | 1356 | dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); |
63cd96b7 | 1357 | controller->dma_rx = NULL; |
f62caccd RG |
1358 | goto err; |
1359 | } | |
1360 | ||
f62caccd RG |
1361 | init_completion(&spi_imx->dma_rx_completion); |
1362 | init_completion(&spi_imx->dma_tx_completion); | |
63cd96b7 MKB |
1363 | controller->can_dma = spi_imx_can_dma; |
1364 | controller->max_dma_len = MAX_SDMA_BD_BYTES; | |
307c897d | 1365 | spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | |
63cd96b7 | 1366 | SPI_CONTROLLER_MUST_TX; |
f62caccd RG |
1367 | |
1368 | return 0; | |
1369 | err: | |
1370 | spi_imx_sdma_exit(spi_imx); | |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | static void spi_imx_dma_rx_callback(void *cookie) | |
1375 | { | |
1376 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
1377 | ||
1378 | complete(&spi_imx->dma_rx_completion); | |
1379 | } | |
1380 | ||
1381 | static void spi_imx_dma_tx_callback(void *cookie) | |
1382 | { | |
1383 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
1384 | ||
1385 | complete(&spi_imx->dma_tx_completion); | |
1386 | } | |
1387 | ||
4bfe927a AB |
1388 | static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) |
1389 | { | |
1390 | unsigned long timeout = 0; | |
1391 | ||
1392 | /* Time with actual data transfer and CS change delay related to HW */ | |
1393 | timeout = (8 + 4) * size / spi_imx->spi_bus_clk; | |
1394 | ||
1395 | /* Add extra second for scheduler related activities */ | |
1396 | timeout += 1; | |
1397 | ||
1398 | /* Double calculated timeout */ | |
1399 | return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); | |
1400 | } | |
1401 | ||
f62caccd RG |
1402 | static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
1403 | struct spi_transfer *transfer) | |
1404 | { | |
6b6192c0 | 1405 | struct dma_async_tx_descriptor *desc_tx, *desc_rx; |
4bfe927a | 1406 | unsigned long transfer_timeout; |
56536a7f | 1407 | unsigned long timeout; |
307c897d | 1408 | struct spi_controller *controller = spi_imx->controller; |
f62caccd | 1409 | struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; |
5ba5a373 RG |
1410 | struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); |
1411 | unsigned int bytes_per_word, i; | |
987a2dfe RG |
1412 | int ret; |
1413 | ||
5ba5a373 RG |
1414 | /* Get the right burst length from the last sg to ensure no tail data */ |
1415 | bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); | |
1416 | for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { | |
1417 | if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) | |
1418 | break; | |
1419 | } | |
1420 | /* Use 1 as wml in case no available burst length got */ | |
1421 | if (i == 0) | |
1422 | i = 1; | |
1423 | ||
1424 | spi_imx->wml = i; | |
1425 | ||
63cd96b7 | 1426 | ret = spi_imx_dma_configure(controller); |
987a2dfe | 1427 | if (ret) |
7a908832 | 1428 | goto dma_failure_no_start; |
987a2dfe | 1429 | |
5ba5a373 RG |
1430 | if (!spi_imx->devtype_data->setup_wml) { |
1431 | dev_err(spi_imx->dev, "No setup_wml()?\n"); | |
7a908832 RG |
1432 | ret = -EINVAL; |
1433 | goto dma_failure_no_start; | |
5ba5a373 | 1434 | } |
987a2dfe | 1435 | spi_imx->devtype_data->setup_wml(spi_imx); |
f62caccd | 1436 | |
6b6192c0 SH |
1437 | /* |
1438 | * The TX DMA setup starts the transfer, so make sure RX is configured | |
1439 | * before TX. | |
1440 | */ | |
63cd96b7 | 1441 | desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, |
6b6192c0 SH |
1442 | rx->sgl, rx->nents, DMA_DEV_TO_MEM, |
1443 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
7a908832 RG |
1444 | if (!desc_rx) { |
1445 | ret = -EINVAL; | |
1446 | goto dma_failure_no_start; | |
1447 | } | |
f62caccd | 1448 | |
6b6192c0 SH |
1449 | desc_rx->callback = spi_imx_dma_rx_callback; |
1450 | desc_rx->callback_param = (void *)spi_imx; | |
1451 | dmaengine_submit(desc_rx); | |
1452 | reinit_completion(&spi_imx->dma_rx_completion); | |
63cd96b7 | 1453 | dma_async_issue_pending(controller->dma_rx); |
f62caccd | 1454 | |
63cd96b7 | 1455 | desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, |
6b6192c0 SH |
1456 | tx->sgl, tx->nents, DMA_MEM_TO_DEV, |
1457 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1458 | if (!desc_tx) { | |
63cd96b7 MKB |
1459 | dmaengine_terminate_all(controller->dma_tx); |
1460 | dmaengine_terminate_all(controller->dma_rx); | |
6b6192c0 | 1461 | return -EINVAL; |
f62caccd RG |
1462 | } |
1463 | ||
6b6192c0 SH |
1464 | desc_tx->callback = spi_imx_dma_tx_callback; |
1465 | desc_tx->callback_param = (void *)spi_imx; | |
1466 | dmaengine_submit(desc_tx); | |
f62caccd | 1467 | reinit_completion(&spi_imx->dma_tx_completion); |
63cd96b7 | 1468 | dma_async_issue_pending(controller->dma_tx); |
f62caccd | 1469 | |
4bfe927a AB |
1470 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1471 | ||
f62caccd | 1472 | /* Wait SDMA to finish the data transfer.*/ |
56536a7f | 1473 | timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
4bfe927a | 1474 | transfer_timeout); |
56536a7f | 1475 | if (!timeout) { |
6aa800ca | 1476 | dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); |
63cd96b7 MKB |
1477 | dmaengine_terminate_all(controller->dma_tx); |
1478 | dmaengine_terminate_all(controller->dma_rx); | |
6b6192c0 | 1479 | return -ETIMEDOUT; |
f62caccd RG |
1480 | } |
1481 | ||
6b6192c0 SH |
1482 | timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, |
1483 | transfer_timeout); | |
1484 | if (!timeout) { | |
63cd96b7 | 1485 | dev_err(&controller->dev, "I/O Error in DMA RX\n"); |
6b6192c0 | 1486 | spi_imx->devtype_data->reset(spi_imx); |
63cd96b7 | 1487 | dmaengine_terminate_all(controller->dma_rx); |
6b6192c0 SH |
1488 | return -ETIMEDOUT; |
1489 | } | |
f62caccd | 1490 | |
307c897d | 1491 | return 0; |
7a908832 RG |
1492 | /* fallback to pio */ |
1493 | dma_failure_no_start: | |
1494 | transfer->error |= SPI_TRANS_FAIL_NO_START; | |
1495 | return ret; | |
f62caccd RG |
1496 | } |
1497 | ||
1498 | static int spi_imx_pio_transfer(struct spi_device *spi, | |
b5f3294f SH |
1499 | struct spi_transfer *transfer) |
1500 | { | |
63cd96b7 | 1501 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); |
ff1ba3da CG |
1502 | unsigned long transfer_timeout; |
1503 | unsigned long timeout; | |
b5f3294f | 1504 | |
6cdeb002 UKK |
1505 | spi_imx->tx_buf = transfer->tx_buf; |
1506 | spi_imx->rx_buf = transfer->rx_buf; | |
1507 | spi_imx->count = transfer->len; | |
1508 | spi_imx->txfifo = 0; | |
2ca300ac | 1509 | spi_imx->remainder = 0; |
b5f3294f | 1510 | |
aa0fe826 | 1511 | reinit_completion(&spi_imx->xfer_done); |
b5f3294f | 1512 | |
6cdeb002 | 1513 | spi_imx_push(spi_imx); |
b5f3294f | 1514 | |
edd501bb | 1515 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 1516 | |
ff1ba3da CG |
1517 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1518 | ||
1519 | timeout = wait_for_completion_timeout(&spi_imx->xfer_done, | |
1520 | transfer_timeout); | |
1521 | if (!timeout) { | |
1522 | dev_err(&spi->dev, "I/O Error in PIO\n"); | |
1523 | spi_imx->devtype_data->reset(spi_imx); | |
1524 | return -ETIMEDOUT; | |
1525 | } | |
b5f3294f | 1526 | |
307c897d | 1527 | return 0; |
b5f3294f SH |
1528 | } |
1529 | ||
07e75938 MKB |
1530 | static int spi_imx_poll_transfer(struct spi_device *spi, |
1531 | struct spi_transfer *transfer) | |
1532 | { | |
1533 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); | |
1534 | unsigned long timeout; | |
1535 | ||
1536 | spi_imx->tx_buf = transfer->tx_buf; | |
1537 | spi_imx->rx_buf = transfer->rx_buf; | |
1538 | spi_imx->count = transfer->len; | |
1539 | spi_imx->txfifo = 0; | |
1540 | spi_imx->remainder = 0; | |
1541 | ||
1542 | /* fill in the fifo before timeout calculations if we are | |
1543 | * interrupted here, then the data is getting transferred by | |
1544 | * the HW while we are interrupted | |
1545 | */ | |
1546 | spi_imx_push(spi_imx); | |
1547 | ||
1548 | timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; | |
1549 | while (spi_imx->txfifo) { | |
1550 | /* RX */ | |
1551 | while (spi_imx->txfifo && | |
1552 | spi_imx->devtype_data->rx_available(spi_imx)) { | |
1553 | spi_imx->rx(spi_imx); | |
1554 | spi_imx->txfifo--; | |
1555 | } | |
1556 | ||
1557 | /* TX */ | |
1558 | if (spi_imx->count) { | |
1559 | spi_imx_push(spi_imx); | |
1560 | continue; | |
1561 | } | |
1562 | ||
1563 | if (spi_imx->txfifo && | |
1564 | time_after(jiffies, timeout)) { | |
1565 | ||
1566 | dev_err_ratelimited(&spi->dev, | |
1567 | "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", | |
1568 | jiffies - timeout); | |
1569 | ||
1570 | /* fall back to interrupt mode */ | |
1571 | return spi_imx_pio_transfer(spi, transfer); | |
1572 | } | |
1573 | } | |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | ||
756d5bf0 YY |
1578 | static int spi_imx_pio_transfer_target(struct spi_device *spi, |
1579 | struct spi_transfer *transfer) | |
71abd290 | 1580 | { |
63cd96b7 | 1581 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); |
307c897d | 1582 | int ret = 0; |
71abd290 | 1583 | |
1584 | if (is_imx53_ecspi(spi_imx) && | |
1585 | transfer->len > MX53_MAX_TRANSFER_BYTES) { | |
1586 | dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", | |
1587 | MX53_MAX_TRANSFER_BYTES); | |
1588 | return -EMSGSIZE; | |
1589 | } | |
1590 | ||
1591 | spi_imx->tx_buf = transfer->tx_buf; | |
1592 | spi_imx->rx_buf = transfer->rx_buf; | |
1593 | spi_imx->count = transfer->len; | |
1594 | spi_imx->txfifo = 0; | |
2ca300ac | 1595 | spi_imx->remainder = 0; |
71abd290 | 1596 | |
1597 | reinit_completion(&spi_imx->xfer_done); | |
756d5bf0 | 1598 | spi_imx->target_aborted = false; |
71abd290 | 1599 | |
1600 | spi_imx_push(spi_imx); | |
1601 | ||
1602 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); | |
1603 | ||
1604 | if (wait_for_completion_interruptible(&spi_imx->xfer_done) || | |
756d5bf0 | 1605 | spi_imx->target_aborted) { |
71abd290 | 1606 | dev_dbg(&spi->dev, "interrupted\n"); |
1607 | ret = -EINTR; | |
1608 | } | |
1609 | ||
756d5bf0 | 1610 | /* ecspi has a HW issue when works in Target mode, |
71abd290 | 1611 | * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, |
1612 | * ECSPI_TXDATA keeps shift out the last word data, | |
756d5bf0 | 1613 | * so we have to disable ECSPI when in target mode after the |
71abd290 | 1614 | * transfer completes |
1615 | */ | |
1616 | if (spi_imx->devtype_data->disable) | |
1617 | spi_imx->devtype_data->disable(spi_imx); | |
1618 | ||
1619 | return ret; | |
1620 | } | |
1621 | ||
307c897d MKB |
1622 | static int spi_imx_transfer_one(struct spi_controller *controller, |
1623 | struct spi_device *spi, | |
f62caccd RG |
1624 | struct spi_transfer *transfer) |
1625 | { | |
63cd96b7 | 1626 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); |
07e75938 | 1627 | unsigned long hz_per_byte, byte_limit; |
f62caccd | 1628 | |
307c897d | 1629 | spi_imx_setupxfer(spi, transfer); |
bf253e6b MKB |
1630 | transfer->effective_speed_hz = spi_imx->spi_bus_clk; |
1631 | ||
71abd290 | 1632 | /* flush rxfifo before transfer */ |
1633 | while (spi_imx->devtype_data->rx_available(spi_imx)) | |
c842749e | 1634 | readl(spi_imx->base + MXC_CSPIRXDATA); |
71abd290 | 1635 | |
756d5bf0 YY |
1636 | if (spi_imx->target_mode) |
1637 | return spi_imx_pio_transfer_target(spi, transfer); | |
71abd290 | 1638 | |
e85e9e0d MKB |
1639 | /* |
1640 | * If we decided in spi_imx_can_dma() that we want to do a DMA | |
1641 | * transfer, the SPI transfer has already been mapped, so we | |
1642 | * have to do the DMA transfer here. | |
1643 | */ | |
1644 | if (spi_imx->usedma) | |
1645 | return spi_imx_dma_transfer(spi_imx, transfer); | |
07e75938 MKB |
1646 | /* |
1647 | * Calculate the estimated time in us the transfer runs. Find | |
1648 | * the number of Hz per byte per polling limit. | |
1649 | */ | |
1650 | hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0; | |
1651 | byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1; | |
1652 | ||
1653 | /* run in polling mode for short transfers */ | |
1654 | if (transfer->len < byte_limit) | |
1655 | return spi_imx_poll_transfer(spi, transfer); | |
1656 | ||
bcd8e776 | 1657 | return spi_imx_pio_transfer(spi, transfer); |
f62caccd RG |
1658 | } |
1659 | ||
6cdeb002 | 1660 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 1661 | { |
f4d4ecfe | 1662 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
1663 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
1664 | ||
b5f3294f SH |
1665 | return 0; |
1666 | } | |
1667 | ||
6cdeb002 | 1668 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
1669 | { |
1670 | } | |
1671 | ||
9e556dcc | 1672 | static int |
63cd96b7 | 1673 | spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg) |
9e556dcc | 1674 | { |
63cd96b7 | 1675 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); |
9e556dcc HS |
1676 | int ret; |
1677 | ||
7d34ff58 | 1678 | ret = pm_runtime_resume_and_get(spi_imx->dev); |
525c9e5a CW |
1679 | if (ret < 0) { |
1680 | dev_err(spi_imx->dev, "failed to enable clock\n"); | |
9e556dcc HS |
1681 | return ret; |
1682 | } | |
1683 | ||
e697271c UKK |
1684 | ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); |
1685 | if (ret) { | |
525c9e5a CW |
1686 | pm_runtime_mark_last_busy(spi_imx->dev); |
1687 | pm_runtime_put_autosuspend(spi_imx->dev); | |
e697271c UKK |
1688 | } |
1689 | ||
1690 | return ret; | |
9e556dcc HS |
1691 | } |
1692 | ||
1693 | static int | |
63cd96b7 | 1694 | spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg) |
9e556dcc | 1695 | { |
63cd96b7 | 1696 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); |
9e556dcc | 1697 | |
525c9e5a CW |
1698 | pm_runtime_mark_last_busy(spi_imx->dev); |
1699 | pm_runtime_put_autosuspend(spi_imx->dev); | |
9e556dcc HS |
1700 | return 0; |
1701 | } | |
1702 | ||
756d5bf0 | 1703 | static int spi_imx_target_abort(struct spi_controller *controller) |
71abd290 | 1704 | { |
63cd96b7 | 1705 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); |
71abd290 | 1706 | |
756d5bf0 | 1707 | spi_imx->target_aborted = true; |
71abd290 | 1708 | complete(&spi_imx->xfer_done); |
1709 | ||
1710 | return 0; | |
1711 | } | |
1712 | ||
fd4a319b | 1713 | static int spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 1714 | { |
22a85e4c | 1715 | struct device_node *np = pdev->dev.of_node; |
63cd96b7 | 1716 | struct spi_controller *controller; |
6cdeb002 | 1717 | struct spi_imx_data *spi_imx; |
b5f3294f | 1718 | struct resource *res; |
8cdcd8ae | 1719 | int ret, irq, spi_drctl; |
200d925e TT |
1720 | const struct spi_imx_devtype_data *devtype_data = |
1721 | of_device_get_match_data(&pdev->dev); | |
756d5bf0 | 1722 | bool target_mode; |
8cdcd8ae | 1723 | u32 val; |
b5f3294f | 1724 | |
756d5bf0 YY |
1725 | target_mode = devtype_data->has_targetmode && |
1726 | of_property_read_bool(np, "spi-slave"); | |
1727 | if (target_mode) | |
1728 | controller = spi_alloc_target(&pdev->dev, | |
63cd96b7 | 1729 | sizeof(struct spi_imx_data)); |
756d5bf0 YY |
1730 | else |
1731 | controller = spi_alloc_host(&pdev->dev, | |
1732 | sizeof(struct spi_imx_data)); | |
63cd96b7 | 1733 | if (!controller) |
2c147776 FE |
1734 | return -ENOMEM; |
1735 | ||
f72efa7e LM |
1736 | ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); |
1737 | if ((ret < 0) || (spi_drctl >= 0x3)) { | |
1738 | /* '11' is reserved */ | |
1739 | spi_drctl = 0; | |
1740 | } | |
1741 | ||
63cd96b7 | 1742 | platform_set_drvdata(pdev, controller); |
b5f3294f | 1743 | |
63cd96b7 MKB |
1744 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
1745 | controller->bus_num = np ? -1 : pdev->id; | |
1746 | controller->use_gpio_descriptors = true; | |
b5f3294f | 1747 | |
63cd96b7 | 1748 | spi_imx = spi_controller_get_devdata(controller); |
307c897d | 1749 | spi_imx->controller = controller; |
6aa800ca | 1750 | spi_imx->dev = &pdev->dev; |
756d5bf0 | 1751 | spi_imx->target_mode = target_mode; |
b5f3294f | 1752 | |
71abd290 | 1753 | spi_imx->devtype_data = devtype_data; |
4686d1c3 | 1754 | |
8cdcd8ae LW |
1755 | /* |
1756 | * Get number of chip selects from device properties. This can be | |
1757 | * coming from device tree or boardfiles, if it is not defined, | |
1758 | * a default value of 3 chip selects will be used, as all the legacy | |
1759 | * board files have <= 3 chip selects. | |
1760 | */ | |
1761 | if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) | |
63cd96b7 | 1762 | controller->num_chipselect = val; |
8cdcd8ae | 1763 | else |
63cd96b7 | 1764 | controller->num_chipselect = 3; |
b5f3294f | 1765 | |
d9032b30 RV |
1766 | controller->transfer_one = spi_imx_transfer_one; |
1767 | controller->setup = spi_imx_setup; | |
1768 | controller->cleanup = spi_imx_cleanup; | |
1769 | controller->prepare_message = spi_imx_prepare_message; | |
1770 | controller->unprepare_message = spi_imx_unprepare_message; | |
756d5bf0 | 1771 | controller->target_abort = spi_imx_target_abort; |
6a983ff5 BS |
1772 | controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS | |
1773 | SPI_MOSI_IDLE_LOW; | |
307c897d | 1774 | |
26e4bb86 | 1775 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || |
1776 | is_imx53_ecspi(spi_imx)) | |
d9032b30 | 1777 | controller->mode_bits |= SPI_LOOP | SPI_READY; |
f72efa7e | 1778 | |
79422ed9 | 1779 | if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) |
d9032b30 | 1780 | controller->mode_bits |= SPI_RX_CPHA_FLIP; |
79422ed9 | 1781 | |
6e95b23a UKK |
1782 | if (is_imx51_ecspi(spi_imx) && |
1783 | device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) | |
1784 | /* | |
1785 | * When using HW-CS implementing SPI_CS_WORD can be done by just | |
1786 | * setting the burst length to the word size. This is | |
1787 | * considerably faster than manually controlling the CS. | |
1788 | */ | |
d9032b30 | 1789 | controller->mode_bits |= SPI_CS_WORD; |
6e95b23a | 1790 | |
8ce1bb9a RV |
1791 | if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) { |
1792 | controller->max_native_cs = 4; | |
82238d2c | 1793 | controller->flags |= SPI_CONTROLLER_GPIO_SS; |
8ce1bb9a RV |
1794 | } |
1795 | ||
f72efa7e | 1796 | spi_imx->spi_drctl = spi_drctl; |
b5f3294f | 1797 | |
6cdeb002 | 1798 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 1799 | |
d909451c | 1800 | spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
130b82c0 FE |
1801 | if (IS_ERR(spi_imx->base)) { |
1802 | ret = PTR_ERR(spi_imx->base); | |
63cd96b7 | 1803 | goto out_controller_put; |
b5f3294f | 1804 | } |
f12ae171 | 1805 | spi_imx->base_phys = res->start; |
b5f3294f | 1806 | |
4b5d6aad FE |
1807 | irq = platform_get_irq(pdev, 0); |
1808 | if (irq < 0) { | |
1809 | ret = irq; | |
63cd96b7 | 1810 | goto out_controller_put; |
b5f3294f SH |
1811 | } |
1812 | ||
4b5d6aad | 1813 | ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, |
8fc39b51 | 1814 | dev_name(&pdev->dev), spi_imx); |
b5f3294f | 1815 | if (ret) { |
4b5d6aad | 1816 | dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); |
63cd96b7 | 1817 | goto out_controller_put; |
b5f3294f SH |
1818 | } |
1819 | ||
aa29d840 SH |
1820 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1821 | if (IS_ERR(spi_imx->clk_ipg)) { | |
1822 | ret = PTR_ERR(spi_imx->clk_ipg); | |
63cd96b7 | 1823 | goto out_controller_put; |
b5f3294f SH |
1824 | } |
1825 | ||
aa29d840 SH |
1826 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
1827 | if (IS_ERR(spi_imx->clk_per)) { | |
1828 | ret = PTR_ERR(spi_imx->clk_per); | |
63cd96b7 | 1829 | goto out_controller_put; |
aa29d840 SH |
1830 | } |
1831 | ||
43b6bf40 SH |
1832 | ret = clk_prepare_enable(spi_imx->clk_per); |
1833 | if (ret) | |
63cd96b7 | 1834 | goto out_controller_put; |
43b6bf40 SH |
1835 | |
1836 | ret = clk_prepare_enable(spi_imx->clk_ipg); | |
1837 | if (ret) | |
1838 | goto out_put_per; | |
1839 | ||
525c9e5a CW |
1840 | pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); |
1841 | pm_runtime_use_autosuspend(spi_imx->dev); | |
7cd71202 | 1842 | pm_runtime_get_noresume(spi_imx->dev); |
43b6bf40 SH |
1843 | pm_runtime_set_active(spi_imx->dev); |
1844 | pm_runtime_enable(spi_imx->dev); | |
aa29d840 SH |
1845 | |
1846 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
f62caccd | 1847 | /* |
2dd33f9c MK |
1848 | * Only validated on i.mx35 and i.mx6 now, can remove the constraint |
1849 | * if validated on other chips. | |
f62caccd | 1850 | */ |
fd8d4e2d | 1851 | if (spi_imx->devtype_data->has_dmamode) { |
63cd96b7 | 1852 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); |
bf9af08c | 1853 | if (ret == -EPROBE_DEFER) |
525c9e5a | 1854 | goto out_runtime_pm_put; |
bf9af08c | 1855 | |
3760047a | 1856 | if (ret < 0) |
0ec0da74 | 1857 | dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", |
3760047a AB |
1858 | ret); |
1859 | } | |
b5f3294f | 1860 | |
edd501bb | 1861 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 1862 | |
edd501bb | 1863 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 1864 | |
63cd96b7 | 1865 | controller->dev.of_node = pdev->dev.of_node; |
307c897d | 1866 | ret = spi_register_controller(controller); |
8197f489 | 1867 | if (ret) { |
307c897d MKB |
1868 | dev_err_probe(&pdev->dev, ret, "register controller failed\n"); |
1869 | goto out_register_controller; | |
8197f489 | 1870 | } |
b5f3294f | 1871 | |
525c9e5a CW |
1872 | pm_runtime_mark_last_busy(spi_imx->dev); |
1873 | pm_runtime_put_autosuspend(spi_imx->dev); | |
1874 | ||
b5f3294f SH |
1875 | return ret; |
1876 | ||
307c897d | 1877 | out_register_controller: |
45f0bbda MV |
1878 | if (spi_imx->devtype_data->has_dmamode) |
1879 | spi_imx_sdma_exit(spi_imx); | |
525c9e5a CW |
1880 | out_runtime_pm_put: |
1881 | pm_runtime_dont_use_autosuspend(spi_imx->dev); | |
43b6bf40 | 1882 | pm_runtime_set_suspended(&pdev->dev); |
525c9e5a | 1883 | pm_runtime_disable(spi_imx->dev); |
43b6bf40 SH |
1884 | |
1885 | clk_disable_unprepare(spi_imx->clk_ipg); | |
1886 | out_put_per: | |
1887 | clk_disable_unprepare(spi_imx->clk_per); | |
63cd96b7 MKB |
1888 | out_controller_put: |
1889 | spi_controller_put(controller); | |
130b82c0 | 1890 | |
b5f3294f SH |
1891 | return ret; |
1892 | } | |
1893 | ||
423e5481 | 1894 | static void spi_imx_remove(struct platform_device *pdev) |
b5f3294f | 1895 | { |
63cd96b7 MKB |
1896 | struct spi_controller *controller = platform_get_drvdata(pdev); |
1897 | struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); | |
d593574a | 1898 | int ret; |
b5f3294f | 1899 | |
307c897d | 1900 | spi_unregister_controller(controller); |
b5f3294f | 1901 | |
11951c9e UKK |
1902 | ret = pm_runtime_get_sync(spi_imx->dev); |
1903 | if (ret >= 0) | |
1904 | writel(0, spi_imx->base + MXC_CSPICTRL); | |
1905 | else | |
1906 | dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); | |
525c9e5a CW |
1907 | |
1908 | pm_runtime_dont_use_autosuspend(spi_imx->dev); | |
1909 | pm_runtime_put_sync(spi_imx->dev); | |
1910 | pm_runtime_disable(spi_imx->dev); | |
1911 | ||
1912 | spi_imx_sdma_exit(spi_imx); | |
525c9e5a CW |
1913 | } |
1914 | ||
1915 | static int __maybe_unused spi_imx_runtime_resume(struct device *dev) | |
1916 | { | |
63cd96b7 | 1917 | struct spi_controller *controller = dev_get_drvdata(dev); |
525c9e5a CW |
1918 | struct spi_imx_data *spi_imx; |
1919 | int ret; | |
1920 | ||
63cd96b7 | 1921 | spi_imx = spi_controller_get_devdata(controller); |
525c9e5a CW |
1922 | |
1923 | ret = clk_prepare_enable(spi_imx->clk_per); | |
d593574a SA |
1924 | if (ret) |
1925 | return ret; | |
1926 | ||
525c9e5a | 1927 | ret = clk_prepare_enable(spi_imx->clk_ipg); |
d593574a | 1928 | if (ret) { |
525c9e5a | 1929 | clk_disable_unprepare(spi_imx->clk_per); |
d593574a SA |
1930 | return ret; |
1931 | } | |
1932 | ||
525c9e5a CW |
1933 | return 0; |
1934 | } | |
1935 | ||
1936 | static int __maybe_unused spi_imx_runtime_suspend(struct device *dev) | |
1937 | { | |
63cd96b7 | 1938 | struct spi_controller *controller = dev_get_drvdata(dev); |
525c9e5a CW |
1939 | struct spi_imx_data *spi_imx; |
1940 | ||
63cd96b7 | 1941 | spi_imx = spi_controller_get_devdata(controller); |
525c9e5a | 1942 | |
d593574a | 1943 | clk_disable_unprepare(spi_imx->clk_per); |
525c9e5a CW |
1944 | clk_disable_unprepare(spi_imx->clk_ipg); |
1945 | ||
1946 | return 0; | |
1947 | } | |
b5f3294f | 1948 | |
525c9e5a CW |
1949 | static int __maybe_unused spi_imx_suspend(struct device *dev) |
1950 | { | |
1951 | pinctrl_pm_select_sleep_state(dev); | |
b5f3294f SH |
1952 | return 0; |
1953 | } | |
1954 | ||
525c9e5a CW |
1955 | static int __maybe_unused spi_imx_resume(struct device *dev) |
1956 | { | |
1957 | pinctrl_pm_select_default_state(dev); | |
1958 | return 0; | |
1959 | } | |
1960 | ||
1961 | static const struct dev_pm_ops imx_spi_pm = { | |
1962 | SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend, | |
1963 | spi_imx_runtime_resume, NULL) | |
1964 | SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume) | |
1965 | }; | |
1966 | ||
6cdeb002 | 1967 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
1968 | .driver = { |
1969 | .name = DRIVER_NAME, | |
22a85e4c | 1970 | .of_match_table = spi_imx_dt_ids, |
525c9e5a CW |
1971 | .pm = &imx_spi_pm, |
1972 | }, | |
6cdeb002 | 1973 | .probe = spi_imx_probe, |
423e5481 | 1974 | .remove_new = spi_imx_remove, |
b5f3294f | 1975 | }; |
940ab889 | 1976 | module_platform_driver(spi_imx_driver); |
b5f3294f | 1977 | |
92bad4a4 | 1978 | MODULE_DESCRIPTION("i.MX SPI Controller driver"); |
b5f3294f SH |
1979 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
1980 | MODULE_LICENSE("GPL"); | |
3133fba3 | 1981 | MODULE_ALIAS("platform:" DRIVER_NAME); |