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79650597 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | // Copyright (C) 2008 Juergen Beisert | |
b5f3294f SH |
4 | |
5 | #include <linux/clk.h> | |
6 | #include <linux/completion.h> | |
7 | #include <linux/delay.h> | |
f62caccd RG |
8 | #include <linux/dmaengine.h> |
9 | #include <linux/dma-mapping.h> | |
b5f3294f SH |
10 | #include <linux/err.h> |
11 | #include <linux/gpio.h> | |
b5f3294f SH |
12 | #include <linux/interrupt.h> |
13 | #include <linux/io.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
b5f3294f SH |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/spi_bitbang.h> | |
21 | #include <linux/types.h> | |
22a85e4c SG |
22 | #include <linux/of.h> |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_gpio.h> | |
b5f3294f | 25 | |
f62caccd | 26 | #include <linux/platform_data/dma-imx.h> |
82906b13 | 27 | #include <linux/platform_data/spi-imx.h> |
b5f3294f SH |
28 | |
29 | #define DRIVER_NAME "spi_imx" | |
30 | ||
0a9c8998 TP |
31 | static bool use_dma = true; |
32 | module_param(use_dma, bool, 0644); | |
33 | MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); | |
34 | ||
b5f3294f SH |
35 | #define MXC_CSPIRXDATA 0x00 |
36 | #define MXC_CSPITXDATA 0x04 | |
37 | #define MXC_CSPICTRL 0x08 | |
38 | #define MXC_CSPIINT 0x0c | |
39 | #define MXC_RESET 0x1c | |
40 | ||
41 | /* generic defines to abstract from the different register layouts */ | |
42 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
43 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
71abd290 | 44 | #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ |
b5f3294f | 45 | |
30d67142 UKK |
46 | /* The maximum bytes that a sdma BD can transfer. */ |
47 | #define MAX_SDMA_BD_BYTES (1 << 15) | |
1673c81d | 48 | #define MX51_ECSPI_CTRL_MAX_BURST 512 |
71abd290 | 49 | /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ |
50 | #define MX53_MAX_TRANSFER_BYTES 512 | |
b5f3294f | 51 | |
f4ba6315 | 52 | enum spi_imx_devtype { |
04ee5854 SG |
53 | IMX1_CSPI, |
54 | IMX21_CSPI, | |
55 | IMX27_CSPI, | |
56 | IMX31_CSPI, | |
57 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
26e4bb86 | 58 | IMX51_ECSPI, /* ECSPI on i.mx51 */ |
59 | IMX53_ECSPI, /* ECSPI on i.mx53 and later */ | |
f4ba6315 UKK |
60 | }; |
61 | ||
62 | struct spi_imx_data; | |
63 | ||
64 | struct spi_imx_devtype_data { | |
65 | void (*intctrl)(struct spi_imx_data *, int); | |
e697271c | 66 | int (*prepare_message)(struct spi_imx_data *, struct spi_message *); |
1d374703 UKK |
67 | int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *, |
68 | struct spi_transfer *); | |
f4ba6315 UKK |
69 | void (*trigger)(struct spi_imx_data *); |
70 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 71 | void (*reset)(struct spi_imx_data *); |
987a2dfe | 72 | void (*setup_wml)(struct spi_imx_data *); |
71abd290 | 73 | void (*disable)(struct spi_imx_data *); |
fd8d4e2d | 74 | bool has_dmamode; |
71abd290 | 75 | bool has_slavemode; |
fd8d4e2d | 76 | unsigned int fifo_size; |
1673c81d | 77 | bool dynamic_burst; |
04ee5854 | 78 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
79 | }; |
80 | ||
6cdeb002 | 81 | struct spi_imx_data { |
b5f3294f | 82 | struct spi_bitbang bitbang; |
6aa800ca | 83 | struct device *dev; |
b5f3294f SH |
84 | |
85 | struct completion xfer_done; | |
cc4d22ae | 86 | void __iomem *base; |
f12ae171 AB |
87 | unsigned long base_phys; |
88 | ||
aa29d840 SH |
89 | struct clk *clk_per; |
90 | struct clk *clk_ipg; | |
b5f3294f | 91 | unsigned long spi_clk; |
4bfe927a | 92 | unsigned int spi_bus_clk; |
b5f3294f | 93 | |
d52345b6 | 94 | unsigned int bits_per_word; |
f72efa7e | 95 | unsigned int spi_drctl; |
f12ae171 | 96 | |
1673c81d | 97 | unsigned int count, remainder; |
6cdeb002 UKK |
98 | void (*tx)(struct spi_imx_data *); |
99 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
100 | void *rx_buf; |
101 | const void *tx_buf; | |
102 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
2ca300ac | 103 | unsigned int dynamic_burst; |
b5f3294f | 104 | |
71abd290 | 105 | /* Slave mode */ |
106 | bool slave_mode; | |
107 | bool slave_aborted; | |
108 | unsigned int slave_burst; | |
109 | ||
f62caccd | 110 | /* DMA */ |
f62caccd | 111 | bool usedma; |
0dfbaa89 | 112 | u32 wml; |
f62caccd RG |
113 | struct completion dma_rx_completion; |
114 | struct completion dma_tx_completion; | |
115 | ||
80023cb3 | 116 | const struct spi_imx_devtype_data *devtype_data; |
b5f3294f SH |
117 | }; |
118 | ||
04ee5854 SG |
119 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
120 | { | |
121 | return d->devtype_data->devtype == IMX27_CSPI; | |
122 | } | |
123 | ||
124 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
125 | { | |
126 | return d->devtype_data->devtype == IMX35_CSPI; | |
127 | } | |
128 | ||
f8a87617 AB |
129 | static inline int is_imx51_ecspi(struct spi_imx_data *d) |
130 | { | |
131 | return d->devtype_data->devtype == IMX51_ECSPI; | |
132 | } | |
133 | ||
26e4bb86 | 134 | static inline int is_imx53_ecspi(struct spi_imx_data *d) |
135 | { | |
136 | return d->devtype_data->devtype == IMX53_ECSPI; | |
137 | } | |
138 | ||
b5f3294f | 139 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 140 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 141 | { \ |
6cdeb002 | 142 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 143 | \ |
6cdeb002 UKK |
144 | if (spi_imx->rx_buf) { \ |
145 | *(type *)spi_imx->rx_buf = val; \ | |
146 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f | 147 | } \ |
2ca300ac MC |
148 | \ |
149 | spi_imx->remainder -= sizeof(type); \ | |
b5f3294f SH |
150 | } |
151 | ||
152 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 153 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
154 | { \ |
155 | type val = 0; \ | |
156 | \ | |
6cdeb002 UKK |
157 | if (spi_imx->tx_buf) { \ |
158 | val = *(type *)spi_imx->tx_buf; \ | |
159 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
160 | } \ |
161 | \ | |
6cdeb002 | 162 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 163 | \ |
6cdeb002 | 164 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
165 | } |
166 | ||
167 | MXC_SPI_BUF_RX(u8) | |
168 | MXC_SPI_BUF_TX(u8) | |
169 | MXC_SPI_BUF_RX(u16) | |
170 | MXC_SPI_BUF_TX(u16) | |
171 | MXC_SPI_BUF_RX(u32) | |
172 | MXC_SPI_BUF_TX(u32) | |
173 | ||
174 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
175 | * (which is currently not the case in this driver) | |
176 | */ | |
177 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
178 | 256, 384, 512, 768, 1024}; | |
179 | ||
180 | /* MX21, MX27 */ | |
6cdeb002 | 181 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
32df9ff2 | 182 | unsigned int fspi, unsigned int max, unsigned int *fres) |
b5f3294f | 183 | { |
04ee5854 | 184 | int i; |
b5f3294f SH |
185 | |
186 | for (i = 2; i < max; i++) | |
187 | if (fspi * mxc_clkdivs[i] >= fin) | |
32df9ff2 | 188 | break; |
b5f3294f | 189 | |
32df9ff2 RB |
190 | *fres = fin / mxc_clkdivs[i]; |
191 | return i; | |
b5f3294f SH |
192 | } |
193 | ||
0b599603 | 194 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 195 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
2636ba8f | 196 | unsigned int fspi, unsigned int *fres) |
b5f3294f SH |
197 | { |
198 | int i, div = 4; | |
199 | ||
200 | for (i = 0; i < 7; i++) { | |
201 | if (fspi * div >= fin) | |
2636ba8f | 202 | goto out; |
b5f3294f SH |
203 | div <<= 1; |
204 | } | |
205 | ||
2636ba8f MK |
206 | out: |
207 | *fres = fin / div; | |
208 | return i; | |
b5f3294f SH |
209 | } |
210 | ||
2e312f6c | 211 | static int spi_imx_bytes_per_word(const int bits_per_word) |
f12ae171 | 212 | { |
afb27208 MC |
213 | if (bits_per_word <= 8) |
214 | return 1; | |
215 | else if (bits_per_word <= 16) | |
216 | return 2; | |
217 | else | |
218 | return 4; | |
f12ae171 AB |
219 | } |
220 | ||
f62caccd RG |
221 | static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, |
222 | struct spi_transfer *transfer) | |
223 | { | |
224 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
f12ae171 | 225 | |
0a9c8998 TP |
226 | if (!use_dma) |
227 | return false; | |
228 | ||
f12ae171 AB |
229 | if (!master->dma_rx) |
230 | return false; | |
231 | ||
71abd290 | 232 | if (spi_imx->slave_mode) |
233 | return false; | |
234 | ||
133eb8e3 RG |
235 | if (transfer->len < spi_imx->devtype_data->fifo_size) |
236 | return false; | |
237 | ||
1673c81d | 238 | spi_imx->dynamic_burst = 0; |
66459c5a | 239 | |
f12ae171 | 240 | return true; |
f62caccd RG |
241 | } |
242 | ||
66de757c SG |
243 | #define MX51_ECSPI_CTRL 0x08 |
244 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
245 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
f62caccd | 246 | #define MX51_ECSPI_CTRL_SMC (1 << 3) |
66de757c | 247 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) |
f72efa7e | 248 | #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) |
66de757c SG |
249 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 |
250 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
251 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
252 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
1673c81d | 253 | #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) |
66de757c SG |
254 | |
255 | #define MX51_ECSPI_CONFIG 0x0c | |
256 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
257 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
258 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
259 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
c09b890b | 260 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) |
66de757c SG |
261 | |
262 | #define MX51_ECSPI_INT 0x10 | |
263 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
264 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
71abd290 | 265 | #define MX51_ECSPI_INT_RDREN (1 << 4) |
66de757c | 266 | |
30d67142 | 267 | #define MX51_ECSPI_DMA 0x14 |
d629c2a0 SH |
268 | #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) |
269 | #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) | |
270 | #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) | |
f62caccd | 271 | |
2b0fd069 SH |
272 | #define MX51_ECSPI_DMA_TEDEN (1 << 7) |
273 | #define MX51_ECSPI_DMA_RXDEN (1 << 23) | |
274 | #define MX51_ECSPI_DMA_RXTDEN (1 << 31) | |
f62caccd | 275 | |
66de757c SG |
276 | #define MX51_ECSPI_STAT 0x18 |
277 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 | 278 | |
9f6aa42b FE |
279 | #define MX51_ECSPI_TESTREG 0x20 |
280 | #define MX51_ECSPI_TESTREG_LBC BIT(31) | |
281 | ||
1673c81d | 282 | static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) |
283 | { | |
284 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); | |
5904c9d3 | 285 | #ifdef __LITTLE_ENDIAN |
1673c81d | 286 | unsigned int bytes_per_word; |
5904c9d3 | 287 | #endif |
1673c81d | 288 | |
289 | if (spi_imx->rx_buf) { | |
290 | #ifdef __LITTLE_ENDIAN | |
291 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
292 | if (bytes_per_word == 1) | |
293 | val = cpu_to_be32(val); | |
294 | else if (bytes_per_word == 2) | |
295 | val = (val << 16) | (val >> 16); | |
296 | #endif | |
1673c81d | 297 | *(u32 *)spi_imx->rx_buf = val; |
298 | spi_imx->rx_buf += sizeof(u32); | |
299 | } | |
2ca300ac MC |
300 | |
301 | spi_imx->remainder -= sizeof(u32); | |
1673c81d | 302 | } |
303 | ||
304 | static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) | |
305 | { | |
2ca300ac MC |
306 | int unaligned; |
307 | u32 val; | |
1673c81d | 308 | |
2ca300ac MC |
309 | unaligned = spi_imx->remainder % 4; |
310 | ||
311 | if (!unaligned) { | |
1673c81d | 312 | spi_imx_buf_rx_swap_u32(spi_imx); |
313 | return; | |
314 | } | |
315 | ||
2ca300ac | 316 | if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { |
1673c81d | 317 | spi_imx_buf_rx_u16(spi_imx); |
2ca300ac MC |
318 | return; |
319 | } | |
320 | ||
321 | val = readl(spi_imx->base + MXC_CSPIRXDATA); | |
322 | ||
323 | while (unaligned--) { | |
324 | if (spi_imx->rx_buf) { | |
325 | *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; | |
326 | spi_imx->rx_buf++; | |
327 | } | |
328 | spi_imx->remainder--; | |
329 | } | |
1673c81d | 330 | } |
331 | ||
332 | static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) | |
333 | { | |
334 | u32 val = 0; | |
5904c9d3 | 335 | #ifdef __LITTLE_ENDIAN |
1673c81d | 336 | unsigned int bytes_per_word; |
5904c9d3 | 337 | #endif |
1673c81d | 338 | |
339 | if (spi_imx->tx_buf) { | |
340 | val = *(u32 *)spi_imx->tx_buf; | |
1673c81d | 341 | spi_imx->tx_buf += sizeof(u32); |
342 | } | |
343 | ||
344 | spi_imx->count -= sizeof(u32); | |
345 | #ifdef __LITTLE_ENDIAN | |
346 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
347 | ||
348 | if (bytes_per_word == 1) | |
349 | val = cpu_to_be32(val); | |
350 | else if (bytes_per_word == 2) | |
351 | val = (val << 16) | (val >> 16); | |
352 | #endif | |
353 | writel(val, spi_imx->base + MXC_CSPITXDATA); | |
354 | } | |
355 | ||
356 | static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) | |
357 | { | |
2ca300ac MC |
358 | int unaligned; |
359 | u32 val = 0; | |
1673c81d | 360 | |
2ca300ac | 361 | unaligned = spi_imx->count % 4; |
1673c81d | 362 | |
2ca300ac MC |
363 | if (!unaligned) { |
364 | spi_imx_buf_tx_swap_u32(spi_imx); | |
365 | return; | |
1673c81d | 366 | } |
367 | ||
2ca300ac MC |
368 | if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { |
369 | spi_imx_buf_tx_u16(spi_imx); | |
1673c81d | 370 | return; |
371 | } | |
372 | ||
2ca300ac MC |
373 | while (unaligned--) { |
374 | if (spi_imx->tx_buf) { | |
375 | val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); | |
376 | spi_imx->tx_buf++; | |
377 | } | |
378 | spi_imx->count--; | |
379 | } | |
1673c81d | 380 | |
2ca300ac | 381 | writel(val, spi_imx->base + MXC_CSPITXDATA); |
1673c81d | 382 | } |
383 | ||
71abd290 | 384 | static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) |
385 | { | |
386 | u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); | |
387 | ||
388 | if (spi_imx->rx_buf) { | |
389 | int n_bytes = spi_imx->slave_burst % sizeof(val); | |
390 | ||
391 | if (!n_bytes) | |
392 | n_bytes = sizeof(val); | |
393 | ||
394 | memcpy(spi_imx->rx_buf, | |
395 | ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); | |
396 | ||
397 | spi_imx->rx_buf += n_bytes; | |
398 | spi_imx->slave_burst -= n_bytes; | |
399 | } | |
2ca300ac MC |
400 | |
401 | spi_imx->remainder -= sizeof(u32); | |
71abd290 | 402 | } |
403 | ||
404 | static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) | |
405 | { | |
406 | u32 val = 0; | |
407 | int n_bytes = spi_imx->count % sizeof(val); | |
408 | ||
409 | if (!n_bytes) | |
410 | n_bytes = sizeof(val); | |
411 | ||
412 | if (spi_imx->tx_buf) { | |
413 | memcpy(((u8 *)&val) + sizeof(val) - n_bytes, | |
414 | spi_imx->tx_buf, n_bytes); | |
415 | val = cpu_to_be32(val); | |
416 | spi_imx->tx_buf += n_bytes; | |
417 | } | |
418 | ||
419 | spi_imx->count -= n_bytes; | |
420 | ||
421 | writel(val, spi_imx->base + MXC_CSPITXDATA); | |
422 | } | |
423 | ||
0b599603 | 424 | /* MX51 eCSPI */ |
6aa800ca SH |
425 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
426 | unsigned int fspi, unsigned int *fres) | |
0b599603 UKK |
427 | { |
428 | /* | |
429 | * there are two 4-bit dividers, the pre-divider divides by | |
430 | * $pre, the post-divider by 2^$post | |
431 | */ | |
432 | unsigned int pre, post; | |
6aa800ca | 433 | unsigned int fin = spi_imx->spi_clk; |
0b599603 UKK |
434 | |
435 | if (unlikely(fspi > fin)) | |
436 | return 0; | |
437 | ||
438 | post = fls(fin) - fls(fspi); | |
439 | if (fin > fspi << post) | |
440 | post++; | |
441 | ||
442 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
443 | ||
444 | post = max(4U, post) - 4; | |
445 | if (unlikely(post > 0xf)) { | |
6aa800ca SH |
446 | dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", |
447 | fspi, fin); | |
0b599603 UKK |
448 | return 0xff; |
449 | } | |
450 | ||
451 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
452 | ||
6aa800ca | 453 | dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", |
0b599603 | 454 | __func__, fin, fspi, post, pre); |
6fd8b850 MV |
455 | |
456 | /* Resulting frequency for the SCLK line. */ | |
457 | *fres = (fin / (pre + 1)) >> post; | |
458 | ||
66de757c SG |
459 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
460 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
461 | } |
462 | ||
f989bc69 | 463 | static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
464 | { |
465 | unsigned val = 0; | |
466 | ||
467 | if (enable & MXC_INT_TE) | |
66de757c | 468 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
469 | |
470 | if (enable & MXC_INT_RR) | |
66de757c | 471 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 472 | |
71abd290 | 473 | if (enable & MXC_INT_RDR) |
474 | val |= MX51_ECSPI_INT_RDREN; | |
475 | ||
66de757c | 476 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
477 | } |
478 | ||
f989bc69 | 479 | static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 | 480 | { |
b03c3884 | 481 | u32 reg; |
f62caccd | 482 | |
b03c3884 SH |
483 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
484 | reg |= MX51_ECSPI_CTRL_XCH; | |
66de757c | 485 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); |
0b599603 UKK |
486 | } |
487 | ||
71abd290 | 488 | static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) |
489 | { | |
490 | u32 ctrl; | |
491 | ||
492 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | |
493 | ctrl &= ~MX51_ECSPI_CTRL_ENABLE; | |
494 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
495 | } | |
496 | ||
e697271c UKK |
497 | static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, |
498 | struct spi_message *msg) | |
499 | { | |
00b80ac9 | 500 | struct spi_device *spi = msg->spi; |
793c7f92 | 501 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE; |
00b80ac9 | 502 | u32 testreg; |
793c7f92 | 503 | u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); |
0b599603 | 504 | |
71abd290 | 505 | /* set Master or Slave mode */ |
506 | if (spi_imx->slave_mode) | |
507 | ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; | |
508 | else | |
509 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; | |
0b599603 | 510 | |
f72efa7e LM |
511 | /* |
512 | * Enable SPI_RDY handling (falling edge/level triggered). | |
513 | */ | |
514 | if (spi->mode & SPI_READY) | |
515 | ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); | |
516 | ||
0b599603 | 517 | /* set chip select to use */ |
b36581df | 518 | ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); |
0b599603 | 519 | |
00b80ac9 UKK |
520 | /* |
521 | * The ctrl register must be written first, with the EN bit set other | |
522 | * registers must not be written to. | |
523 | */ | |
524 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
525 | ||
526 | testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); | |
527 | if (spi->mode & SPI_LOOP) | |
528 | testreg |= MX51_ECSPI_TESTREG_LBC; | |
71abd290 | 529 | else |
00b80ac9 UKK |
530 | testreg &= ~MX51_ECSPI_TESTREG_LBC; |
531 | writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); | |
0b599603 | 532 | |
71abd290 | 533 | /* |
534 | * eCSPI burst completion by Chip Select signal in Slave mode | |
535 | * is not functional for imx53 Soc, config SPI burst completed when | |
536 | * BURST_LENGTH + 1 bits are received | |
537 | */ | |
538 | if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) | |
539 | cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); | |
540 | else | |
541 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); | |
0b599603 | 542 | |
c0c7a5d7 | 543 | if (spi->mode & SPI_CPHA) |
b36581df | 544 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); |
793c7f92 | 545 | else |
b36581df | 546 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); |
0b599603 | 547 | |
c0c7a5d7 | 548 | if (spi->mode & SPI_CPOL) { |
b36581df AS |
549 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); |
550 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); | |
793c7f92 | 551 | } else { |
b36581df AS |
552 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); |
553 | cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); | |
c09b890b | 554 | } |
00b80ac9 | 555 | |
c0c7a5d7 | 556 | if (spi->mode & SPI_CS_HIGH) |
b36581df | 557 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); |
793c7f92 | 558 | else |
b36581df | 559 | cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); |
0b599603 | 560 | |
00b80ac9 | 561 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); |
b03c3884 | 562 | |
00b80ac9 UKK |
563 | return 0; |
564 | } | |
f677f17c | 565 | |
1d374703 UKK |
566 | static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, |
567 | struct spi_device *spi, | |
568 | struct spi_transfer *t) | |
00b80ac9 | 569 | { |
00b80ac9 | 570 | u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); |
3f75720d | 571 | u32 clk = t->speed_hz, delay; |
00b80ac9 UKK |
572 | |
573 | /* Clear BL field and set the right value */ | |
574 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | |
575 | if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) | |
576 | ctrl |= (spi_imx->slave_burst * 8 - 1) | |
577 | << MX51_ECSPI_CTRL_BL_OFFSET; | |
9f6aa42b | 578 | else |
00b80ac9 UKK |
579 | ctrl |= (spi_imx->bits_per_word - 1) |
580 | << MX51_ECSPI_CTRL_BL_OFFSET; | |
9f6aa42b | 581 | |
00b80ac9 UKK |
582 | /* set clock speed */ |
583 | ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | | |
584 | 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); | |
3f75720d | 585 | ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk); |
00b80ac9 UKK |
586 | spi_imx->spi_bus_clk = clk; |
587 | ||
588 | if (spi_imx->usedma) | |
589 | ctrl |= MX51_ECSPI_CTRL_SMC; | |
590 | ||
591 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
0b599603 | 592 | |
6fd8b850 MV |
593 | /* |
594 | * Wait until the changes in the configuration register CONFIGREG | |
595 | * propagate into the hardware. It takes exactly one tick of the | |
596 | * SCLK clock, but we will wait two SCLK clock just to be sure. The | |
597 | * effect of the delay it takes for the hardware to apply changes | |
598 | * is noticable if the SCLK clock run very slow. In such a case, if | |
599 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might | |
600 | * be asserted before the SCLK polarity changes, which would disrupt | |
601 | * the SPI communication as the device on the other end would consider | |
602 | * the change of SCLK polarity as a clock tick already. | |
603 | */ | |
604 | delay = (2 * 1000000) / clk; | |
605 | if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ | |
606 | udelay(delay); | |
607 | else /* SCLK is _very_ slow */ | |
608 | usleep_range(delay, delay + 10); | |
609 | ||
987a2dfe RG |
610 | return 0; |
611 | } | |
612 | ||
613 | static void mx51_setup_wml(struct spi_imx_data *spi_imx) | |
614 | { | |
f62caccd RG |
615 | /* |
616 | * Configure the DMA register: setup the watermark | |
617 | * and enable DMA request. | |
618 | */ | |
5ba5a373 | 619 | writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | |
d629c2a0 SH |
620 | MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | |
621 | MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | | |
2b0fd069 SH |
622 | MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | |
623 | MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); | |
0b599603 UKK |
624 | } |
625 | ||
f989bc69 | 626 | static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 627 | { |
66de757c | 628 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
629 | } |
630 | ||
f989bc69 | 631 | static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
632 | { |
633 | /* drain receive buffer */ | |
66de757c | 634 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
635 | readl(spi_imx->base + MXC_CSPIRXDATA); |
636 | } | |
637 | ||
b5f3294f SH |
638 | #define MX31_INTREG_TEEN (1 << 0) |
639 | #define MX31_INTREG_RREN (1 << 3) | |
640 | ||
641 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
642 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
643 | #define MX31_CSPICTRL_XCH (1 << 2) | |
2dd33f9c | 644 | #define MX31_CSPICTRL_SMC (1 << 3) |
b5f3294f SH |
645 | #define MX31_CSPICTRL_POL (1 << 4) |
646 | #define MX31_CSPICTRL_PHA (1 << 5) | |
647 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
648 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
649 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
650 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
651 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
652 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
653 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
654 | ||
2dd33f9c MK |
655 | #define MX31_CSPI_DMAREG 0x10 |
656 | #define MX31_DMAREG_RH_DEN (1<<4) | |
657 | #define MX31_DMAREG_TH_DEN (1<<1) | |
658 | ||
b5f3294f SH |
659 | #define MX31_CSPISTATUS 0x14 |
660 | #define MX31_STATUS_RR (1 << 3) | |
661 | ||
15ca9215 MK |
662 | #define MX31_CSPI_TESTREG 0x1C |
663 | #define MX31_TEST_LBC (1 << 14) | |
664 | ||
b5f3294f SH |
665 | /* These functions also work for the i.MX35, but be aware that |
666 | * the i.MX35 has a slightly different register layout for bits | |
667 | * we do not use here. | |
668 | */ | |
f989bc69 | 669 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
670 | { |
671 | unsigned int val = 0; | |
672 | ||
673 | if (enable & MXC_INT_TE) | |
674 | val |= MX31_INTREG_TEEN; | |
675 | if (enable & MXC_INT_RR) | |
676 | val |= MX31_INTREG_RREN; | |
677 | ||
6cdeb002 | 678 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
679 | } |
680 | ||
f989bc69 | 681 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
682 | { |
683 | unsigned int reg; | |
684 | ||
6cdeb002 | 685 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 686 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 687 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
688 | } |
689 | ||
e697271c UKK |
690 | static int mx31_prepare_message(struct spi_imx_data *spi_imx, |
691 | struct spi_message *msg) | |
692 | { | |
693 | return 0; | |
694 | } | |
695 | ||
1d374703 UKK |
696 | static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, |
697 | struct spi_device *spi, | |
698 | struct spi_transfer *t) | |
1723e66b UKK |
699 | { |
700 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
2636ba8f | 701 | unsigned int clk; |
1723e66b | 702 | |
3f75720d | 703 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << |
1723e66b | 704 | MX31_CSPICTRL_DR_SHIFT; |
2636ba8f | 705 | spi_imx->spi_bus_clk = clk; |
1723e66b | 706 | |
04ee5854 | 707 | if (is_imx35_cspi(spi_imx)) { |
d52345b6 | 708 | reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; |
2a64a90a SG |
709 | reg |= MX31_CSPICTRL_SSCTL; |
710 | } else { | |
d52345b6 | 711 | reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; |
2a64a90a | 712 | } |
1723e66b | 713 | |
c0c7a5d7 | 714 | if (spi->mode & SPI_CPHA) |
1723e66b | 715 | reg |= MX31_CSPICTRL_PHA; |
c0c7a5d7 | 716 | if (spi->mode & SPI_CPOL) |
1723e66b | 717 | reg |= MX31_CSPICTRL_POL; |
c0c7a5d7 | 718 | if (spi->mode & SPI_CS_HIGH) |
1723e66b | 719 | reg |= MX31_CSPICTRL_SSPOL; |
602c8f44 GU |
720 | if (!gpio_is_valid(spi->cs_gpio)) |
721 | reg |= (spi->chip_select) << | |
04ee5854 SG |
722 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
723 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b | 724 | |
2dd33f9c MK |
725 | if (spi_imx->usedma) |
726 | reg |= MX31_CSPICTRL_SMC; | |
727 | ||
1723e66b UKK |
728 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
729 | ||
15ca9215 MK |
730 | reg = readl(spi_imx->base + MX31_CSPI_TESTREG); |
731 | if (spi->mode & SPI_LOOP) | |
732 | reg |= MX31_TEST_LBC; | |
733 | else | |
734 | reg &= ~MX31_TEST_LBC; | |
735 | writel(reg, spi_imx->base + MX31_CSPI_TESTREG); | |
736 | ||
2dd33f9c | 737 | if (spi_imx->usedma) { |
30d67142 UKK |
738 | /* |
739 | * configure DMA requests when RXFIFO is half full and | |
740 | * when TXFIFO is half empty | |
741 | */ | |
2dd33f9c MK |
742 | writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, |
743 | spi_imx->base + MX31_CSPI_DMAREG); | |
744 | } | |
745 | ||
1723e66b UKK |
746 | return 0; |
747 | } | |
748 | ||
f989bc69 | 749 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 750 | { |
6cdeb002 | 751 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
752 | } |
753 | ||
f989bc69 | 754 | static void mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
755 | { |
756 | /* drain receive buffer */ | |
2a64a90a | 757 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
758 | readl(spi_imx->base + MXC_CSPIRXDATA); |
759 | } | |
760 | ||
3451fb15 SG |
761 | #define MX21_INTREG_RR (1 << 4) |
762 | #define MX21_INTREG_TEEN (1 << 9) | |
763 | #define MX21_INTREG_RREN (1 << 13) | |
764 | ||
765 | #define MX21_CSPICTRL_POL (1 << 5) | |
766 | #define MX21_CSPICTRL_PHA (1 << 6) | |
767 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
768 | #define MX21_CSPICTRL_XCH (1 << 9) | |
769 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
770 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
771 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
772 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
773 | ||
f989bc69 | 774 | static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
775 | { |
776 | unsigned int val = 0; | |
777 | ||
778 | if (enable & MXC_INT_TE) | |
3451fb15 | 779 | val |= MX21_INTREG_TEEN; |
b5f3294f | 780 | if (enable & MXC_INT_RR) |
3451fb15 | 781 | val |= MX21_INTREG_RREN; |
b5f3294f | 782 | |
6cdeb002 | 783 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
784 | } |
785 | ||
f989bc69 | 786 | static void mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
787 | { |
788 | unsigned int reg; | |
789 | ||
6cdeb002 | 790 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 791 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 792 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
793 | } |
794 | ||
e697271c UKK |
795 | static int mx21_prepare_message(struct spi_imx_data *spi_imx, |
796 | struct spi_message *msg) | |
797 | { | |
798 | return 0; | |
799 | } | |
800 | ||
1d374703 UKK |
801 | static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, |
802 | struct spi_device *spi, | |
803 | struct spi_transfer *t) | |
b5f3294f | 804 | { |
3451fb15 | 805 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
04ee5854 | 806 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
32df9ff2 RB |
807 | unsigned int clk; |
808 | ||
3f75720d | 809 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk) |
32df9ff2 RB |
810 | << MX21_CSPICTRL_DR_SHIFT; |
811 | spi_imx->spi_bus_clk = clk; | |
b5f3294f | 812 | |
d52345b6 | 813 | reg |= spi_imx->bits_per_word - 1; |
b5f3294f | 814 | |
c0c7a5d7 | 815 | if (spi->mode & SPI_CPHA) |
3451fb15 | 816 | reg |= MX21_CSPICTRL_PHA; |
c0c7a5d7 | 817 | if (spi->mode & SPI_CPOL) |
3451fb15 | 818 | reg |= MX21_CSPICTRL_POL; |
c0c7a5d7 | 819 | if (spi->mode & SPI_CS_HIGH) |
3451fb15 | 820 | reg |= MX21_CSPICTRL_SSPOL; |
602c8f44 GU |
821 | if (!gpio_is_valid(spi->cs_gpio)) |
822 | reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; | |
b5f3294f | 823 | |
6cdeb002 | 824 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
825 | |
826 | return 0; | |
827 | } | |
828 | ||
f989bc69 | 829 | static int mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 830 | { |
3451fb15 | 831 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
832 | } |
833 | ||
f989bc69 | 834 | static void mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
835 | { |
836 | writel(1, spi_imx->base + MXC_RESET); | |
837 | } | |
838 | ||
b5f3294f SH |
839 | #define MX1_INTREG_RR (1 << 3) |
840 | #define MX1_INTREG_TEEN (1 << 8) | |
841 | #define MX1_INTREG_RREN (1 << 11) | |
842 | ||
843 | #define MX1_CSPICTRL_POL (1 << 4) | |
844 | #define MX1_CSPICTRL_PHA (1 << 5) | |
845 | #define MX1_CSPICTRL_XCH (1 << 8) | |
846 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
847 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
848 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
849 | ||
f989bc69 | 850 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
851 | { |
852 | unsigned int val = 0; | |
853 | ||
854 | if (enable & MXC_INT_TE) | |
855 | val |= MX1_INTREG_TEEN; | |
856 | if (enable & MXC_INT_RR) | |
857 | val |= MX1_INTREG_RREN; | |
858 | ||
6cdeb002 | 859 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
860 | } |
861 | ||
f989bc69 | 862 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
863 | { |
864 | unsigned int reg; | |
865 | ||
6cdeb002 | 866 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 867 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 868 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
869 | } |
870 | ||
e697271c UKK |
871 | static int mx1_prepare_message(struct spi_imx_data *spi_imx, |
872 | struct spi_message *msg) | |
873 | { | |
874 | return 0; | |
875 | } | |
876 | ||
1d374703 UKK |
877 | static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, |
878 | struct spi_device *spi, | |
879 | struct spi_transfer *t) | |
b5f3294f SH |
880 | { |
881 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
2636ba8f | 882 | unsigned int clk; |
b5f3294f | 883 | |
3f75720d | 884 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << |
b5f3294f | 885 | MX1_CSPICTRL_DR_SHIFT; |
2636ba8f MK |
886 | spi_imx->spi_bus_clk = clk; |
887 | ||
d52345b6 | 888 | reg |= spi_imx->bits_per_word - 1; |
b5f3294f | 889 | |
c0c7a5d7 | 890 | if (spi->mode & SPI_CPHA) |
b5f3294f | 891 | reg |= MX1_CSPICTRL_PHA; |
c0c7a5d7 | 892 | if (spi->mode & SPI_CPOL) |
b5f3294f SH |
893 | reg |= MX1_CSPICTRL_POL; |
894 | ||
6cdeb002 | 895 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
896 | |
897 | return 0; | |
898 | } | |
899 | ||
f989bc69 | 900 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 901 | { |
6cdeb002 | 902 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
903 | } |
904 | ||
f989bc69 | 905 | static void mx1_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
906 | { |
907 | writel(1, spi_imx->base + MXC_RESET); | |
908 | } | |
909 | ||
04ee5854 SG |
910 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
911 | .intctrl = mx1_intctrl, | |
e697271c | 912 | .prepare_message = mx1_prepare_message, |
1d374703 | 913 | .prepare_transfer = mx1_prepare_transfer, |
04ee5854 SG |
914 | .trigger = mx1_trigger, |
915 | .rx_available = mx1_rx_available, | |
916 | .reset = mx1_reset, | |
fd8d4e2d | 917 | .fifo_size = 8, |
918 | .has_dmamode = false, | |
1673c81d | 919 | .dynamic_burst = false, |
71abd290 | 920 | .has_slavemode = false, |
04ee5854 SG |
921 | .devtype = IMX1_CSPI, |
922 | }; | |
923 | ||
924 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
925 | .intctrl = mx21_intctrl, | |
e697271c | 926 | .prepare_message = mx21_prepare_message, |
1d374703 | 927 | .prepare_transfer = mx21_prepare_transfer, |
04ee5854 SG |
928 | .trigger = mx21_trigger, |
929 | .rx_available = mx21_rx_available, | |
930 | .reset = mx21_reset, | |
fd8d4e2d | 931 | .fifo_size = 8, |
932 | .has_dmamode = false, | |
1673c81d | 933 | .dynamic_burst = false, |
71abd290 | 934 | .has_slavemode = false, |
04ee5854 SG |
935 | .devtype = IMX21_CSPI, |
936 | }; | |
937 | ||
938 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
939 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
940 | .intctrl = mx21_intctrl, | |
e697271c | 941 | .prepare_message = mx21_prepare_message, |
1d374703 | 942 | .prepare_transfer = mx21_prepare_transfer, |
04ee5854 SG |
943 | .trigger = mx21_trigger, |
944 | .rx_available = mx21_rx_available, | |
945 | .reset = mx21_reset, | |
fd8d4e2d | 946 | .fifo_size = 8, |
947 | .has_dmamode = false, | |
1673c81d | 948 | .dynamic_burst = false, |
71abd290 | 949 | .has_slavemode = false, |
04ee5854 SG |
950 | .devtype = IMX27_CSPI, |
951 | }; | |
952 | ||
953 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
954 | .intctrl = mx31_intctrl, | |
e697271c | 955 | .prepare_message = mx31_prepare_message, |
1d374703 | 956 | .prepare_transfer = mx31_prepare_transfer, |
04ee5854 SG |
957 | .trigger = mx31_trigger, |
958 | .rx_available = mx31_rx_available, | |
959 | .reset = mx31_reset, | |
fd8d4e2d | 960 | .fifo_size = 8, |
961 | .has_dmamode = false, | |
1673c81d | 962 | .dynamic_burst = false, |
71abd290 | 963 | .has_slavemode = false, |
04ee5854 SG |
964 | .devtype = IMX31_CSPI, |
965 | }; | |
966 | ||
967 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
968 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
969 | .intctrl = mx31_intctrl, | |
e697271c | 970 | .prepare_message = mx31_prepare_message, |
1d374703 | 971 | .prepare_transfer = mx31_prepare_transfer, |
04ee5854 SG |
972 | .trigger = mx31_trigger, |
973 | .rx_available = mx31_rx_available, | |
974 | .reset = mx31_reset, | |
fd8d4e2d | 975 | .fifo_size = 8, |
976 | .has_dmamode = true, | |
1673c81d | 977 | .dynamic_burst = false, |
71abd290 | 978 | .has_slavemode = false, |
04ee5854 SG |
979 | .devtype = IMX35_CSPI, |
980 | }; | |
981 | ||
982 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
983 | .intctrl = mx51_ecspi_intctrl, | |
e697271c | 984 | .prepare_message = mx51_ecspi_prepare_message, |
1d374703 | 985 | .prepare_transfer = mx51_ecspi_prepare_transfer, |
04ee5854 SG |
986 | .trigger = mx51_ecspi_trigger, |
987 | .rx_available = mx51_ecspi_rx_available, | |
988 | .reset = mx51_ecspi_reset, | |
987a2dfe | 989 | .setup_wml = mx51_setup_wml, |
fd8d4e2d | 990 | .fifo_size = 64, |
991 | .has_dmamode = true, | |
1673c81d | 992 | .dynamic_burst = true, |
71abd290 | 993 | .has_slavemode = true, |
994 | .disable = mx51_ecspi_disable, | |
04ee5854 SG |
995 | .devtype = IMX51_ECSPI, |
996 | }; | |
997 | ||
26e4bb86 | 998 | static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { |
999 | .intctrl = mx51_ecspi_intctrl, | |
e697271c | 1000 | .prepare_message = mx51_ecspi_prepare_message, |
1d374703 | 1001 | .prepare_transfer = mx51_ecspi_prepare_transfer, |
26e4bb86 | 1002 | .trigger = mx51_ecspi_trigger, |
1003 | .rx_available = mx51_ecspi_rx_available, | |
1004 | .reset = mx51_ecspi_reset, | |
1005 | .fifo_size = 64, | |
1006 | .has_dmamode = true, | |
71abd290 | 1007 | .has_slavemode = true, |
1008 | .disable = mx51_ecspi_disable, | |
26e4bb86 | 1009 | .devtype = IMX53_ECSPI, |
1010 | }; | |
1011 | ||
db1b8200 | 1012 | static const struct platform_device_id spi_imx_devtype[] = { |
04ee5854 SG |
1013 | { |
1014 | .name = "imx1-cspi", | |
1015 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
1016 | }, { | |
1017 | .name = "imx21-cspi", | |
1018 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
1019 | }, { | |
1020 | .name = "imx27-cspi", | |
1021 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
1022 | }, { | |
1023 | .name = "imx31-cspi", | |
1024 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
1025 | }, { | |
1026 | .name = "imx35-cspi", | |
1027 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
1028 | }, { | |
1029 | .name = "imx51-ecspi", | |
1030 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
26e4bb86 | 1031 | }, { |
1032 | .name = "imx53-ecspi", | |
1033 | .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data, | |
04ee5854 SG |
1034 | }, { |
1035 | /* sentinel */ | |
1036 | } | |
f4ba6315 UKK |
1037 | }; |
1038 | ||
22a85e4c SG |
1039 | static const struct of_device_id spi_imx_dt_ids[] = { |
1040 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
1041 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
1042 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
1043 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
1044 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
1045 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
26e4bb86 | 1046 | { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, |
22a85e4c SG |
1047 | { /* sentinel */ } |
1048 | }; | |
27743e0b | 1049 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
22a85e4c | 1050 | |
6cdeb002 | 1051 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 1052 | { |
e6a0a8bf UKK |
1053 | int active = is_active != BITBANG_CS_INACTIVE; |
1054 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 1055 | |
ab2f3572 OR |
1056 | if (spi->mode & SPI_NO_CS) |
1057 | return; | |
1058 | ||
b36581df | 1059 | if (!gpio_is_valid(spi->cs_gpio)) |
b5f3294f | 1060 | return; |
b5f3294f | 1061 | |
b36581df | 1062 | gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
1063 | } |
1064 | ||
2ca300ac MC |
1065 | static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) |
1066 | { | |
1067 | u32 ctrl; | |
1068 | ||
1069 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | |
1070 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | |
1071 | ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); | |
1072 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
1073 | } | |
1074 | ||
6cdeb002 | 1075 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 1076 | { |
2ca300ac MC |
1077 | unsigned int burst_len, fifo_words; |
1078 | ||
1079 | if (spi_imx->dynamic_burst) | |
1080 | fifo_words = 4; | |
1081 | else | |
1082 | fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
1083 | /* | |
1084 | * Reload the FIFO when the remaining bytes to be transferred in the | |
1085 | * current burst is 0. This only applies when bits_per_word is a | |
1086 | * multiple of 8. | |
1087 | */ | |
1088 | if (!spi_imx->remainder) { | |
1089 | if (spi_imx->dynamic_burst) { | |
1090 | ||
1091 | /* We need to deal unaligned data first */ | |
1092 | burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; | |
1093 | ||
1094 | if (!burst_len) | |
1095 | burst_len = MX51_ECSPI_CTRL_MAX_BURST; | |
1096 | ||
1097 | spi_imx_set_burst_len(spi_imx, burst_len * 8); | |
1098 | ||
1099 | spi_imx->remainder = burst_len; | |
1100 | } else { | |
1101 | spi_imx->remainder = fifo_words; | |
1102 | } | |
1103 | } | |
1104 | ||
fd8d4e2d | 1105 | while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { |
6cdeb002 | 1106 | if (!spi_imx->count) |
b5f3294f | 1107 | break; |
2ca300ac | 1108 | if (spi_imx->dynamic_burst && |
30d67142 | 1109 | spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, |
2ca300ac | 1110 | fifo_words)) |
1673c81d | 1111 | break; |
6cdeb002 UKK |
1112 | spi_imx->tx(spi_imx); |
1113 | spi_imx->txfifo++; | |
b5f3294f SH |
1114 | } |
1115 | ||
71abd290 | 1116 | if (!spi_imx->slave_mode) |
1117 | spi_imx->devtype_data->trigger(spi_imx); | |
b5f3294f SH |
1118 | } |
1119 | ||
6cdeb002 | 1120 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 1121 | { |
6cdeb002 | 1122 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 1123 | |
71abd290 | 1124 | while (spi_imx->txfifo && |
1125 | spi_imx->devtype_data->rx_available(spi_imx)) { | |
6cdeb002 UKK |
1126 | spi_imx->rx(spi_imx); |
1127 | spi_imx->txfifo--; | |
b5f3294f SH |
1128 | } |
1129 | ||
6cdeb002 UKK |
1130 | if (spi_imx->count) { |
1131 | spi_imx_push(spi_imx); | |
b5f3294f SH |
1132 | return IRQ_HANDLED; |
1133 | } | |
1134 | ||
6cdeb002 | 1135 | if (spi_imx->txfifo) { |
b5f3294f SH |
1136 | /* No data left to push, but still waiting for rx data, |
1137 | * enable receive data available interrupt. | |
1138 | */ | |
edd501bb | 1139 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 1140 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
1141 | return IRQ_HANDLED; |
1142 | } | |
1143 | ||
edd501bb | 1144 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 1145 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
1146 | |
1147 | return IRQ_HANDLED; | |
1148 | } | |
1149 | ||
65017ee2 | 1150 | static int spi_imx_dma_configure(struct spi_master *master) |
f12ae171 AB |
1151 | { |
1152 | int ret; | |
1153 | enum dma_slave_buswidth buswidth; | |
1154 | struct dma_slave_config rx = {}, tx = {}; | |
1155 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1156 | ||
65017ee2 | 1157 | switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { |
f12ae171 AB |
1158 | case 4: |
1159 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1160 | break; | |
1161 | case 2: | |
1162 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1163 | break; | |
1164 | case 1: | |
1165 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1166 | break; | |
1167 | default: | |
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
1171 | tx.direction = DMA_MEM_TO_DEV; | |
1172 | tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; | |
1173 | tx.dst_addr_width = buswidth; | |
1174 | tx.dst_maxburst = spi_imx->wml; | |
1175 | ret = dmaengine_slave_config(master->dma_tx, &tx); | |
1176 | if (ret) { | |
1177 | dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); | |
1178 | return ret; | |
1179 | } | |
1180 | ||
1181 | rx.direction = DMA_DEV_TO_MEM; | |
1182 | rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; | |
1183 | rx.src_addr_width = buswidth; | |
1184 | rx.src_maxburst = spi_imx->wml; | |
1185 | ret = dmaengine_slave_config(master->dma_rx, &rx); | |
1186 | if (ret) { | |
1187 | dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); | |
1188 | return ret; | |
1189 | } | |
1190 | ||
f12ae171 AB |
1191 | return 0; |
1192 | } | |
1193 | ||
6cdeb002 | 1194 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
1195 | struct spi_transfer *t) |
1196 | { | |
6cdeb002 | 1197 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 1198 | |
abb1ff19 SH |
1199 | if (!t) |
1200 | return 0; | |
1201 | ||
d52345b6 | 1202 | spi_imx->bits_per_word = t->bits_per_word; |
b5f3294f | 1203 | |
2801b2f5 MC |
1204 | /* |
1205 | * Initialize the functions for transfer. To transfer non byte-aligned | |
1206 | * words, we have to use multiple word-size bursts, we can't use | |
1207 | * dynamic_burst in that case. | |
1208 | */ | |
1209 | if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && | |
1210 | (spi_imx->bits_per_word == 8 || | |
1211 | spi_imx->bits_per_word == 16 || | |
1212 | spi_imx->bits_per_word == 32)) { | |
1673c81d | 1213 | |
1673c81d | 1214 | spi_imx->rx = spi_imx_buf_rx_swap; |
1215 | spi_imx->tx = spi_imx_buf_tx_swap; | |
1216 | spi_imx->dynamic_burst = 1; | |
1673c81d | 1217 | |
6051426f | 1218 | } else { |
1673c81d | 1219 | if (spi_imx->bits_per_word <= 8) { |
1220 | spi_imx->rx = spi_imx_buf_rx_u8; | |
1221 | spi_imx->tx = spi_imx_buf_tx_u8; | |
1222 | } else if (spi_imx->bits_per_word <= 16) { | |
1223 | spi_imx->rx = spi_imx_buf_rx_u16; | |
1224 | spi_imx->tx = spi_imx_buf_tx_u16; | |
1225 | } else { | |
1226 | spi_imx->rx = spi_imx_buf_rx_u32; | |
1227 | spi_imx->tx = spi_imx_buf_tx_u32; | |
1228 | } | |
2ca300ac | 1229 | spi_imx->dynamic_burst = 0; |
24778be2 | 1230 | } |
e6a0a8bf | 1231 | |
c008a800 SH |
1232 | if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) |
1233 | spi_imx->usedma = 1; | |
1234 | else | |
1235 | spi_imx->usedma = 0; | |
1236 | ||
71abd290 | 1237 | if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { |
1238 | spi_imx->rx = mx53_ecspi_rx_slave; | |
1239 | spi_imx->tx = mx53_ecspi_tx_slave; | |
1240 | spi_imx->slave_burst = t->len; | |
1241 | } | |
1242 | ||
1d374703 | 1243 | spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); |
b5f3294f SH |
1244 | |
1245 | return 0; | |
1246 | } | |
1247 | ||
f62caccd RG |
1248 | static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) |
1249 | { | |
1250 | struct spi_master *master = spi_imx->bitbang.master; | |
1251 | ||
1252 | if (master->dma_rx) { | |
1253 | dma_release_channel(master->dma_rx); | |
1254 | master->dma_rx = NULL; | |
1255 | } | |
1256 | ||
1257 | if (master->dma_tx) { | |
1258 | dma_release_channel(master->dma_tx); | |
1259 | master->dma_tx = NULL; | |
1260 | } | |
f62caccd RG |
1261 | } |
1262 | ||
1263 | static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, | |
f12ae171 | 1264 | struct spi_master *master) |
f62caccd | 1265 | { |
f62caccd RG |
1266 | int ret; |
1267 | ||
a02bb401 RG |
1268 | /* use pio mode for i.mx6dl chip TKT238285 */ |
1269 | if (of_machine_is_compatible("fsl,imx6dl")) | |
1270 | return 0; | |
1271 | ||
fd8d4e2d | 1272 | spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; |
0dfbaa89 | 1273 | |
f62caccd | 1274 | /* Prepare for TX DMA: */ |
3760047a AB |
1275 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); |
1276 | if (IS_ERR(master->dma_tx)) { | |
1277 | ret = PTR_ERR(master->dma_tx); | |
1278 | dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); | |
1279 | master->dma_tx = NULL; | |
f62caccd RG |
1280 | goto err; |
1281 | } | |
1282 | ||
f62caccd | 1283 | /* Prepare for RX : */ |
3760047a AB |
1284 | master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); |
1285 | if (IS_ERR(master->dma_rx)) { | |
1286 | ret = PTR_ERR(master->dma_rx); | |
1287 | dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); | |
1288 | master->dma_rx = NULL; | |
f62caccd RG |
1289 | goto err; |
1290 | } | |
1291 | ||
f62caccd RG |
1292 | init_completion(&spi_imx->dma_rx_completion); |
1293 | init_completion(&spi_imx->dma_tx_completion); | |
1294 | master->can_dma = spi_imx_can_dma; | |
1295 | master->max_dma_len = MAX_SDMA_BD_BYTES; | |
1296 | spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | | |
1297 | SPI_MASTER_MUST_TX; | |
f62caccd RG |
1298 | |
1299 | return 0; | |
1300 | err: | |
1301 | spi_imx_sdma_exit(spi_imx); | |
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | static void spi_imx_dma_rx_callback(void *cookie) | |
1306 | { | |
1307 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
1308 | ||
1309 | complete(&spi_imx->dma_rx_completion); | |
1310 | } | |
1311 | ||
1312 | static void spi_imx_dma_tx_callback(void *cookie) | |
1313 | { | |
1314 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
1315 | ||
1316 | complete(&spi_imx->dma_tx_completion); | |
1317 | } | |
1318 | ||
4bfe927a AB |
1319 | static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) |
1320 | { | |
1321 | unsigned long timeout = 0; | |
1322 | ||
1323 | /* Time with actual data transfer and CS change delay related to HW */ | |
1324 | timeout = (8 + 4) * size / spi_imx->spi_bus_clk; | |
1325 | ||
1326 | /* Add extra second for scheduler related activities */ | |
1327 | timeout += 1; | |
1328 | ||
1329 | /* Double calculated timeout */ | |
1330 | return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); | |
1331 | } | |
1332 | ||
f62caccd RG |
1333 | static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
1334 | struct spi_transfer *transfer) | |
1335 | { | |
6b6192c0 | 1336 | struct dma_async_tx_descriptor *desc_tx, *desc_rx; |
4bfe927a | 1337 | unsigned long transfer_timeout; |
56536a7f | 1338 | unsigned long timeout; |
f62caccd RG |
1339 | struct spi_master *master = spi_imx->bitbang.master; |
1340 | struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; | |
5ba5a373 RG |
1341 | struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); |
1342 | unsigned int bytes_per_word, i; | |
987a2dfe RG |
1343 | int ret; |
1344 | ||
5ba5a373 RG |
1345 | /* Get the right burst length from the last sg to ensure no tail data */ |
1346 | bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); | |
1347 | for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { | |
1348 | if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) | |
1349 | break; | |
1350 | } | |
1351 | /* Use 1 as wml in case no available burst length got */ | |
1352 | if (i == 0) | |
1353 | i = 1; | |
1354 | ||
1355 | spi_imx->wml = i; | |
1356 | ||
987a2dfe RG |
1357 | ret = spi_imx_dma_configure(master); |
1358 | if (ret) | |
1359 | return ret; | |
1360 | ||
5ba5a373 RG |
1361 | if (!spi_imx->devtype_data->setup_wml) { |
1362 | dev_err(spi_imx->dev, "No setup_wml()?\n"); | |
1363 | return -EINVAL; | |
1364 | } | |
987a2dfe | 1365 | spi_imx->devtype_data->setup_wml(spi_imx); |
f62caccd | 1366 | |
6b6192c0 SH |
1367 | /* |
1368 | * The TX DMA setup starts the transfer, so make sure RX is configured | |
1369 | * before TX. | |
1370 | */ | |
1371 | desc_rx = dmaengine_prep_slave_sg(master->dma_rx, | |
1372 | rx->sgl, rx->nents, DMA_DEV_TO_MEM, | |
1373 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1374 | if (!desc_rx) | |
1375 | return -EINVAL; | |
f62caccd | 1376 | |
6b6192c0 SH |
1377 | desc_rx->callback = spi_imx_dma_rx_callback; |
1378 | desc_rx->callback_param = (void *)spi_imx; | |
1379 | dmaengine_submit(desc_rx); | |
1380 | reinit_completion(&spi_imx->dma_rx_completion); | |
1381 | dma_async_issue_pending(master->dma_rx); | |
f62caccd | 1382 | |
6b6192c0 SH |
1383 | desc_tx = dmaengine_prep_slave_sg(master->dma_tx, |
1384 | tx->sgl, tx->nents, DMA_MEM_TO_DEV, | |
1385 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1386 | if (!desc_tx) { | |
1387 | dmaengine_terminate_all(master->dma_tx); | |
1388 | return -EINVAL; | |
f62caccd RG |
1389 | } |
1390 | ||
6b6192c0 SH |
1391 | desc_tx->callback = spi_imx_dma_tx_callback; |
1392 | desc_tx->callback_param = (void *)spi_imx; | |
1393 | dmaengine_submit(desc_tx); | |
f62caccd | 1394 | reinit_completion(&spi_imx->dma_tx_completion); |
fab44ef1 | 1395 | dma_async_issue_pending(master->dma_tx); |
f62caccd | 1396 | |
4bfe927a AB |
1397 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1398 | ||
f62caccd | 1399 | /* Wait SDMA to finish the data transfer.*/ |
56536a7f | 1400 | timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
4bfe927a | 1401 | transfer_timeout); |
56536a7f | 1402 | if (!timeout) { |
6aa800ca | 1403 | dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); |
f62caccd | 1404 | dmaengine_terminate_all(master->dma_tx); |
e47b33c0 | 1405 | dmaengine_terminate_all(master->dma_rx); |
6b6192c0 | 1406 | return -ETIMEDOUT; |
f62caccd RG |
1407 | } |
1408 | ||
6b6192c0 SH |
1409 | timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, |
1410 | transfer_timeout); | |
1411 | if (!timeout) { | |
1412 | dev_err(&master->dev, "I/O Error in DMA RX\n"); | |
1413 | spi_imx->devtype_data->reset(spi_imx); | |
1414 | dmaengine_terminate_all(master->dma_rx); | |
1415 | return -ETIMEDOUT; | |
1416 | } | |
f62caccd | 1417 | |
6b6192c0 | 1418 | return transfer->len; |
f62caccd RG |
1419 | } |
1420 | ||
1421 | static int spi_imx_pio_transfer(struct spi_device *spi, | |
b5f3294f SH |
1422 | struct spi_transfer *transfer) |
1423 | { | |
6cdeb002 | 1424 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
ff1ba3da CG |
1425 | unsigned long transfer_timeout; |
1426 | unsigned long timeout; | |
b5f3294f | 1427 | |
6cdeb002 UKK |
1428 | spi_imx->tx_buf = transfer->tx_buf; |
1429 | spi_imx->rx_buf = transfer->rx_buf; | |
1430 | spi_imx->count = transfer->len; | |
1431 | spi_imx->txfifo = 0; | |
2ca300ac | 1432 | spi_imx->remainder = 0; |
b5f3294f | 1433 | |
aa0fe826 | 1434 | reinit_completion(&spi_imx->xfer_done); |
b5f3294f | 1435 | |
6cdeb002 | 1436 | spi_imx_push(spi_imx); |
b5f3294f | 1437 | |
edd501bb | 1438 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 1439 | |
ff1ba3da CG |
1440 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1441 | ||
1442 | timeout = wait_for_completion_timeout(&spi_imx->xfer_done, | |
1443 | transfer_timeout); | |
1444 | if (!timeout) { | |
1445 | dev_err(&spi->dev, "I/O Error in PIO\n"); | |
1446 | spi_imx->devtype_data->reset(spi_imx); | |
1447 | return -ETIMEDOUT; | |
1448 | } | |
b5f3294f SH |
1449 | |
1450 | return transfer->len; | |
1451 | } | |
1452 | ||
71abd290 | 1453 | static int spi_imx_pio_transfer_slave(struct spi_device *spi, |
1454 | struct spi_transfer *transfer) | |
1455 | { | |
1456 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); | |
1457 | int ret = transfer->len; | |
1458 | ||
1459 | if (is_imx53_ecspi(spi_imx) && | |
1460 | transfer->len > MX53_MAX_TRANSFER_BYTES) { | |
1461 | dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", | |
1462 | MX53_MAX_TRANSFER_BYTES); | |
1463 | return -EMSGSIZE; | |
1464 | } | |
1465 | ||
1466 | spi_imx->tx_buf = transfer->tx_buf; | |
1467 | spi_imx->rx_buf = transfer->rx_buf; | |
1468 | spi_imx->count = transfer->len; | |
1469 | spi_imx->txfifo = 0; | |
2ca300ac | 1470 | spi_imx->remainder = 0; |
71abd290 | 1471 | |
1472 | reinit_completion(&spi_imx->xfer_done); | |
1473 | spi_imx->slave_aborted = false; | |
1474 | ||
1475 | spi_imx_push(spi_imx); | |
1476 | ||
1477 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); | |
1478 | ||
1479 | if (wait_for_completion_interruptible(&spi_imx->xfer_done) || | |
1480 | spi_imx->slave_aborted) { | |
1481 | dev_dbg(&spi->dev, "interrupted\n"); | |
1482 | ret = -EINTR; | |
1483 | } | |
1484 | ||
1485 | /* ecspi has a HW issue when works in Slave mode, | |
1486 | * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, | |
1487 | * ECSPI_TXDATA keeps shift out the last word data, | |
1488 | * so we have to disable ECSPI when in slave mode after the | |
1489 | * transfer completes | |
1490 | */ | |
1491 | if (spi_imx->devtype_data->disable) | |
1492 | spi_imx->devtype_data->disable(spi_imx); | |
1493 | ||
1494 | return ret; | |
1495 | } | |
1496 | ||
f62caccd RG |
1497 | static int spi_imx_transfer(struct spi_device *spi, |
1498 | struct spi_transfer *transfer) | |
1499 | { | |
f62caccd RG |
1500 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
1501 | ||
71abd290 | 1502 | /* flush rxfifo before transfer */ |
1503 | while (spi_imx->devtype_data->rx_available(spi_imx)) | |
c842749e | 1504 | readl(spi_imx->base + MXC_CSPIRXDATA); |
71abd290 | 1505 | |
1506 | if (spi_imx->slave_mode) | |
1507 | return spi_imx_pio_transfer_slave(spi, transfer); | |
1508 | ||
c008a800 | 1509 | if (spi_imx->usedma) |
99f1cf1c | 1510 | return spi_imx_dma_transfer(spi_imx, transfer); |
c008a800 SH |
1511 | else |
1512 | return spi_imx_pio_transfer(spi, transfer); | |
f62caccd RG |
1513 | } |
1514 | ||
6cdeb002 | 1515 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 1516 | { |
f4d4ecfe | 1517 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
1518 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
1519 | ||
ab2f3572 OR |
1520 | if (spi->mode & SPI_NO_CS) |
1521 | return 0; | |
1522 | ||
b36581df AS |
1523 | if (gpio_is_valid(spi->cs_gpio)) |
1524 | gpio_direction_output(spi->cs_gpio, | |
1525 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
6c23e5d4 | 1526 | |
6cdeb002 | 1527 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
1528 | |
1529 | return 0; | |
1530 | } | |
1531 | ||
6cdeb002 | 1532 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
1533 | { |
1534 | } | |
1535 | ||
9e556dcc HS |
1536 | static int |
1537 | spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) | |
1538 | { | |
1539 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1540 | int ret; | |
1541 | ||
1542 | ret = clk_enable(spi_imx->clk_per); | |
1543 | if (ret) | |
1544 | return ret; | |
1545 | ||
1546 | ret = clk_enable(spi_imx->clk_ipg); | |
1547 | if (ret) { | |
1548 | clk_disable(spi_imx->clk_per); | |
1549 | return ret; | |
1550 | } | |
1551 | ||
e697271c UKK |
1552 | ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); |
1553 | if (ret) { | |
1554 | clk_disable(spi_imx->clk_ipg); | |
1555 | clk_disable(spi_imx->clk_per); | |
1556 | } | |
1557 | ||
1558 | return ret; | |
9e556dcc HS |
1559 | } |
1560 | ||
1561 | static int | |
1562 | spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) | |
1563 | { | |
1564 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1565 | ||
1566 | clk_disable(spi_imx->clk_ipg); | |
1567 | clk_disable(spi_imx->clk_per); | |
1568 | return 0; | |
1569 | } | |
1570 | ||
71abd290 | 1571 | static int spi_imx_slave_abort(struct spi_master *master) |
1572 | { | |
1573 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1574 | ||
1575 | spi_imx->slave_aborted = true; | |
1576 | complete(&spi_imx->xfer_done); | |
1577 | ||
1578 | return 0; | |
1579 | } | |
1580 | ||
fd4a319b | 1581 | static int spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 1582 | { |
22a85e4c SG |
1583 | struct device_node *np = pdev->dev.of_node; |
1584 | const struct of_device_id *of_id = | |
1585 | of_match_device(spi_imx_dt_ids, &pdev->dev); | |
1586 | struct spi_imx_master *mxc_platform_info = | |
1587 | dev_get_platdata(&pdev->dev); | |
b5f3294f | 1588 | struct spi_master *master; |
6cdeb002 | 1589 | struct spi_imx_data *spi_imx; |
b5f3294f | 1590 | struct resource *res; |
f72efa7e | 1591 | int i, ret, irq, spi_drctl; |
71abd290 | 1592 | const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : |
1593 | (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; | |
1594 | bool slave_mode; | |
b5f3294f | 1595 | |
22a85e4c | 1596 | if (!np && !mxc_platform_info) { |
b5f3294f SH |
1597 | dev_err(&pdev->dev, "can't get the platform data\n"); |
1598 | return -EINVAL; | |
1599 | } | |
1600 | ||
71abd290 | 1601 | slave_mode = devtype_data->has_slavemode && |
1602 | of_property_read_bool(np, "spi-slave"); | |
1603 | if (slave_mode) | |
1604 | master = spi_alloc_slave(&pdev->dev, | |
1605 | sizeof(struct spi_imx_data)); | |
1606 | else | |
1607 | master = spi_alloc_master(&pdev->dev, | |
1608 | sizeof(struct spi_imx_data)); | |
2c147776 FE |
1609 | if (!master) |
1610 | return -ENOMEM; | |
1611 | ||
f72efa7e LM |
1612 | ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); |
1613 | if ((ret < 0) || (spi_drctl >= 0x3)) { | |
1614 | /* '11' is reserved */ | |
1615 | spi_drctl = 0; | |
1616 | } | |
1617 | ||
b5f3294f SH |
1618 | platform_set_drvdata(pdev, master); |
1619 | ||
24778be2 | 1620 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
b36581df | 1621 | master->bus_num = np ? -1 : pdev->id; |
b5f3294f | 1622 | |
6cdeb002 | 1623 | spi_imx = spi_master_get_devdata(master); |
94c69f76 | 1624 | spi_imx->bitbang.master = master; |
6aa800ca | 1625 | spi_imx->dev = &pdev->dev; |
71abd290 | 1626 | spi_imx->slave_mode = slave_mode; |
b5f3294f | 1627 | |
71abd290 | 1628 | spi_imx->devtype_data = devtype_data; |
4686d1c3 | 1629 | |
881a0b99 | 1630 | /* Get number of chip selects, either platform data or OF */ |
b36581df AS |
1631 | if (mxc_platform_info) { |
1632 | master->num_chipselect = mxc_platform_info->num_chipselect; | |
ffd4db9e | 1633 | if (mxc_platform_info->chipselect) { |
a86854d0 KC |
1634 | master->cs_gpios = devm_kcalloc(&master->dev, |
1635 | master->num_chipselect, sizeof(int), | |
1636 | GFP_KERNEL); | |
ffd4db9e TP |
1637 | if (!master->cs_gpios) |
1638 | return -ENOMEM; | |
1639 | ||
1640 | for (i = 0; i < master->num_chipselect; i++) | |
1641 | master->cs_gpios[i] = mxc_platform_info->chipselect[i]; | |
1642 | } | |
881a0b99 TP |
1643 | } else { |
1644 | u32 num_cs; | |
1645 | ||
1646 | if (!of_property_read_u32(np, "num-cs", &num_cs)) | |
1647 | master->num_chipselect = num_cs; | |
1648 | /* If not preset, default value of 1 is used */ | |
1649 | } | |
b5f3294f | 1650 | |
6cdeb002 UKK |
1651 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
1652 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
1653 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
1654 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
1655 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
9e556dcc HS |
1656 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
1657 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; | |
71abd290 | 1658 | spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; |
ab2f3572 OR |
1659 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
1660 | | SPI_NO_CS; | |
26e4bb86 | 1661 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || |
1662 | is_imx53_ecspi(spi_imx)) | |
f72efa7e LM |
1663 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; |
1664 | ||
1665 | spi_imx->spi_drctl = spi_drctl; | |
b5f3294f | 1666 | |
6cdeb002 | 1667 | init_completion(&spi_imx->xfer_done); |
b5f3294f SH |
1668 | |
1669 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130b82c0 FE |
1670 | spi_imx->base = devm_ioremap_resource(&pdev->dev, res); |
1671 | if (IS_ERR(spi_imx->base)) { | |
1672 | ret = PTR_ERR(spi_imx->base); | |
1673 | goto out_master_put; | |
b5f3294f | 1674 | } |
f12ae171 | 1675 | spi_imx->base_phys = res->start; |
b5f3294f | 1676 | |
4b5d6aad FE |
1677 | irq = platform_get_irq(pdev, 0); |
1678 | if (irq < 0) { | |
1679 | ret = irq; | |
130b82c0 | 1680 | goto out_master_put; |
b5f3294f SH |
1681 | } |
1682 | ||
4b5d6aad | 1683 | ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, |
8fc39b51 | 1684 | dev_name(&pdev->dev), spi_imx); |
b5f3294f | 1685 | if (ret) { |
4b5d6aad | 1686 | dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); |
130b82c0 | 1687 | goto out_master_put; |
b5f3294f SH |
1688 | } |
1689 | ||
aa29d840 SH |
1690 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1691 | if (IS_ERR(spi_imx->clk_ipg)) { | |
1692 | ret = PTR_ERR(spi_imx->clk_ipg); | |
130b82c0 | 1693 | goto out_master_put; |
b5f3294f SH |
1694 | } |
1695 | ||
aa29d840 SH |
1696 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
1697 | if (IS_ERR(spi_imx->clk_per)) { | |
1698 | ret = PTR_ERR(spi_imx->clk_per); | |
130b82c0 | 1699 | goto out_master_put; |
aa29d840 SH |
1700 | } |
1701 | ||
83174626 FE |
1702 | ret = clk_prepare_enable(spi_imx->clk_per); |
1703 | if (ret) | |
1704 | goto out_master_put; | |
1705 | ||
1706 | ret = clk_prepare_enable(spi_imx->clk_ipg); | |
1707 | if (ret) | |
1708 | goto out_put_per; | |
aa29d840 SH |
1709 | |
1710 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
f62caccd | 1711 | /* |
2dd33f9c MK |
1712 | * Only validated on i.mx35 and i.mx6 now, can remove the constraint |
1713 | * if validated on other chips. | |
f62caccd | 1714 | */ |
fd8d4e2d | 1715 | if (spi_imx->devtype_data->has_dmamode) { |
f12ae171 | 1716 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); |
bf9af08c AB |
1717 | if (ret == -EPROBE_DEFER) |
1718 | goto out_clk_put; | |
1719 | ||
3760047a AB |
1720 | if (ret < 0) |
1721 | dev_err(&pdev->dev, "dma setup error %d, use pio\n", | |
1722 | ret); | |
1723 | } | |
b5f3294f | 1724 | |
edd501bb | 1725 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 1726 | |
edd501bb | 1727 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 1728 | |
22a85e4c | 1729 | master->dev.of_node = pdev->dev.of_node; |
8197f489 TP |
1730 | ret = spi_bitbang_start(&spi_imx->bitbang); |
1731 | if (ret) { | |
1732 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
1733 | goto out_clk_put; | |
1734 | } | |
b5f3294f | 1735 | |
881a0b99 TP |
1736 | /* Request GPIO CS lines, if any */ |
1737 | if (!spi_imx->slave_mode && master->cs_gpios) { | |
71abd290 | 1738 | for (i = 0; i < master->num_chipselect; i++) { |
1739 | if (!gpio_is_valid(master->cs_gpios[i])) | |
1740 | continue; | |
1741 | ||
1742 | ret = devm_gpio_request(&pdev->dev, | |
1743 | master->cs_gpios[i], | |
1744 | DRIVER_NAME); | |
1745 | if (ret) { | |
1746 | dev_err(&pdev->dev, "Can't get CS GPIO %i\n", | |
1747 | master->cs_gpios[i]); | |
4e21791e | 1748 | goto out_spi_bitbang; |
71abd290 | 1749 | } |
1750 | } | |
b36581df AS |
1751 | } |
1752 | ||
b5f3294f SH |
1753 | dev_info(&pdev->dev, "probed\n"); |
1754 | ||
9e556dcc HS |
1755 | clk_disable(spi_imx->clk_ipg); |
1756 | clk_disable(spi_imx->clk_per); | |
b5f3294f SH |
1757 | return ret; |
1758 | ||
4e21791e TP |
1759 | out_spi_bitbang: |
1760 | spi_bitbang_stop(&spi_imx->bitbang); | |
b5f3294f | 1761 | out_clk_put: |
aa29d840 | 1762 | clk_disable_unprepare(spi_imx->clk_ipg); |
83174626 FE |
1763 | out_put_per: |
1764 | clk_disable_unprepare(spi_imx->clk_per); | |
130b82c0 | 1765 | out_master_put: |
b5f3294f | 1766 | spi_master_put(master); |
130b82c0 | 1767 | |
b5f3294f SH |
1768 | return ret; |
1769 | } | |
1770 | ||
fd4a319b | 1771 | static int spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
1772 | { |
1773 | struct spi_master *master = platform_get_drvdata(pdev); | |
6cdeb002 | 1774 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
d593574a | 1775 | int ret; |
b5f3294f | 1776 | |
6cdeb002 | 1777 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 1778 | |
d593574a SA |
1779 | ret = clk_enable(spi_imx->clk_per); |
1780 | if (ret) | |
1781 | return ret; | |
1782 | ||
1783 | ret = clk_enable(spi_imx->clk_ipg); | |
1784 | if (ret) { | |
1785 | clk_disable(spi_imx->clk_per); | |
1786 | return ret; | |
1787 | } | |
1788 | ||
6cdeb002 | 1789 | writel(0, spi_imx->base + MXC_CSPICTRL); |
d593574a SA |
1790 | clk_disable_unprepare(spi_imx->clk_ipg); |
1791 | clk_disable_unprepare(spi_imx->clk_per); | |
f62caccd | 1792 | spi_imx_sdma_exit(spi_imx); |
b5f3294f SH |
1793 | spi_master_put(master); |
1794 | ||
b5f3294f SH |
1795 | return 0; |
1796 | } | |
1797 | ||
6cdeb002 | 1798 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
1799 | .driver = { |
1800 | .name = DRIVER_NAME, | |
22a85e4c | 1801 | .of_match_table = spi_imx_dt_ids, |
b5f3294f | 1802 | }, |
f4ba6315 | 1803 | .id_table = spi_imx_devtype, |
6cdeb002 | 1804 | .probe = spi_imx_probe, |
fd4a319b | 1805 | .remove = spi_imx_remove, |
b5f3294f | 1806 | }; |
940ab889 | 1807 | module_platform_driver(spi_imx_driver); |
b5f3294f | 1808 | |
af82800c | 1809 | MODULE_DESCRIPTION("SPI Controller driver"); |
b5f3294f SH |
1810 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
1811 | MODULE_LICENSE("GPL"); | |
3133fba3 | 1812 | MODULE_ALIAS("platform:" DRIVER_NAME); |