[linux-2.6-block.git] / drivers / spi / spi-hisi-sfc-v3xx.c

// SPDX-License-Identifier: GPL-2.0-only
//
// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
//
// Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
// Author: John Garry <john.garry@huawei.com>

#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/completion.h>
#include <linux/dmi.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>

#define HISI_SFC_V3XX_VERSION (0x1f8)

#define HISI_SFC_V3XX_GLB_CFG (0x100)
#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
#define HISI_SFC_V3XX_INT_STAT (0x124)
#define HISI_SFC_V3XX_INT_MASK (0x128)
#define HISI_SFC_V3XX_INT_CLR (0x12c)
#define HISI_SFC_V3XX_CMD_CFG (0x300)
#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
#define HISI_SFC_V3XX_CMD_INS (0x308)
#define HISI_SFC_V3XX_CMD_ADDR (0x30c)
#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)

/* Common definition of interrupt bit masks */
#define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff)	/* all the masks */
#define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0)	/* command execution complete */
#define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2)	/* page progrom error */
#define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5)	/* error visiting inaccessible/
						 * protected address
						 */

/* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */
#define HISI_SFC_V3XX_STD (0 << 17)
#define HISI_SFC_V3XX_DIDO (1 << 17)
#define HISI_SFC_V3XX_DIO (2 << 17)
#define HISI_SFC_V3XX_FULL_DIO (3 << 17)
#define HISI_SFC_V3XX_QIQO (5 << 17)
#define HISI_SFC_V3XX_QIO (6 << 17)
#define HISI_SFC_V3XX_FULL_QIO (7 << 17)

/*
 * The IO modes lookup table. hisi_sfc_v3xx_io_modes[(z - 1) / 2][y / 2][x / 2]
 * stands for x-y-z mode, as described in SFDP terminology. -EIO indicates
 * an invalid mode.
 */
static const int hisi_sfc_v3xx_io_modes[2][3][3] = {
	{
		{ HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO },
		{ HISI_SFC_V3XX_DIO, HISI_SFC_V3XX_FULL_DIO, -EIO },
		{ -EIO, -EIO, -EIO },
	},
	{
		{ HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO },
		{ -EIO, -EIO, -EIO },
		{ HISI_SFC_V3XX_QIO, -EIO, HISI_SFC_V3XX_FULL_QIO },
	},
};

struct hisi_sfc_v3xx_host {
	struct device *dev;
	void __iomem *regbase;
	int max_cmd_dword;
	struct completion *completion;
	u8 address_mode;
	int irq;
};

static void hisi_sfc_v3xx_disable_int(struct hisi_sfc_v3xx_host *host)
{
	writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
}

static void hisi_sfc_v3xx_enable_int(struct hisi_sfc_v3xx_host *host)
{
	writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
}

static void hisi_sfc_v3xx_clear_int(struct hisi_sfc_v3xx_host *host)
{
	writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
}

/*
 * The interrupt status register indicates whether an error occurs
 * after per operation. Check it, and clear the interrupts for
 * next time judgement.
 */
static int hisi_sfc_v3xx_handle_completion(struct hisi_sfc_v3xx_host *host)
{
	u32 reg;

	reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT);
	hisi_sfc_v3xx_clear_int(host);

	if (reg & HISI_SFC_V3XX_INT_MASK_IACCES) {
		dev_err(host->dev, "fail to access protected address\n");
		return -EIO;
	}

	if (reg & HISI_SFC_V3XX_INT_MASK_PP_ERR) {
		dev_err(host->dev, "page program operation failed\n");
		return -EIO;
	}

	/*
	 * The other bits of the interrupt registers is not currently
	 * used and probably not be triggered in this driver. When it
	 * happens, we regard it as an unsupported error here.
	 */
	if (!(reg & HISI_SFC_V3XX_INT_MASK_CPLT)) {
		dev_err(host->dev, "unsupported error occurred, status=0x%x\n", reg);
		return -EIO;
	}

	return 0;
}

#define HISI_SFC_V3XX_WAIT_TIMEOUT_US		1000000
#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US	10

static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
{
	u32 reg;

	return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
				  !(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
				  HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
				  HISI_SFC_V3XX_WAIT_TIMEOUT_US);
}

static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
					struct spi_mem_op *op)
{
	struct spi_device *spi = mem->spi;
	struct hisi_sfc_v3xx_host *host;
	uintptr_t addr = (uintptr_t)op->data.buf.in;
	int max_byte_count;

	host = spi_controller_get_devdata(spi->master);

	max_byte_count = host->max_cmd_dword * 4;

	if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
		op->data.nbytes = 4 - (addr % 4);
	else if (op->data.nbytes > max_byte_count)
		op->data.nbytes = max_byte_count;

	return 0;
}

/*
 * The controller only supports Standard SPI mode, Duall mode and
 * Quad mode. Double sanitize the ops here to avoid OOB access.
 */
static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
				      const struct spi_mem_op *op)
{
	struct spi_device *spi = mem->spi;
	struct hisi_sfc_v3xx_host *host;

	host = spi_controller_get_devdata(spi->master);

	if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
	    op->addr.buswidth > 4 || op->cmd.buswidth > 4)
		return false;

	if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
		return false;

	return spi_mem_default_supports_op(mem, op);
}

/*
 * memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
 * DATABUF registers -so use __io{read,write}32_copy when possible. For
 * trailing bytes, copy them byte-by-byte from the DATABUF register, as we
 * can't clobber outside the source/dest buffer.
 *
 * For efficient data read/write, we try to put any start 32b unaligned data
 * into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
 */
static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
				       u8 *to, unsigned int len)
{
	void __iomem *from;
	int i;

	from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;

	if (IS_ALIGNED((uintptr_t)to, 4)) {
		int words = len / 4;

		__ioread32_copy(to, from, words);

		len -= words * 4;
		if (len) {
			u32 val;

			to += words * 4;
			from += words * 4;

			val = __raw_readl(from);

			for (i = 0; i < len; i++, val >>= 8, to++)
				*to = (u8)val;
		}
	} else {
		for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
			u32 val = __raw_readl(from);
			int j;

			for (j = 0; j < 4 && (j + (i * 4) < len);
			     to++, val >>= 8, j++)
				*to = (u8)val;
		}
	}
}

static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
					const u8 *from, unsigned int len)
{
	void __iomem *to;
	int i;

	to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;

	if (IS_ALIGNED((uintptr_t)from, 4)) {
		int words = len / 4;

		__iowrite32_copy(to, from, words);

		len -= words * 4;
		if (len) {
			u32 val = 0;

			to += words * 4;
			from += words * 4;

			for (i = 0; i < len; i++, from++)
				val |= *from << i * 8;
			__raw_writel(val, to);
		}

	} else {
		for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
			u32 val = 0;
			int j;

			for (j = 0; j < 4 && (j + (i * 4) < len);
			     from++, j++)
				val |= *from << j * 8;
			__raw_writel(val, to);
		}
	}
}

static int hisi_sfc_v3xx_start_bus(struct hisi_sfc_v3xx_host *host,
				   const struct spi_mem_op *op,
				   u8 chip_select)
{
	int len = op->data.nbytes, buswidth_mode;
	u32 config = 0;

	if (op->addr.nbytes)
		config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;

	if (op->data.buswidth == 0 || op->data.buswidth == 1) {
		buswidth_mode = HISI_SFC_V3XX_STD;
	} else {
		int data_idx, addr_idx, cmd_idx;

		data_idx = (op->data.buswidth - 1) / 2;
		addr_idx = op->addr.buswidth / 2;
		cmd_idx = op->cmd.buswidth / 2;
		buswidth_mode = hisi_sfc_v3xx_io_modes[data_idx][addr_idx][cmd_idx];
	}
	if (buswidth_mode < 0)
		return buswidth_mode;
	config |= buswidth_mode;

	if (op->data.dir != SPI_MEM_NO_DATA) {
		config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
		config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
	}

	if (op->data.dir == SPI_MEM_DATA_IN)
		config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;

	config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
		  chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
		  HISI_SFC_V3XX_CMD_CFG_START_MSK;

	writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
	writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);

	writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);

	return 0;
}

static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
					 const struct spi_mem_op *op,
					 u8 chip_select)
{
	DECLARE_COMPLETION_ONSTACK(done);
	int ret;

	if (host->irq) {
		host->completion = &done;
		hisi_sfc_v3xx_enable_int(host);
	}

	if (op->data.dir == SPI_MEM_DATA_OUT)
		hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, op->data.nbytes);

	ret = hisi_sfc_v3xx_start_bus(host, op, chip_select);
	if (ret)
		return ret;

	if (host->irq) {
		ret = wait_for_completion_timeout(host->completion,
						  usecs_to_jiffies(HISI_SFC_V3XX_WAIT_TIMEOUT_US));
		if (!ret)
			ret = -ETIMEDOUT;
		else
			ret = 0;

		hisi_sfc_v3xx_disable_int(host);
		host->completion = NULL;
	} else {
		ret = hisi_sfc_v3xx_wait_cmd_idle(host);
	}
	if (hisi_sfc_v3xx_handle_completion(host) || ret)
		return -EIO;

	if (op->data.dir == SPI_MEM_DATA_IN)
		hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, op->data.nbytes);

	return 0;
}

static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
				 const struct spi_mem_op *op)
{
	struct hisi_sfc_v3xx_host *host;
	struct spi_device *spi = mem->spi;
	u8 chip_select = spi->chip_select;

	host = spi_controller_get_devdata(spi->master);

	return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
}

static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
	.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
	.supports_op = hisi_sfc_v3xx_supports_op,
	.exec_op = hisi_sfc_v3xx_exec_op,
};

static irqreturn_t hisi_sfc_v3xx_isr(int irq, void *data)
{
	struct hisi_sfc_v3xx_host *host = data;

	hisi_sfc_v3xx_disable_int(host);

	complete(host->completion);

	return IRQ_HANDLED;
}

static int hisi_sfc_v3xx_buswidth_override_bits;

/*
 * ACPI FW does not allow us to currently set the device buswidth, so quirk it
 * depending on the board.
 */
static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
{
	hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;

	return 0;
}

static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[]  = {
	{
	.callback = hisi_sfc_v3xx_dmi_quirk,
	.matches = {
		DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
		DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
	},
	},
	{
	.callback = hisi_sfc_v3xx_dmi_quirk,
	.matches = {
		DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
		DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
	},
	},
	{
	.callback = hisi_sfc_v3xx_dmi_quirk,
	.matches = {
		DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
		DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
	},
	},
	{}
};

static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct hisi_sfc_v3xx_host *host;
	struct spi_controller *ctlr;
	u32 version, glb_config;
	int ret;

	ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
	if (!ctlr)
		return -ENOMEM;

	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
			  SPI_TX_DUAL | SPI_TX_QUAD;

	ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;

	host = spi_controller_get_devdata(ctlr);
	host->dev = dev;

	platform_set_drvdata(pdev, host);

	host->regbase = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(host->regbase)) {
		ret = PTR_ERR(host->regbase);
		goto err_put_master;
	}

	host->irq = platform_get_irq_optional(pdev, 0);
	if (host->irq == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		goto err_put_master;
	}

	hisi_sfc_v3xx_disable_int(host);

	if (host->irq > 0) {
		ret = devm_request_irq(dev, host->irq, hisi_sfc_v3xx_isr, 0,
				       "hisi-sfc-v3xx", host);

		if (ret) {
			dev_err(dev, "failed to request irq%d, ret = %d\n", host->irq, ret);
			host->irq = 0;
		}
	} else {
		host->irq = 0;
	}

	ctlr->bus_num = -1;
	ctlr->num_chipselect = 1;
	ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;

	/*
	 * The address mode of the controller is either 3 or 4,
	 * which is indicated by the address mode bit in
	 * the global config register. The register is read only
	 * for the OS driver.
	 */
	glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
	if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
		host->address_mode = 4;
	else
		host->address_mode = 3;

	version = readl(host->regbase + HISI_SFC_V3XX_VERSION);

	if (version >= 0x351)
		host->max_cmd_dword = 64;
	else
		host->max_cmd_dword = 16;

	ret = devm_spi_register_controller(dev, ctlr);
	if (ret)
		goto err_put_master;

	dev_info(&pdev->dev, "hw version 0x%x, %s mode.\n",
		 version, host->irq ? "irq" : "polling");

	return 0;

err_put_master:
	spi_master_put(ctlr);
	return ret;
}

#if IS_ENABLED(CONFIG_ACPI)
static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
	{"HISI0341", 0},
	{}
};
MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
#endif

static struct platform_driver hisi_sfc_v3xx_spi_driver = {
	.driver = {
		.name	= "hisi-sfc-v3xx",
		.acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
	},
	.probe	= hisi_sfc_v3xx_probe,
};

static int __init hisi_sfc_v3xx_spi_init(void)
{
	dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);

	return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
}

static void __exit hisi_sfc_v3xx_spi_exit(void)
{
	platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
}

module_init(hisi_sfc_v3xx_spi_init);
module_exit(hisi_sfc_v3xx_spi_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");
Commit	Line	Data
a2ca53b5 JG	1	// SPDX-License-Identifier: GPL-2.0-only
	2	//
	3	// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
	4	//
	5	// Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
	6	// Author: John Garry <john.garry@huawei.com>
	7
	8	#include <linux/acpi.h>
	9	#include <linux/bitops.h>
b1dd5651	10	#include <linux/completion.h>
34e608b0	11	#include <linux/dmi.h>
b1dd5651	12	#include <linux/interrupt.h>
a2ca53b5 JG	13	#include <linux/iopoll.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/slab.h>
	17	#include <linux/spi/spi.h>
	18	#include <linux/spi/spi-mem.h>
	19
	20	#define HISI_SFC_V3XX_VERSION (0x1f8)
	21
6d2386e3 YY	22	#define HISI_SFC_V3XX_GLB_CFG (0x100)
6d2386e3 YY	23	#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
b1dd5651 YY	24	#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
	25	#define HISI_SFC_V3XX_INT_STAT (0x124)
	26	#define HISI_SFC_V3XX_INT_MASK (0x128)
59fc9ad5	27	#define HISI_SFC_V3XX_INT_CLR (0x12c)
a2ca53b5 JG	28	#define HISI_SFC_V3XX_CMD_CFG (0x300)
	29	#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
	30	#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
	31	#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
	32	#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
	33	#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
	34	#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
	35	#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
	36	#define HISI_SFC_V3XX_CMD_INS (0x308)
	37	#define HISI_SFC_V3XX_CMD_ADDR (0x30c)
	38	#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
	39
aac6edff YY	40	/* Common definition of interrupt bit masks */
aac6edff YY	41	#define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */
b1dd5651	42	#define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */
aac6edff YY	43	#define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */
	44	#define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/
	45	* protected address
	46	*/
	47
2c8af6a5 YY	48	/* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */
	49	#define HISI_SFC_V3XX_STD (0 << 17)
	50	#define HISI_SFC_V3XX_DIDO (1 << 17)
	51	#define HISI_SFC_V3XX_DIO (2 << 17)
	52	#define HISI_SFC_V3XX_FULL_DIO (3 << 17)
	53	#define HISI_SFC_V3XX_QIQO (5 << 17)
	54	#define HISI_SFC_V3XX_QIO (6 << 17)
	55	#define HISI_SFC_V3XX_FULL_QIO (7 << 17)
	56
	57	/*
	58	* The IO modes lookup table. hisi_sfc_v3xx_io_modes[(z - 1) / 2][y / 2][x / 2]
	59	* stands for x-y-z mode, as described in SFDP terminology. -EIO indicates
	60	* an invalid mode.
	61	*/
	62	static const int hisi_sfc_v3xx_io_modes[2][3][3] = {
	63	{
	64	{ HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO },
	65	{ HISI_SFC_V3XX_DIO, HISI_SFC_V3XX_FULL_DIO, -EIO },
	66	{ -EIO, -EIO, -EIO },
	67	},
	68	{
	69	{ HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO },
	70	{ -EIO, -EIO, -EIO },
	71	{ HISI_SFC_V3XX_QIO, -EIO, HISI_SFC_V3XX_FULL_QIO },
	72	},
	73	};
	74
a2ca53b5 JG	75	struct hisi_sfc_v3xx_host {
	76	struct device *dev;
	77	void __iomem *regbase;
	78	int max_cmd_dword;
b1dd5651	79	struct completion *completion;
6d2386e3	80	u8 address_mode;
b1dd5651	81	int irq;
a2ca53b5 JG	82	};
a2ca53b5 JG	83
b1dd5651 YY	84	static void hisi_sfc_v3xx_disable_int(struct hisi_sfc_v3xx_host *host)
	85	{
	86	writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
	87	}
	88
	89	static void hisi_sfc_v3xx_enable_int(struct hisi_sfc_v3xx_host *host)
	90	{
	91	writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
	92	}
	93
	94	static void hisi_sfc_v3xx_clear_int(struct hisi_sfc_v3xx_host *host)
	95	{
	96	writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
	97	}
	98
	99	/*
	100	* The interrupt status register indicates whether an error occurs
	101	* after per operation. Check it, and clear the interrupts for
	102	* next time judgement.
	103	*/
	104	static int hisi_sfc_v3xx_handle_completion(struct hisi_sfc_v3xx_host *host)
	105	{
	106	u32 reg;
	107
	108	reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT);
	109	hisi_sfc_v3xx_clear_int(host);
	110
	111	if (reg & HISI_SFC_V3XX_INT_MASK_IACCES) {
	112	dev_err(host->dev, "fail to access protected address\n");
	113	return -EIO;
	114	}
	115
	116	if (reg & HISI_SFC_V3XX_INT_MASK_PP_ERR) {
	117	dev_err(host->dev, "page program operation failed\n");
	118	return -EIO;
	119	}
	120
	121	/*
	122	* The other bits of the interrupt registers is not currently
	123	* used and probably not be triggered in this driver. When it
	124	* happens, we regard it as an unsupported error here.
	125	*/
	126	if (!(reg & HISI_SFC_V3XX_INT_MASK_CPLT)) {
0e968365	127	dev_err(host->dev, "unsupported error occurred, status=0x%x\n", reg);
b1dd5651 YY	128	return -EIO;
	129	}
	130
	131	return 0;
	132	}
	133
a2ca53b5 JG	134	#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
	135	#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
	136
	137	static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
	138	{
	139	u32 reg;
	140
	141	return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
	142	!(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
	143	HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
	144	HISI_SFC_V3XX_WAIT_TIMEOUT_US);
	145	}
	146
	147	static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
	148	struct spi_mem_op *op)
	149	{
	150	struct spi_device *spi = mem->spi;
	151	struct hisi_sfc_v3xx_host *host;
	152	uintptr_t addr = (uintptr_t)op->data.buf.in;
	153	int max_byte_count;
	154
	155	host = spi_controller_get_devdata(spi->master);
	156
	157	max_byte_count = host->max_cmd_dword * 4;
	158
	159	if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
	160	op->data.nbytes = 4 - (addr % 4);
	161	else if (op->data.nbytes > max_byte_count)
	162	op->data.nbytes = max_byte_count;
	163
	164	return 0;
	165	}
	166
2c8af6a5 YY	167	/*
	168	* The controller only supports Standard SPI mode, Duall mode and
	169	* Quad mode. Double sanitize the ops here to avoid OOB access.
	170	*/
	171	static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
	172	const struct spi_mem_op *op)
	173	{
6d2386e3 YY	174	struct spi_device *spi = mem->spi;
	175	struct hisi_sfc_v3xx_host *host;
	176
	177	host = spi_controller_get_devdata(spi->master);
	178
2c8af6a5 YY	179	if (op->data.buswidth > 4 \|\| op->dummy.buswidth > 4 \|\|
	180	op->addr.buswidth > 4 \|\| op->cmd.buswidth > 4)
	181	return false;
	182
6d2386e3 YY	183	if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
	184	return false;
	185
2c8af6a5 YY	186	return spi_mem_default_supports_op(mem, op);
	187	}
	188
a2ca53b5 JG	189	/*
	190	* memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
	191	* DATABUF registers -so use __io{read,write}32_copy when possible. For
	192	* trailing bytes, copy them byte-by-byte from the DATABUF register, as we
	193	* can't clobber outside the source/dest buffer.
	194	*
	195	* For efficient data read/write, we try to put any start 32b unaligned data
	196	* into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
	197	*/
	198	static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
	199	u8 *to, unsigned int len)
	200	{
	201	void __iomem *from;
	202	int i;
	203
	204	from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
	205
	206	if (IS_ALIGNED((uintptr_t)to, 4)) {
	207	int words = len / 4;
	208
	209	__ioread32_copy(to, from, words);
	210
	211	len -= words * 4;
	212	if (len) {
	213	u32 val;
	214
	215	to += words * 4;
	216	from += words * 4;
	217
	218	val = __raw_readl(from);
	219
	220	for (i = 0; i < len; i++, val >>= 8, to++)
	221	*to = (u8)val;
	222	}
	223	} else {
	224	for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
	225	u32 val = __raw_readl(from);
	226	int j;
	227
	228	for (j = 0; j < 4 && (j + (i * 4) < len);
	229	to++, val >>= 8, j++)
	230	*to = (u8)val;
	231	}
	232	}
	233	}
	234
	235	static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
	236	const u8 *from, unsigned int len)
	237	{
	238	void __iomem *to;
	239	int i;
	240
	241	to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
	242
	243	if (IS_ALIGNED((uintptr_t)from, 4)) {
	244	int words = len / 4;
	245
	246	__iowrite32_copy(to, from, words);
	247
	248	len -= words * 4;
	249	if (len) {
	250	u32 val = 0;
	251
	252	to += words * 4;
253	from += words * 4;
254
255	for (i = 0; i < len; i++, from++)
256	val \|= from << i 8;
257	__raw_writel(val, to);
258	}
259
260	} else {
261	for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
262	u32 val = 0;
263	int j;
264
265	for (j = 0; j < 4 && (j + (i * 4) < len);
266	from++, j++)
267	val \|= from << j 8;
268	__raw_writel(val, to);
269	}
270	}
271	}
272
f6d27377 YY	273	static int hisi_sfc_v3xx_start_bus(struct hisi_sfc_v3xx_host *host,
	274	const struct spi_mem_op *op,
	275	u8 chip_select)
a2ca53b5	276	{
f6d27377 YY	277	int len = op->data.nbytes, buswidth_mode;
f6d27377 YY	278	u32 config = 0;
a2ca53b5 JG	279
	280	if (op->addr.nbytes)
	281	config \|= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
	282
2c8af6a5 YY	283	if (op->data.buswidth == 0 \|\| op->data.buswidth == 1) {
	284	buswidth_mode = HISI_SFC_V3XX_STD;
	285	} else {
	286	int data_idx, addr_idx, cmd_idx;
	287
	288	data_idx = (op->data.buswidth - 1) / 2;
	289	addr_idx = op->addr.buswidth / 2;
	290	cmd_idx = op->cmd.buswidth / 2;
	291	buswidth_mode = hisi_sfc_v3xx_io_modes[data_idx][addr_idx][cmd_idx];
8fe21d6b	292	}
2c8af6a5 YY	293	if (buswidth_mode < 0)
	294	return buswidth_mode;
	295	config \|= buswidth_mode;
8fe21d6b	296
a2ca53b5 JG	297	if (op->data.dir != SPI_MEM_NO_DATA) {
	298	config \|= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
	299	config \|= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
	300	}
	301
f6d27377	302	if (op->data.dir == SPI_MEM_DATA_IN)
a2ca53b5 JG	303	config \|= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
	304
	305	config \|= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF \|
	306	chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF \|
	307	HISI_SFC_V3XX_CMD_CFG_START_MSK;
	308
	309	writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
	310	writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
	311
	312	writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
	313
f6d27377 YY	314	return 0;
	315	}
	316
	317	static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
	318	const struct spi_mem_op *op,
	319	u8 chip_select)
	320	{
b1dd5651	321	DECLARE_COMPLETION_ONSTACK(done);
f6d27377 YY	322	int ret;
f6d27377 YY	323
b1dd5651 YY	324	if (host->irq) {
	325	host->completion = &done;
	326	hisi_sfc_v3xx_enable_int(host);
	327	}
	328
f6d27377 YY	329	if (op->data.dir == SPI_MEM_DATA_OUT)
	330	hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, op->data.nbytes);
	331
	332	ret = hisi_sfc_v3xx_start_bus(host, op, chip_select);
	333	if (ret)
	334	return ret;
	335
b1dd5651 YY	336	if (host->irq) {
	337	ret = wait_for_completion_timeout(host->completion,
	338	usecs_to_jiffies(HISI_SFC_V3XX_WAIT_TIMEOUT_US));
	339	if (!ret)
	340	ret = -ETIMEDOUT;
	341	else
	342	ret = 0;
59fc9ad5	343
b1dd5651 YY	344	hisi_sfc_v3xx_disable_int(host);
	345	host->completion = NULL;
	346	} else {
	347	ret = hisi_sfc_v3xx_wait_cmd_idle(host);
59fc9ad5	348	}
b1dd5651	349	if (hisi_sfc_v3xx_handle_completion(host) \|\| ret)
59fc9ad5	350	return -EIO;
59fc9ad5	351
a2ca53b5	352	if (op->data.dir == SPI_MEM_DATA_IN)
f6d27377	353	hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, op->data.nbytes);
a2ca53b5 JG	354
	355	return 0;
	356	}
	357
	358	static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
	359	const struct spi_mem_op *op)
	360	{
	361	struct hisi_sfc_v3xx_host *host;
	362	struct spi_device *spi = mem->spi;
	363	u8 chip_select = spi->chip_select;
	364
	365	host = spi_controller_get_devdata(spi->master);
	366
	367	return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
	368	}
	369
	370	static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
	371	.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
2c8af6a5	372	.supports_op = hisi_sfc_v3xx_supports_op,
a2ca53b5 JG	373	.exec_op = hisi_sfc_v3xx_exec_op,
	374	};
	375
b1dd5651 YY	376	static irqreturn_t hisi_sfc_v3xx_isr(int irq, void *data)
	377	{
	378	struct hisi_sfc_v3xx_host *host = data;
	379
	380	hisi_sfc_v3xx_disable_int(host);
	381
	382	complete(host->completion);
	383
	384	return IRQ_HANDLED;
	385	}
	386
34e608b0 JG	387	static int hisi_sfc_v3xx_buswidth_override_bits;
	388
	389	/*
	390	* ACPI FW does not allow us to currently set the device buswidth, so quirk it
	391	* depending on the board.
	392	*/
	393	static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
	394	{
	395	hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD \| SPI_TX_QUAD;
	396
	397	return 0;
	398	}
	399
	400	static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
	401	{
	402	.callback = hisi_sfc_v3xx_dmi_quirk,
	403	.matches = {
	404	DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
	405	DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
	406	},
	407	},
	408	{
	409	.callback = hisi_sfc_v3xx_dmi_quirk,
	410	.matches = {
	411	DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
	412	DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
	413	},
	414	},
	415	{
	416	.callback = hisi_sfc_v3xx_dmi_quirk,
	417	.matches = {
	418	DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
	419	DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
	420	},
	421	},
	422	{}
	423	};
	424
a2ca53b5 JG	425	static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
	426	{
	427	struct device *dev = &pdev->dev;
	428	struct hisi_sfc_v3xx_host *host;
	429	struct spi_controller *ctlr;
6d2386e3	430	u32 version, glb_config;
a2ca53b5 JG	431	int ret;
	432
	433	ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
	434	if (!ctlr)
	435	return -ENOMEM;
	436
	437	ctlr->mode_bits = SPI_RX_DUAL \| SPI_RX_QUAD \|
	438	SPI_TX_DUAL \| SPI_TX_QUAD;
	439
34e608b0 JG	440	ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
34e608b0 JG	441
a2ca53b5 JG	442	host = spi_controller_get_devdata(ctlr);
	443	host->dev = dev;
	444
	445	platform_set_drvdata(pdev, host);
	446
	447	host->regbase = devm_platform_ioremap_resource(pdev, 0);
	448	if (IS_ERR(host->regbase)) {
	449	ret = PTR_ERR(host->regbase);
	450	goto err_put_master;
	451	}
	452
b1dd5651 YY	453	host->irq = platform_get_irq_optional(pdev, 0);
	454	if (host->irq == -EPROBE_DEFER) {
	455	ret = -EPROBE_DEFER;
	456	goto err_put_master;
	457	}
	458
	459	hisi_sfc_v3xx_disable_int(host);
	460
	461	if (host->irq > 0) {
	462	ret = devm_request_irq(dev, host->irq, hisi_sfc_v3xx_isr, 0,
	463	"hisi-sfc-v3xx", host);
	464
	465	if (ret) {
	466	dev_err(dev, "failed to request irq%d, ret = %d\n", host->irq, ret);
	467	host->irq = 0;
	468	}
	469	} else {
	470	host->irq = 0;
	471	}
	472
a2ca53b5 JG	473	ctlr->bus_num = -1;
	474	ctlr->num_chipselect = 1;
	475	ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
	476
6d2386e3 YY	477	/*
	478	* The address mode of the controller is either 3 or 4,
	479	* which is indicated by the address mode bit in
	480	* the global config register. The register is read only
	481	* for the OS driver.
	482	*/
	483	glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
	484	if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
	485	host->address_mode = 4;
	486	else
	487	host->address_mode = 3;
	488
a2ca53b5 JG	489	version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
a2ca53b5 JG	490
566c6120	491	if (version >= 0x351)
a2ca53b5	492	host->max_cmd_dword = 64;
566c6120	493	else
a2ca53b5	494	host->max_cmd_dword = 16;
a2ca53b5 JG	495
	496	ret = devm_spi_register_controller(dev, ctlr);
	497	if (ret)
	498	goto err_put_master;
	499
b1dd5651 YY	500	dev_info(&pdev->dev, "hw version 0x%x, %s mode.\n",
b1dd5651 YY	501	version, host->irq ? "irq" : "polling");
a2ca53b5 JG	502
	503	return 0;
	504
	505	err_put_master:
	506	spi_master_put(ctlr);
	507	return ret;
	508	}
	509
	510	#if IS_ENABLED(CONFIG_ACPI)
	511	static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
	512	{"HISI0341", 0},
	513	{}
	514	};
	515	MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
	516	#endif
	517
	518	static struct platform_driver hisi_sfc_v3xx_spi_driver = {
	519	.driver = {
	520	.name = "hisi-sfc-v3xx",
	521	.acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
	522	},
	523	.probe = hisi_sfc_v3xx_probe,
	524	};
	525
34e608b0 JG	526	static int __init hisi_sfc_v3xx_spi_init(void)
	527	{
	528	dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
	529
	530	return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
	531	}
	532
	533	static void __exit hisi_sfc_v3xx_spi_exit(void)
	534	{
	535	platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
	536	}
	537
	538	module_init(hisi_sfc_v3xx_spi_init);
	539	module_exit(hisi_sfc_v3xx_spi_exit);
a2ca53b5 JG	540
	541	MODULE_LICENSE("GPL");
	542	MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
	543	MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");