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561de45f GM |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. | |
3 | ||
4 | #include <linux/clk.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/io.h> | |
7 | #include <linux/log2.h> | |
8 | #include <linux/module.h> | |
561de45f | 9 | #include <linux/platform_device.h> |
1a9e489e | 10 | #include <linux/pm_opp.h> |
561de45f GM |
11 | #include <linux/pm_runtime.h> |
12 | #include <linux/qcom-geni-se.h> | |
13 | #include <linux/spi/spi.h> | |
14 | #include <linux/spinlock.h> | |
15 | ||
16 | /* SPI SE specific registers and respective register fields */ | |
17 | #define SE_SPI_CPHA 0x224 | |
18 | #define CPHA BIT(0) | |
19 | ||
20 | #define SE_SPI_LOOPBACK 0x22c | |
21 | #define LOOPBACK_ENABLE 0x1 | |
22 | #define NORMAL_MODE 0x0 | |
23 | #define LOOPBACK_MSK GENMASK(1, 0) | |
24 | ||
25 | #define SE_SPI_CPOL 0x230 | |
26 | #define CPOL BIT(2) | |
27 | ||
28 | #define SE_SPI_DEMUX_OUTPUT_INV 0x24c | |
29 | #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) | |
30 | ||
31 | #define SE_SPI_DEMUX_SEL 0x250 | |
32 | #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) | |
33 | ||
34 | #define SE_SPI_TRANS_CFG 0x25c | |
35 | #define CS_TOGGLE BIT(0) | |
36 | ||
37 | #define SE_SPI_WORD_LEN 0x268 | |
38 | #define WORD_LEN_MSK GENMASK(9, 0) | |
39 | #define MIN_WORD_LEN 4 | |
40 | ||
41 | #define SE_SPI_TX_TRANS_LEN 0x26c | |
42 | #define SE_SPI_RX_TRANS_LEN 0x270 | |
43 | #define TRANS_LEN_MSK GENMASK(23, 0) | |
44 | ||
45 | #define SE_SPI_PRE_POST_CMD_DLY 0x274 | |
46 | ||
47 | #define SE_SPI_DELAY_COUNTERS 0x278 | |
48 | #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) | |
49 | #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) | |
50 | #define SPI_CS_CLK_DELAY_SHFT 10 | |
51 | ||
52 | /* M_CMD OP codes for SPI */ | |
53 | #define SPI_TX_ONLY 1 | |
54 | #define SPI_RX_ONLY 2 | |
561de45f GM |
55 | #define SPI_TX_RX 7 |
56 | #define SPI_CS_ASSERT 8 | |
57 | #define SPI_CS_DEASSERT 9 | |
58 | #define SPI_SCK_ONLY 10 | |
59 | /* M_CMD params for SPI */ | |
60 | #define SPI_PRE_CMD_DELAY BIT(0) | |
61 | #define TIMESTAMP_BEFORE BIT(1) | |
62 | #define FRAGMENTATION BIT(2) | |
63 | #define TIMESTAMP_AFTER BIT(3) | |
64 | #define POST_CMD_DELAY BIT(4) | |
65 | ||
561de45f GM |
66 | struct spi_geni_master { |
67 | struct geni_se se; | |
68 | struct device *dev; | |
69 | u32 tx_fifo_depth; | |
70 | u32 fifo_width_bits; | |
71 | u32 tx_wm; | |
da48dc8c | 72 | u32 last_mode; |
561de45f | 73 | unsigned long cur_speed_hz; |
5f219524 | 74 | unsigned long cur_sclk_hz; |
561de45f GM |
75 | unsigned int cur_bits_per_word; |
76 | unsigned int tx_rem_bytes; | |
77 | unsigned int rx_rem_bytes; | |
78 | const struct spi_transfer *cur_xfer; | |
7ba9bdcb DA |
79 | struct completion cs_done; |
80 | struct completion cancel_done; | |
81 | struct completion abort_done; | |
561de45f GM |
82 | unsigned int oversampling; |
83 | spinlock_t lock; | |
561de45f | 84 | int irq; |
638d8488 | 85 | bool cs_flag; |
690d8b91 | 86 | bool abort_failed; |
561de45f GM |
87 | }; |
88 | ||
561de45f GM |
89 | static int get_spi_clk_cfg(unsigned int speed_hz, |
90 | struct spi_geni_master *mas, | |
91 | unsigned int *clk_idx, | |
92 | unsigned int *clk_div) | |
93 | { | |
94 | unsigned long sclk_freq; | |
95 | unsigned int actual_hz; | |
561de45f GM |
96 | int ret; |
97 | ||
98 | ret = geni_se_clk_freq_match(&mas->se, | |
99 | speed_hz * mas->oversampling, | |
100 | clk_idx, &sclk_freq, false); | |
101 | if (ret) { | |
102 | dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", | |
103 | ret, speed_hz); | |
104 | return ret; | |
105 | } | |
106 | ||
107 | *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); | |
108 | actual_hz = sclk_freq / (mas->oversampling * *clk_div); | |
109 | ||
110 | dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, | |
111 | actual_hz, sclk_freq, *clk_idx, *clk_div); | |
1a9e489e | 112 | ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); |
561de45f | 113 | if (ret) |
1a9e489e | 114 | dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); |
5f219524 DA |
115 | else |
116 | mas->cur_sclk_hz = sclk_freq; | |
117 | ||
561de45f GM |
118 | return ret; |
119 | } | |
120 | ||
de43affe SB |
121 | static void handle_fifo_timeout(struct spi_master *spi, |
122 | struct spi_message *msg) | |
123 | { | |
124 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
539afdf9 | 125 | unsigned long time_left; |
de43affe SB |
126 | struct geni_se *se = &mas->se; |
127 | ||
539afdf9 | 128 | spin_lock_irq(&mas->lock); |
7ba9bdcb | 129 | reinit_completion(&mas->cancel_done); |
de43affe | 130 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); |
7ba9bdcb | 131 | mas->cur_xfer = NULL; |
7ba9bdcb | 132 | geni_se_cancel_m_cmd(se); |
539afdf9 | 133 | spin_unlock_irq(&mas->lock); |
7ba9bdcb DA |
134 | |
135 | time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); | |
de43affe SB |
136 | if (time_left) |
137 | return; | |
138 | ||
539afdf9 | 139 | spin_lock_irq(&mas->lock); |
7ba9bdcb | 140 | reinit_completion(&mas->abort_done); |
de43affe | 141 | geni_se_abort_m_cmd(se); |
539afdf9 | 142 | spin_unlock_irq(&mas->lock); |
7ba9bdcb DA |
143 | |
144 | time_left = wait_for_completion_timeout(&mas->abort_done, HZ); | |
690d8b91 | 145 | if (!time_left) { |
de43affe | 146 | dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); |
690d8b91 DA |
147 | |
148 | /* | |
149 | * No need for a lock since SPI core has a lock and we never | |
150 | * access this from an interrupt. | |
151 | */ | |
152 | mas->abort_failed = true; | |
153 | } | |
154 | } | |
155 | ||
156 | static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) | |
157 | { | |
158 | struct geni_se *se = &mas->se; | |
159 | u32 m_irq, m_irq_en; | |
160 | ||
161 | if (!mas->abort_failed) | |
162 | return false; | |
163 | ||
164 | /* | |
165 | * The only known case where a transfer times out and then a cancel | |
166 | * times out then an abort times out is if something is blocking our | |
167 | * interrupt handler from running. Avoid starting any new transfers | |
168 | * until that sorts itself out. | |
169 | */ | |
170 | spin_lock_irq(&mas->lock); | |
171 | m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); | |
172 | m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); | |
173 | spin_unlock_irq(&mas->lock); | |
174 | ||
175 | if (m_irq & m_irq_en) { | |
176 | dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", | |
177 | m_irq & m_irq_en); | |
178 | return true; | |
179 | } | |
180 | ||
181 | /* | |
182 | * If we're here the problem resolved itself so no need to check more | |
183 | * on future transfers. | |
184 | */ | |
185 | mas->abort_failed = false; | |
186 | ||
187 | return false; | |
de43affe SB |
188 | } |
189 | ||
561de45f GM |
190 | static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) |
191 | { | |
192 | struct spi_geni_master *mas = spi_master_get_devdata(slv->master); | |
193 | struct spi_master *spi = dev_get_drvdata(mas->dev); | |
194 | struct geni_se *se = &mas->se; | |
0dccff3c | 195 | unsigned long time_left; |
561de45f | 196 | |
561de45f GM |
197 | if (!(slv->mode & SPI_CS_HIGH)) |
198 | set_flag = !set_flag; | |
199 | ||
638d8488 DA |
200 | if (set_flag == mas->cs_flag) |
201 | return; | |
202 | ||
690d8b91 DA |
203 | pm_runtime_get_sync(mas->dev); |
204 | ||
205 | if (spi_geni_is_abort_still_pending(mas)) { | |
206 | dev_err(mas->dev, "Can't set chip select\n"); | |
207 | goto exit; | |
208 | } | |
209 | ||
2ee471a1 | 210 | spin_lock_irq(&mas->lock); |
3d7d916f DA |
211 | if (mas->cur_xfer) { |
212 | dev_err(mas->dev, "Can't set CS when prev xfer running\n"); | |
213 | spin_unlock_irq(&mas->lock); | |
214 | goto exit; | |
215 | } | |
216 | ||
217 | mas->cs_flag = set_flag; | |
7ba9bdcb | 218 | reinit_completion(&mas->cs_done); |
561de45f GM |
219 | if (set_flag) |
220 | geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); | |
221 | else | |
222 | geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); | |
2ee471a1 | 223 | spin_unlock_irq(&mas->lock); |
561de45f | 224 | |
7ba9bdcb | 225 | time_left = wait_for_completion_timeout(&mas->cs_done, HZ); |
17fa81aa DA |
226 | if (!time_left) { |
227 | dev_warn(mas->dev, "Timeout setting chip select\n"); | |
561de45f | 228 | handle_fifo_timeout(spi, NULL); |
17fa81aa | 229 | } |
561de45f | 230 | |
690d8b91 | 231 | exit: |
561de45f GM |
232 | pm_runtime_put(mas->dev); |
233 | } | |
234 | ||
235 | static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, | |
236 | unsigned int bits_per_word) | |
237 | { | |
238 | unsigned int pack_words; | |
239 | bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; | |
240 | struct geni_se *se = &mas->se; | |
241 | u32 word_len; | |
242 | ||
561de45f GM |
243 | /* |
244 | * If bits_per_word isn't a byte aligned value, set the packing to be | |
245 | * 1 SPI word per FIFO word. | |
246 | */ | |
247 | if (!(mas->fifo_width_bits % bits_per_word)) | |
248 | pack_words = mas->fifo_width_bits / bits_per_word; | |
249 | else | |
250 | pack_words = 1; | |
561de45f GM |
251 | geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, |
252 | true, true); | |
da48dc8c | 253 | word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; |
561de45f GM |
254 | writel(word_len, se->base + SE_SPI_WORD_LEN); |
255 | } | |
256 | ||
0e3b8a81 AA |
257 | static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, |
258 | unsigned long clk_hz) | |
e68b6624 DA |
259 | { |
260 | u32 clk_sel, m_clk_cfg, idx, div; | |
261 | struct geni_se *se = &mas->se; | |
262 | int ret; | |
263 | ||
68890e20 DA |
264 | if (clk_hz == mas->cur_speed_hz) |
265 | return 0; | |
266 | ||
e68b6624 DA |
267 | ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); |
268 | if (ret) { | |
269 | dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); | |
270 | return ret; | |
271 | } | |
272 | ||
273 | /* | |
274 | * SPI core clock gets configured with the requested frequency | |
275 | * or the frequency closer to the requested frequency. | |
276 | * For that reason requested frequency is stored in the | |
277 | * cur_speed_hz and referred in the consecutive transfer instead | |
278 | * of calling clk_get_rate() API. | |
279 | */ | |
280 | mas->cur_speed_hz = clk_hz; | |
281 | ||
282 | clk_sel = idx & CLK_SEL_MSK; | |
283 | m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; | |
284 | writel(clk_sel, se->base + SE_GENI_CLK_SEL); | |
285 | writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); | |
286 | ||
0e3b8a81 AA |
287 | /* Set BW quota for CPU as driver supports FIFO mode only. */ |
288 | se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); | |
289 | ret = geni_icc_set_bw(se); | |
290 | if (ret) | |
291 | return ret; | |
292 | ||
e68b6624 DA |
293 | return 0; |
294 | } | |
295 | ||
561de45f GM |
296 | static int setup_fifo_params(struct spi_device *spi_slv, |
297 | struct spi_master *spi) | |
298 | { | |
299 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
300 | struct geni_se *se = &mas->se; | |
da48dc8c | 301 | u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; |
e68b6624 | 302 | u32 demux_sel; |
561de45f | 303 | |
da48dc8c DA |
304 | if (mas->last_mode != spi_slv->mode) { |
305 | if (spi_slv->mode & SPI_LOOP) | |
306 | loopback_cfg = LOOPBACK_ENABLE; | |
561de45f | 307 | |
da48dc8c DA |
308 | if (spi_slv->mode & SPI_CPOL) |
309 | cpol = CPOL; | |
561de45f | 310 | |
da48dc8c DA |
311 | if (spi_slv->mode & SPI_CPHA) |
312 | cpha = CPHA; | |
561de45f | 313 | |
da48dc8c DA |
314 | if (spi_slv->mode & SPI_CS_HIGH) |
315 | demux_output_inv = BIT(spi_slv->chip_select); | |
561de45f | 316 | |
da48dc8c DA |
317 | demux_sel = spi_slv->chip_select; |
318 | mas->cur_bits_per_word = spi_slv->bits_per_word; | |
561de45f | 319 | |
da48dc8c DA |
320 | spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); |
321 | writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); | |
322 | writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); | |
323 | writel(cpha, se->base + SE_SPI_CPHA); | |
324 | writel(cpol, se->base + SE_SPI_CPOL); | |
325 | writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); | |
561de45f | 326 | |
da48dc8c DA |
327 | mas->last_mode = spi_slv->mode; |
328 | } | |
e68b6624 | 329 | |
0e3b8a81 | 330 | return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); |
561de45f GM |
331 | } |
332 | ||
333 | static int spi_geni_prepare_message(struct spi_master *spi, | |
334 | struct spi_message *spi_msg) | |
335 | { | |
336 | int ret; | |
337 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
561de45f | 338 | |
690d8b91 DA |
339 | if (spi_geni_is_abort_still_pending(mas)) |
340 | return -EBUSY; | |
341 | ||
561de45f GM |
342 | ret = setup_fifo_params(spi_msg->spi, spi); |
343 | if (ret) | |
344 | dev_err(mas->dev, "Couldn't select mode %d\n", ret); | |
345 | return ret; | |
346 | } | |
347 | ||
348 | static int spi_geni_init(struct spi_geni_master *mas) | |
349 | { | |
350 | struct geni_se *se = &mas->se; | |
351 | unsigned int proto, major, minor, ver; | |
14ac4e04 | 352 | u32 spi_tx_cfg; |
561de45f GM |
353 | |
354 | pm_runtime_get_sync(mas->dev); | |
355 | ||
356 | proto = geni_se_read_proto(se); | |
357 | if (proto != GENI_SE_SPI) { | |
358 | dev_err(mas->dev, "Invalid proto %d\n", proto); | |
359 | pm_runtime_put(mas->dev); | |
360 | return -ENXIO; | |
361 | } | |
362 | mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); | |
363 | ||
364 | /* Width of Tx and Rx FIFO is same */ | |
365 | mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); | |
366 | ||
367 | /* | |
368 | * Hardware programming guide suggests to configure | |
369 | * RX FIFO RFR level to fifo_depth-2. | |
370 | */ | |
fc129a43 | 371 | geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); |
561de45f GM |
372 | /* Transmit an entire FIFO worth of data per IRQ */ |
373 | mas->tx_wm = 1; | |
374 | ver = geni_se_get_qup_hw_version(se); | |
375 | major = GENI_SE_VERSION_MAJOR(ver); | |
376 | minor = GENI_SE_VERSION_MINOR(ver); | |
377 | ||
378 | if (major == 1 && minor == 0) | |
379 | mas->oversampling = 2; | |
380 | else | |
381 | mas->oversampling = 1; | |
382 | ||
da48dc8c DA |
383 | geni_se_select_mode(se, GENI_SE_FIFO); |
384 | ||
14ac4e04 DA |
385 | /* We always control CS manually */ |
386 | spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); | |
387 | spi_tx_cfg &= ~CS_TOGGLE; | |
388 | writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); | |
389 | ||
561de45f GM |
390 | pm_runtime_put(mas->dev); |
391 | return 0; | |
392 | } | |
393 | ||
6d66507d DA |
394 | static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) |
395 | { | |
396 | /* | |
397 | * Calculate how many bytes we'll put in each FIFO word. If the | |
398 | * transfer words don't pack cleanly into a FIFO word we'll just put | |
399 | * one transfer word in each FIFO word. If they do pack we'll pack 'em. | |
400 | */ | |
401 | if (mas->fifo_width_bits % mas->cur_bits_per_word) | |
402 | return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, | |
403 | BITS_PER_BYTE)); | |
404 | ||
405 | return mas->fifo_width_bits / BITS_PER_BYTE; | |
406 | } | |
407 | ||
408 | static bool geni_spi_handle_tx(struct spi_geni_master *mas) | |
409 | { | |
410 | struct geni_se *se = &mas->se; | |
411 | unsigned int max_bytes; | |
412 | const u8 *tx_buf; | |
413 | unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); | |
414 | unsigned int i = 0; | |
415 | ||
4aa1464a DA |
416 | /* Stop the watermark IRQ if nothing to send */ |
417 | if (!mas->cur_xfer) { | |
418 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); | |
419 | return false; | |
420 | } | |
421 | ||
6d66507d DA |
422 | max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; |
423 | if (mas->tx_rem_bytes < max_bytes) | |
424 | max_bytes = mas->tx_rem_bytes; | |
425 | ||
426 | tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; | |
427 | while (i < max_bytes) { | |
428 | unsigned int j; | |
429 | unsigned int bytes_to_write; | |
430 | u32 fifo_word = 0; | |
431 | u8 *fifo_byte = (u8 *)&fifo_word; | |
432 | ||
433 | bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); | |
434 | for (j = 0; j < bytes_to_write; j++) | |
435 | fifo_byte[j] = tx_buf[i++]; | |
436 | iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); | |
437 | } | |
438 | mas->tx_rem_bytes -= max_bytes; | |
439 | if (!mas->tx_rem_bytes) { | |
440 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); | |
441 | return false; | |
442 | } | |
443 | return true; | |
444 | } | |
445 | ||
446 | static void geni_spi_handle_rx(struct spi_geni_master *mas) | |
447 | { | |
448 | struct geni_se *se = &mas->se; | |
449 | u32 rx_fifo_status; | |
450 | unsigned int rx_bytes; | |
451 | unsigned int rx_last_byte_valid; | |
452 | u8 *rx_buf; | |
453 | unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); | |
454 | unsigned int i = 0; | |
455 | ||
456 | rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); | |
457 | rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; | |
458 | if (rx_fifo_status & RX_LAST) { | |
459 | rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; | |
460 | rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; | |
461 | if (rx_last_byte_valid && rx_last_byte_valid < 4) | |
462 | rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; | |
463 | } | |
4aa1464a DA |
464 | |
465 | /* Clear out the FIFO and bail if nowhere to put it */ | |
466 | if (!mas->cur_xfer) { | |
467 | for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) | |
468 | readl(se->base + SE_GENI_RX_FIFOn); | |
469 | return; | |
470 | } | |
471 | ||
6d66507d DA |
472 | if (mas->rx_rem_bytes < rx_bytes) |
473 | rx_bytes = mas->rx_rem_bytes; | |
474 | ||
475 | rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; | |
476 | while (i < rx_bytes) { | |
477 | u32 fifo_word = 0; | |
478 | u8 *fifo_byte = (u8 *)&fifo_word; | |
479 | unsigned int bytes_to_read; | |
480 | unsigned int j; | |
481 | ||
482 | bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); | |
483 | ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); | |
484 | for (j = 0; j < bytes_to_read; j++) | |
485 | rx_buf[i++] = fifo_byte[j]; | |
486 | } | |
487 | mas->rx_rem_bytes -= rx_bytes; | |
488 | } | |
489 | ||
561de45f GM |
490 | static void setup_fifo_xfer(struct spi_transfer *xfer, |
491 | struct spi_geni_master *mas, | |
492 | u16 mode, struct spi_master *spi) | |
493 | { | |
494 | u32 m_cmd = 0; | |
14ac4e04 | 495 | u32 len; |
561de45f | 496 | struct geni_se *se = &mas->se; |
e68b6624 | 497 | int ret; |
561de45f | 498 | |
2ee471a1 DA |
499 | /* |
500 | * Ensure that our interrupt handler isn't still running from some | |
501 | * prior command before we start messing with the hardware behind | |
502 | * its back. We don't need to _keep_ the lock here since we're only | |
503 | * worried about racing with out interrupt handler. The SPI core | |
504 | * already handles making sure that we're not trying to do two | |
505 | * transfers at once or setting a chip select and doing a transfer | |
506 | * concurrently. | |
507 | * | |
508 | * NOTE: we actually _can't_ hold the lock here because possibly we | |
509 | * might call clk_set_rate() which needs to be able to sleep. | |
510 | */ | |
511 | spin_lock_irq(&mas->lock); | |
512 | spin_unlock_irq(&mas->lock); | |
513 | ||
561de45f GM |
514 | if (xfer->bits_per_word != mas->cur_bits_per_word) { |
515 | spi_setup_word_len(mas, mode, xfer->bits_per_word); | |
516 | mas->cur_bits_per_word = xfer->bits_per_word; | |
517 | } | |
518 | ||
519 | /* Speed and bits per word can be overridden per transfer */ | |
68890e20 DA |
520 | ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); |
521 | if (ret) | |
522 | return; | |
561de45f GM |
523 | |
524 | mas->tx_rem_bytes = 0; | |
525 | mas->rx_rem_bytes = 0; | |
561de45f | 526 | |
561de45f GM |
527 | if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) |
528 | len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; | |
529 | else | |
530 | len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); | |
531 | len &= TRANS_LEN_MSK; | |
532 | ||
533 | mas->cur_xfer = xfer; | |
19ea3275 SB |
534 | if (xfer->tx_buf) { |
535 | m_cmd |= SPI_TX_ONLY; | |
561de45f GM |
536 | mas->tx_rem_bytes = xfer->len; |
537 | writel(len, se->base + SE_SPI_TX_TRANS_LEN); | |
538 | } | |
539 | ||
19ea3275 SB |
540 | if (xfer->rx_buf) { |
541 | m_cmd |= SPI_RX_ONLY; | |
561de45f GM |
542 | writel(len, se->base + SE_SPI_RX_TRANS_LEN); |
543 | mas->rx_rem_bytes = xfer->len; | |
544 | } | |
2ee471a1 DA |
545 | |
546 | /* | |
547 | * Lock around right before we start the transfer since our | |
548 | * interrupt could come in at any time now. | |
549 | */ | |
550 | spin_lock_irq(&mas->lock); | |
561de45f GM |
551 | geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); |
552 | ||
553 | /* | |
554 | * TX_WATERMARK_REG should be set after SPI configuration and | |
555 | * setting up GENI SE engine, as driver starts data transfer | |
556 | * for the watermark interrupt. | |
557 | */ | |
6d66507d DA |
558 | if (m_cmd & SPI_TX_ONLY) { |
559 | if (geni_spi_handle_tx(mas)) | |
560 | writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); | |
561 | } | |
2ee471a1 | 562 | spin_unlock_irq(&mas->lock); |
561de45f GM |
563 | } |
564 | ||
561de45f GM |
565 | static int spi_geni_transfer_one(struct spi_master *spi, |
566 | struct spi_device *slv, | |
567 | struct spi_transfer *xfer) | |
568 | { | |
569 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
570 | ||
690d8b91 DA |
571 | if (spi_geni_is_abort_still_pending(mas)) |
572 | return -EBUSY; | |
573 | ||
561de45f GM |
574 | /* Terminate and return success for 0 byte length transfer */ |
575 | if (!xfer->len) | |
576 | return 0; | |
577 | ||
578 | setup_fifo_xfer(xfer, mas, slv->mode, spi); | |
579 | return 1; | |
580 | } | |
581 | ||
561de45f GM |
582 | static irqreturn_t geni_spi_isr(int irq, void *data) |
583 | { | |
584 | struct spi_master *spi = data; | |
585 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
586 | struct geni_se *se = &mas->se; | |
587 | u32 m_irq; | |
561de45f | 588 | |
2ee471a1 DA |
589 | m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); |
590 | if (!m_irq) | |
561de45f GM |
591 | return IRQ_NONE; |
592 | ||
e191a082 DA |
593 | if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | |
594 | M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | | |
595 | M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) | |
596 | dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); | |
597 | ||
539afdf9 | 598 | spin_lock(&mas->lock); |
561de45f GM |
599 | |
600 | if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) | |
601 | geni_spi_handle_rx(mas); | |
602 | ||
603 | if (m_irq & M_TX_FIFO_WATERMARK_EN) | |
604 | geni_spi_handle_tx(mas); | |
605 | ||
606 | if (m_irq & M_CMD_DONE_EN) { | |
7ba9bdcb | 607 | if (mas->cur_xfer) { |
561de45f | 608 | spi_finalize_current_transfer(spi); |
7ba9bdcb | 609 | mas->cur_xfer = NULL; |
59ab0fa0 SB |
610 | /* |
611 | * If this happens, then a CMD_DONE came before all the | |
612 | * Tx buffer bytes were sent out. This is unusual, log | |
613 | * this condition and disable the WM interrupt to | |
614 | * prevent the system from stalling due an interrupt | |
615 | * storm. | |
616 | * | |
617 | * If this happens when all Rx bytes haven't been | |
618 | * received, log the condition. The only known time | |
619 | * this can happen is if bits_per_word != 8 and some | |
620 | * registers that expect xfer lengths in num spi_words | |
621 | * weren't written correctly. | |
622 | */ | |
623 | if (mas->tx_rem_bytes) { | |
624 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); | |
625 | dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", | |
626 | mas->tx_rem_bytes, mas->cur_bits_per_word); | |
627 | } | |
628 | if (mas->rx_rem_bytes) | |
629 | dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", | |
630 | mas->rx_rem_bytes, mas->cur_bits_per_word); | |
7ba9bdcb DA |
631 | } else { |
632 | complete(&mas->cs_done); | |
561de45f | 633 | } |
561de45f GM |
634 | } |
635 | ||
7ba9bdcb DA |
636 | if (m_irq & M_CMD_CANCEL_EN) |
637 | complete(&mas->cancel_done); | |
638 | if (m_irq & M_CMD_ABORT_EN) | |
639 | complete(&mas->abort_done); | |
561de45f | 640 | |
2ee471a1 DA |
641 | /* |
642 | * It's safe or a good idea to Ack all of our our interrupts at the | |
643 | * end of the function. Specifically: | |
644 | * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and | |
645 | * clearing Acks. Clearing at the end relies on nobody else having | |
646 | * started a new transfer yet or else we could be clearing _their_ | |
647 | * done bit, but everyone grabs the spinlock before starting a new | |
648 | * transfer. | |
649 | * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear | |
650 | * to be "latched level" interrupts so it's important to clear them | |
651 | * _after_ you've handled the condition and always safe to do so | |
652 | * since they'll re-assert if they're still happening. | |
653 | */ | |
561de45f | 654 | writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); |
2ee471a1 | 655 | |
539afdf9 | 656 | spin_unlock(&mas->lock); |
2ee471a1 | 657 | |
0dccff3c | 658 | return IRQ_HANDLED; |
561de45f GM |
659 | } |
660 | ||
661 | static int spi_geni_probe(struct platform_device *pdev) | |
662 | { | |
6a34e285 | 663 | int ret, irq; |
561de45f GM |
664 | struct spi_master *spi; |
665 | struct spi_geni_master *mas; | |
6a34e285 AC |
666 | void __iomem *base; |
667 | struct clk *clk; | |
ea1e5b33 | 668 | struct device *dev = &pdev->dev; |
6a34e285 AC |
669 | |
670 | irq = platform_get_irq(pdev, 0); | |
6b8ac10e | 671 | if (irq < 0) |
6a34e285 | 672 | return irq; |
6a34e285 | 673 | |
d8e477ab | 674 | base = devm_platform_ioremap_resource(pdev, 0); |
6a34e285 AC |
675 | if (IS_ERR(base)) |
676 | return PTR_ERR(base); | |
677 | ||
ea1e5b33 SB |
678 | clk = devm_clk_get(dev, "se"); |
679 | if (IS_ERR(clk)) | |
6a34e285 | 680 | return PTR_ERR(clk); |
561de45f | 681 | |
8f96c434 | 682 | spi = devm_spi_alloc_master(dev, sizeof(*mas)); |
561de45f GM |
683 | if (!spi) |
684 | return -ENOMEM; | |
685 | ||
686 | platform_set_drvdata(pdev, spi); | |
687 | mas = spi_master_get_devdata(spi); | |
6a34e285 | 688 | mas->irq = irq; |
ea1e5b33 SB |
689 | mas->dev = dev; |
690 | mas->se.dev = dev; | |
691 | mas->se.wrapper = dev_get_drvdata(dev->parent); | |
6a34e285 AC |
692 | mas->se.base = base; |
693 | mas->se.clk = clk; | |
1a9e489e RN |
694 | mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); |
695 | if (IS_ERR(mas->se.opp_table)) | |
696 | return PTR_ERR(mas->se.opp_table); | |
697 | /* OPP table is optional */ | |
698 | ret = dev_pm_opp_of_add_table(&pdev->dev); | |
7d568edf | 699 | if (ret && ret != -ENODEV) { |
1a9e489e | 700 | dev_err(&pdev->dev, "invalid OPP table in device tree\n"); |
7d568edf | 701 | goto put_clkname; |
1a9e489e | 702 | } |
561de45f GM |
703 | |
704 | spi->bus_num = -1; | |
ea1e5b33 | 705 | spi->dev.of_node = dev->of_node; |
561de45f GM |
706 | spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; |
707 | spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
708 | spi->num_chipselect = 4; | |
709 | spi->max_speed_hz = 50000000; | |
710 | spi->prepare_message = spi_geni_prepare_message; | |
711 | spi->transfer_one = spi_geni_transfer_one; | |
712 | spi->auto_runtime_pm = true; | |
713 | spi->handle_err = handle_fifo_timeout; | |
714 | spi->set_cs = spi_geni_set_cs; | |
3b25f337 | 715 | spi->use_gpio_descriptors = true; |
561de45f | 716 | |
7ba9bdcb DA |
717 | init_completion(&mas->cs_done); |
718 | init_completion(&mas->cancel_done); | |
719 | init_completion(&mas->abort_done); | |
561de45f | 720 | spin_lock_init(&mas->lock); |
cfdab2cd DA |
721 | pm_runtime_use_autosuspend(&pdev->dev); |
722 | pm_runtime_set_autosuspend_delay(&pdev->dev, 250); | |
ea1e5b33 | 723 | pm_runtime_enable(dev); |
561de45f | 724 | |
0e3b8a81 AA |
725 | ret = geni_icc_get(&mas->se, NULL); |
726 | if (ret) | |
727 | goto spi_geni_probe_runtime_disable; | |
728 | /* Set the bus quota to a reasonable value for register access */ | |
729 | mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); | |
730 | mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; | |
731 | ||
732 | ret = geni_icc_set_bw(&mas->se); | |
733 | if (ret) | |
734 | goto spi_geni_probe_runtime_disable; | |
735 | ||
561de45f GM |
736 | ret = spi_geni_init(mas); |
737 | if (ret) | |
738 | goto spi_geni_probe_runtime_disable; | |
739 | ||
ea1e5b33 | 740 | ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); |
561de45f GM |
741 | if (ret) |
742 | goto spi_geni_probe_runtime_disable; | |
743 | ||
744 | ret = spi_register_master(spi); | |
745 | if (ret) | |
746 | goto spi_geni_probe_free_irq; | |
747 | ||
748 | return 0; | |
749 | spi_geni_probe_free_irq: | |
750 | free_irq(mas->irq, spi); | |
751 | spi_geni_probe_runtime_disable: | |
ea1e5b33 | 752 | pm_runtime_disable(dev); |
7d568edf VK |
753 | dev_pm_opp_of_remove_table(&pdev->dev); |
754 | put_clkname: | |
1a9e489e | 755 | dev_pm_opp_put_clkname(mas->se.opp_table); |
561de45f GM |
756 | return ret; |
757 | } | |
758 | ||
759 | static int spi_geni_remove(struct platform_device *pdev) | |
760 | { | |
761 | struct spi_master *spi = platform_get_drvdata(pdev); | |
762 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
763 | ||
764 | /* Unregister _before_ disabling pm_runtime() so we stop transfers */ | |
765 | spi_unregister_master(spi); | |
766 | ||
767 | free_irq(mas->irq, spi); | |
768 | pm_runtime_disable(&pdev->dev); | |
7d568edf | 769 | dev_pm_opp_of_remove_table(&pdev->dev); |
1a9e489e | 770 | dev_pm_opp_put_clkname(mas->se.opp_table); |
561de45f GM |
771 | return 0; |
772 | } | |
773 | ||
774 | static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) | |
775 | { | |
776 | struct spi_master *spi = dev_get_drvdata(dev); | |
777 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
0e3b8a81 AA |
778 | int ret; |
779 | ||
1a9e489e RN |
780 | /* Drop the performance state vote */ |
781 | dev_pm_opp_set_rate(dev, 0); | |
782 | ||
0e3b8a81 AA |
783 | ret = geni_se_resources_off(&mas->se); |
784 | if (ret) | |
785 | return ret; | |
561de45f | 786 | |
0e3b8a81 | 787 | return geni_icc_disable(&mas->se); |
561de45f GM |
788 | } |
789 | ||
790 | static int __maybe_unused spi_geni_runtime_resume(struct device *dev) | |
791 | { | |
792 | struct spi_master *spi = dev_get_drvdata(dev); | |
793 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
0e3b8a81 AA |
794 | int ret; |
795 | ||
796 | ret = geni_icc_enable(&mas->se); | |
797 | if (ret) | |
798 | return ret; | |
561de45f | 799 | |
5f219524 DA |
800 | ret = geni_se_resources_on(&mas->se); |
801 | if (ret) | |
802 | return ret; | |
803 | ||
804 | return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); | |
561de45f GM |
805 | } |
806 | ||
807 | static int __maybe_unused spi_geni_suspend(struct device *dev) | |
808 | { | |
809 | struct spi_master *spi = dev_get_drvdata(dev); | |
810 | int ret; | |
811 | ||
812 | ret = spi_master_suspend(spi); | |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | ret = pm_runtime_force_suspend(dev); | |
817 | if (ret) | |
818 | spi_master_resume(spi); | |
819 | ||
820 | return ret; | |
821 | } | |
822 | ||
823 | static int __maybe_unused spi_geni_resume(struct device *dev) | |
824 | { | |
825 | struct spi_master *spi = dev_get_drvdata(dev); | |
826 | int ret; | |
827 | ||
828 | ret = pm_runtime_force_resume(dev); | |
829 | if (ret) | |
830 | return ret; | |
831 | ||
832 | ret = spi_master_resume(spi); | |
833 | if (ret) | |
834 | pm_runtime_force_suspend(dev); | |
835 | ||
836 | return ret; | |
837 | } | |
838 | ||
839 | static const struct dev_pm_ops spi_geni_pm_ops = { | |
840 | SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, | |
841 | spi_geni_runtime_resume, NULL) | |
842 | SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) | |
843 | }; | |
844 | ||
845 | static const struct of_device_id spi_geni_dt_match[] = { | |
846 | { .compatible = "qcom,geni-spi" }, | |
847 | {} | |
848 | }; | |
849 | MODULE_DEVICE_TABLE(of, spi_geni_dt_match); | |
850 | ||
851 | static struct platform_driver spi_geni_driver = { | |
852 | .probe = spi_geni_probe, | |
853 | .remove = spi_geni_remove, | |
854 | .driver = { | |
855 | .name = "geni_spi", | |
856 | .pm = &spi_geni_pm_ops, | |
857 | .of_match_table = spi_geni_dt_match, | |
858 | }, | |
859 | }; | |
860 | module_platform_driver(spi_geni_driver); | |
861 | ||
862 | MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); | |
863 | MODULE_LICENSE("GPL v2"); |