Commit | Line | Data |
---|---|---|
561de45f GM |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. | |
3 | ||
4 | #include <linux/clk.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/io.h> | |
7 | #include <linux/log2.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/of.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/pm_runtime.h> | |
12 | #include <linux/qcom-geni-se.h> | |
13 | #include <linux/spi/spi.h> | |
14 | #include <linux/spinlock.h> | |
15 | ||
16 | /* SPI SE specific registers and respective register fields */ | |
17 | #define SE_SPI_CPHA 0x224 | |
18 | #define CPHA BIT(0) | |
19 | ||
20 | #define SE_SPI_LOOPBACK 0x22c | |
21 | #define LOOPBACK_ENABLE 0x1 | |
22 | #define NORMAL_MODE 0x0 | |
23 | #define LOOPBACK_MSK GENMASK(1, 0) | |
24 | ||
25 | #define SE_SPI_CPOL 0x230 | |
26 | #define CPOL BIT(2) | |
27 | ||
28 | #define SE_SPI_DEMUX_OUTPUT_INV 0x24c | |
29 | #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) | |
30 | ||
31 | #define SE_SPI_DEMUX_SEL 0x250 | |
32 | #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) | |
33 | ||
34 | #define SE_SPI_TRANS_CFG 0x25c | |
35 | #define CS_TOGGLE BIT(0) | |
36 | ||
37 | #define SE_SPI_WORD_LEN 0x268 | |
38 | #define WORD_LEN_MSK GENMASK(9, 0) | |
39 | #define MIN_WORD_LEN 4 | |
40 | ||
41 | #define SE_SPI_TX_TRANS_LEN 0x26c | |
42 | #define SE_SPI_RX_TRANS_LEN 0x270 | |
43 | #define TRANS_LEN_MSK GENMASK(23, 0) | |
44 | ||
45 | #define SE_SPI_PRE_POST_CMD_DLY 0x274 | |
46 | ||
47 | #define SE_SPI_DELAY_COUNTERS 0x278 | |
48 | #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) | |
49 | #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) | |
50 | #define SPI_CS_CLK_DELAY_SHFT 10 | |
51 | ||
52 | /* M_CMD OP codes for SPI */ | |
53 | #define SPI_TX_ONLY 1 | |
54 | #define SPI_RX_ONLY 2 | |
55 | #define SPI_FULL_DUPLEX 3 | |
56 | #define SPI_TX_RX 7 | |
57 | #define SPI_CS_ASSERT 8 | |
58 | #define SPI_CS_DEASSERT 9 | |
59 | #define SPI_SCK_ONLY 10 | |
60 | /* M_CMD params for SPI */ | |
61 | #define SPI_PRE_CMD_DELAY BIT(0) | |
62 | #define TIMESTAMP_BEFORE BIT(1) | |
63 | #define FRAGMENTATION BIT(2) | |
64 | #define TIMESTAMP_AFTER BIT(3) | |
65 | #define POST_CMD_DELAY BIT(4) | |
66 | ||
0dccff3c | 67 | enum spi_m_cmd_opcode { |
561de45f GM |
68 | CMD_NONE, |
69 | CMD_XFER, | |
70 | CMD_CS, | |
71 | CMD_CANCEL, | |
72 | }; | |
73 | ||
561de45f GM |
74 | struct spi_geni_master { |
75 | struct geni_se se; | |
76 | struct device *dev; | |
77 | u32 tx_fifo_depth; | |
78 | u32 fifo_width_bits; | |
79 | u32 tx_wm; | |
80 | unsigned long cur_speed_hz; | |
81 | unsigned int cur_bits_per_word; | |
82 | unsigned int tx_rem_bytes; | |
83 | unsigned int rx_rem_bytes; | |
84 | const struct spi_transfer *cur_xfer; | |
85 | struct completion xfer_done; | |
86 | unsigned int oversampling; | |
87 | spinlock_t lock; | |
0dccff3c | 88 | enum spi_m_cmd_opcode cur_mcmd; |
561de45f GM |
89 | int irq; |
90 | }; | |
91 | ||
561de45f GM |
92 | static int get_spi_clk_cfg(unsigned int speed_hz, |
93 | struct spi_geni_master *mas, | |
94 | unsigned int *clk_idx, | |
95 | unsigned int *clk_div) | |
96 | { | |
97 | unsigned long sclk_freq; | |
98 | unsigned int actual_hz; | |
99 | struct geni_se *se = &mas->se; | |
100 | int ret; | |
101 | ||
102 | ret = geni_se_clk_freq_match(&mas->se, | |
103 | speed_hz * mas->oversampling, | |
104 | clk_idx, &sclk_freq, false); | |
105 | if (ret) { | |
106 | dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", | |
107 | ret, speed_hz); | |
108 | return ret; | |
109 | } | |
110 | ||
111 | *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); | |
112 | actual_hz = sclk_freq / (mas->oversampling * *clk_div); | |
113 | ||
114 | dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, | |
115 | actual_hz, sclk_freq, *clk_idx, *clk_div); | |
116 | ret = clk_set_rate(se->clk, sclk_freq); | |
117 | if (ret) | |
118 | dev_err(mas->dev, "clk_set_rate failed %d\n", ret); | |
119 | return ret; | |
120 | } | |
121 | ||
de43affe SB |
122 | static void handle_fifo_timeout(struct spi_master *spi, |
123 | struct spi_message *msg) | |
124 | { | |
125 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
126 | unsigned long time_left, flags; | |
127 | struct geni_se *se = &mas->se; | |
128 | ||
129 | spin_lock_irqsave(&mas->lock, flags); | |
130 | reinit_completion(&mas->xfer_done); | |
131 | mas->cur_mcmd = CMD_CANCEL; | |
132 | geni_se_cancel_m_cmd(se); | |
133 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); | |
134 | spin_unlock_irqrestore(&mas->lock, flags); | |
135 | time_left = wait_for_completion_timeout(&mas->xfer_done, HZ); | |
136 | if (time_left) | |
137 | return; | |
138 | ||
139 | spin_lock_irqsave(&mas->lock, flags); | |
140 | reinit_completion(&mas->xfer_done); | |
141 | geni_se_abort_m_cmd(se); | |
142 | spin_unlock_irqrestore(&mas->lock, flags); | |
143 | time_left = wait_for_completion_timeout(&mas->xfer_done, HZ); | |
144 | if (!time_left) | |
145 | dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); | |
146 | } | |
147 | ||
561de45f GM |
148 | static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) |
149 | { | |
150 | struct spi_geni_master *mas = spi_master_get_devdata(slv->master); | |
151 | struct spi_master *spi = dev_get_drvdata(mas->dev); | |
152 | struct geni_se *se = &mas->se; | |
0dccff3c | 153 | unsigned long time_left; |
561de45f GM |
154 | |
155 | reinit_completion(&mas->xfer_done); | |
156 | pm_runtime_get_sync(mas->dev); | |
157 | if (!(slv->mode & SPI_CS_HIGH)) | |
158 | set_flag = !set_flag; | |
159 | ||
160 | mas->cur_mcmd = CMD_CS; | |
161 | if (set_flag) | |
162 | geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); | |
163 | else | |
164 | geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); | |
165 | ||
0dccff3c AC |
166 | time_left = wait_for_completion_timeout(&mas->xfer_done, HZ); |
167 | if (!time_left) | |
561de45f GM |
168 | handle_fifo_timeout(spi, NULL); |
169 | ||
170 | pm_runtime_put(mas->dev); | |
171 | } | |
172 | ||
173 | static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, | |
174 | unsigned int bits_per_word) | |
175 | { | |
176 | unsigned int pack_words; | |
177 | bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; | |
178 | struct geni_se *se = &mas->se; | |
179 | u32 word_len; | |
180 | ||
181 | word_len = readl(se->base + SE_SPI_WORD_LEN); | |
182 | ||
183 | /* | |
184 | * If bits_per_word isn't a byte aligned value, set the packing to be | |
185 | * 1 SPI word per FIFO word. | |
186 | */ | |
187 | if (!(mas->fifo_width_bits % bits_per_word)) | |
188 | pack_words = mas->fifo_width_bits / bits_per_word; | |
189 | else | |
190 | pack_words = 1; | |
191 | word_len &= ~WORD_LEN_MSK; | |
192 | word_len |= ((bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK); | |
193 | geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, | |
194 | true, true); | |
195 | writel(word_len, se->base + SE_SPI_WORD_LEN); | |
196 | } | |
197 | ||
198 | static int setup_fifo_params(struct spi_device *spi_slv, | |
199 | struct spi_master *spi) | |
200 | { | |
201 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
202 | struct geni_se *se = &mas->se; | |
203 | u32 loopback_cfg, cpol, cpha, demux_output_inv; | |
204 | u32 demux_sel, clk_sel, m_clk_cfg, idx, div; | |
205 | int ret; | |
206 | ||
207 | loopback_cfg = readl(se->base + SE_SPI_LOOPBACK); | |
208 | cpol = readl(se->base + SE_SPI_CPOL); | |
209 | cpha = readl(se->base + SE_SPI_CPHA); | |
210 | demux_output_inv = 0; | |
211 | loopback_cfg &= ~LOOPBACK_MSK; | |
212 | cpol &= ~CPOL; | |
213 | cpha &= ~CPHA; | |
214 | ||
215 | if (spi_slv->mode & SPI_LOOP) | |
216 | loopback_cfg |= LOOPBACK_ENABLE; | |
217 | ||
218 | if (spi_slv->mode & SPI_CPOL) | |
219 | cpol |= CPOL; | |
220 | ||
221 | if (spi_slv->mode & SPI_CPHA) | |
222 | cpha |= CPHA; | |
223 | ||
224 | if (spi_slv->mode & SPI_CS_HIGH) | |
225 | demux_output_inv = BIT(spi_slv->chip_select); | |
226 | ||
227 | demux_sel = spi_slv->chip_select; | |
228 | mas->cur_speed_hz = spi_slv->max_speed_hz; | |
229 | mas->cur_bits_per_word = spi_slv->bits_per_word; | |
230 | ||
231 | ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div); | |
232 | if (ret) { | |
233 | dev_err(mas->dev, "Err setting clks ret(%d) for %ld\n", | |
234 | ret, mas->cur_speed_hz); | |
235 | return ret; | |
236 | } | |
237 | ||
238 | clk_sel = idx & CLK_SEL_MSK; | |
239 | m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; | |
240 | spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); | |
241 | writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); | |
242 | writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); | |
243 | writel(cpha, se->base + SE_SPI_CPHA); | |
244 | writel(cpol, se->base + SE_SPI_CPOL); | |
245 | writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); | |
246 | writel(clk_sel, se->base + SE_GENI_CLK_SEL); | |
247 | writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static int spi_geni_prepare_message(struct spi_master *spi, | |
252 | struct spi_message *spi_msg) | |
253 | { | |
254 | int ret; | |
255 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
256 | struct geni_se *se = &mas->se; | |
257 | ||
258 | geni_se_select_mode(se, GENI_SE_FIFO); | |
561de45f GM |
259 | ret = setup_fifo_params(spi_msg->spi, spi); |
260 | if (ret) | |
261 | dev_err(mas->dev, "Couldn't select mode %d\n", ret); | |
262 | return ret; | |
263 | } | |
264 | ||
265 | static int spi_geni_init(struct spi_geni_master *mas) | |
266 | { | |
267 | struct geni_se *se = &mas->se; | |
268 | unsigned int proto, major, minor, ver; | |
269 | ||
270 | pm_runtime_get_sync(mas->dev); | |
271 | ||
272 | proto = geni_se_read_proto(se); | |
273 | if (proto != GENI_SE_SPI) { | |
274 | dev_err(mas->dev, "Invalid proto %d\n", proto); | |
275 | pm_runtime_put(mas->dev); | |
276 | return -ENXIO; | |
277 | } | |
278 | mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); | |
279 | ||
280 | /* Width of Tx and Rx FIFO is same */ | |
281 | mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); | |
282 | ||
283 | /* | |
284 | * Hardware programming guide suggests to configure | |
285 | * RX FIFO RFR level to fifo_depth-2. | |
286 | */ | |
287 | geni_se_init(se, 0x0, mas->tx_fifo_depth - 2); | |
288 | /* Transmit an entire FIFO worth of data per IRQ */ | |
289 | mas->tx_wm = 1; | |
290 | ver = geni_se_get_qup_hw_version(se); | |
291 | major = GENI_SE_VERSION_MAJOR(ver); | |
292 | minor = GENI_SE_VERSION_MINOR(ver); | |
293 | ||
294 | if (major == 1 && minor == 0) | |
295 | mas->oversampling = 2; | |
296 | else | |
297 | mas->oversampling = 1; | |
298 | ||
299 | pm_runtime_put(mas->dev); | |
300 | return 0; | |
301 | } | |
302 | ||
303 | static void setup_fifo_xfer(struct spi_transfer *xfer, | |
304 | struct spi_geni_master *mas, | |
305 | u16 mode, struct spi_master *spi) | |
306 | { | |
307 | u32 m_cmd = 0; | |
308 | u32 spi_tx_cfg, len; | |
309 | struct geni_se *se = &mas->se; | |
310 | ||
311 | spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); | |
312 | if (xfer->bits_per_word != mas->cur_bits_per_word) { | |
313 | spi_setup_word_len(mas, mode, xfer->bits_per_word); | |
314 | mas->cur_bits_per_word = xfer->bits_per_word; | |
315 | } | |
316 | ||
317 | /* Speed and bits per word can be overridden per transfer */ | |
318 | if (xfer->speed_hz != mas->cur_speed_hz) { | |
319 | int ret; | |
320 | u32 clk_sel, m_clk_cfg; | |
321 | unsigned int idx, div; | |
322 | ||
323 | ret = get_spi_clk_cfg(xfer->speed_hz, mas, &idx, &div); | |
324 | if (ret) { | |
325 | dev_err(mas->dev, "Err setting clks:%d\n", ret); | |
326 | return; | |
327 | } | |
328 | /* | |
329 | * SPI core clock gets configured with the requested frequency | |
330 | * or the frequency closer to the requested frequency. | |
331 | * For that reason requested frequency is stored in the | |
332 | * cur_speed_hz and referred in the consecutive transfer instead | |
333 | * of calling clk_get_rate() API. | |
334 | */ | |
335 | mas->cur_speed_hz = xfer->speed_hz; | |
336 | clk_sel = idx & CLK_SEL_MSK; | |
337 | m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; | |
338 | writel(clk_sel, se->base + SE_GENI_CLK_SEL); | |
339 | writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); | |
340 | } | |
341 | ||
342 | mas->tx_rem_bytes = 0; | |
343 | mas->rx_rem_bytes = 0; | |
344 | if (xfer->tx_buf && xfer->rx_buf) | |
345 | m_cmd = SPI_FULL_DUPLEX; | |
346 | else if (xfer->tx_buf) | |
347 | m_cmd = SPI_TX_ONLY; | |
348 | else if (xfer->rx_buf) | |
349 | m_cmd = SPI_RX_ONLY; | |
350 | ||
351 | spi_tx_cfg &= ~CS_TOGGLE; | |
352 | ||
353 | if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) | |
354 | len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; | |
355 | else | |
356 | len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); | |
357 | len &= TRANS_LEN_MSK; | |
358 | ||
359 | mas->cur_xfer = xfer; | |
360 | if (m_cmd & SPI_TX_ONLY) { | |
361 | mas->tx_rem_bytes = xfer->len; | |
362 | writel(len, se->base + SE_SPI_TX_TRANS_LEN); | |
363 | } | |
364 | ||
365 | if (m_cmd & SPI_RX_ONLY) { | |
366 | writel(len, se->base + SE_SPI_RX_TRANS_LEN); | |
367 | mas->rx_rem_bytes = xfer->len; | |
368 | } | |
369 | writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); | |
370 | mas->cur_mcmd = CMD_XFER; | |
371 | geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); | |
372 | ||
373 | /* | |
374 | * TX_WATERMARK_REG should be set after SPI configuration and | |
375 | * setting up GENI SE engine, as driver starts data transfer | |
376 | * for the watermark interrupt. | |
377 | */ | |
378 | if (m_cmd & SPI_TX_ONLY) | |
379 | writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); | |
380 | } | |
381 | ||
561de45f GM |
382 | static int spi_geni_transfer_one(struct spi_master *spi, |
383 | struct spi_device *slv, | |
384 | struct spi_transfer *xfer) | |
385 | { | |
386 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
387 | ||
388 | /* Terminate and return success for 0 byte length transfer */ | |
389 | if (!xfer->len) | |
390 | return 0; | |
391 | ||
392 | setup_fifo_xfer(xfer, mas, slv->mode, spi); | |
393 | return 1; | |
394 | } | |
395 | ||
396 | static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) | |
397 | { | |
398 | /* | |
399 | * Calculate how many bytes we'll put in each FIFO word. If the | |
400 | * transfer words don't pack cleanly into a FIFO word we'll just put | |
401 | * one transfer word in each FIFO word. If they do pack we'll pack 'em. | |
402 | */ | |
403 | if (mas->fifo_width_bits % mas->cur_bits_per_word) | |
404 | return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, | |
405 | BITS_PER_BYTE)); | |
406 | ||
407 | return mas->fifo_width_bits / BITS_PER_BYTE; | |
408 | } | |
409 | ||
410 | static void geni_spi_handle_tx(struct spi_geni_master *mas) | |
411 | { | |
412 | struct geni_se *se = &mas->se; | |
413 | unsigned int max_bytes; | |
414 | const u8 *tx_buf; | |
415 | unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); | |
416 | unsigned int i = 0; | |
417 | ||
418 | max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; | |
419 | if (mas->tx_rem_bytes < max_bytes) | |
420 | max_bytes = mas->tx_rem_bytes; | |
421 | ||
422 | tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; | |
423 | while (i < max_bytes) { | |
424 | unsigned int j; | |
425 | unsigned int bytes_to_write; | |
426 | u32 fifo_word = 0; | |
427 | u8 *fifo_byte = (u8 *)&fifo_word; | |
428 | ||
429 | bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); | |
430 | for (j = 0; j < bytes_to_write; j++) | |
431 | fifo_byte[j] = tx_buf[i++]; | |
432 | iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); | |
433 | } | |
434 | mas->tx_rem_bytes -= max_bytes; | |
435 | if (!mas->tx_rem_bytes) | |
436 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); | |
437 | } | |
438 | ||
439 | static void geni_spi_handle_rx(struct spi_geni_master *mas) | |
440 | { | |
441 | struct geni_se *se = &mas->se; | |
442 | u32 rx_fifo_status; | |
443 | unsigned int rx_bytes; | |
444 | unsigned int rx_last_byte_valid; | |
445 | u8 *rx_buf; | |
446 | unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); | |
447 | unsigned int i = 0; | |
448 | ||
449 | rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); | |
450 | rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; | |
451 | if (rx_fifo_status & RX_LAST) { | |
452 | rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; | |
453 | rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; | |
454 | if (rx_last_byte_valid && rx_last_byte_valid < 4) | |
455 | rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; | |
456 | } | |
457 | if (mas->rx_rem_bytes < rx_bytes) | |
458 | rx_bytes = mas->rx_rem_bytes; | |
459 | ||
460 | rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; | |
461 | while (i < rx_bytes) { | |
462 | u32 fifo_word = 0; | |
463 | u8 *fifo_byte = (u8 *)&fifo_word; | |
464 | unsigned int bytes_to_read; | |
465 | unsigned int j; | |
466 | ||
467 | bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); | |
468 | ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); | |
469 | for (j = 0; j < bytes_to_read; j++) | |
470 | rx_buf[i++] = fifo_byte[j]; | |
471 | } | |
472 | mas->rx_rem_bytes -= rx_bytes; | |
473 | } | |
474 | ||
475 | static irqreturn_t geni_spi_isr(int irq, void *data) | |
476 | { | |
477 | struct spi_master *spi = data; | |
478 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
479 | struct geni_se *se = &mas->se; | |
480 | u32 m_irq; | |
481 | unsigned long flags; | |
561de45f GM |
482 | |
483 | if (mas->cur_mcmd == CMD_NONE) | |
484 | return IRQ_NONE; | |
485 | ||
486 | spin_lock_irqsave(&mas->lock, flags); | |
487 | m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); | |
488 | ||
489 | if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) | |
490 | geni_spi_handle_rx(mas); | |
491 | ||
492 | if (m_irq & M_TX_FIFO_WATERMARK_EN) | |
493 | geni_spi_handle_tx(mas); | |
494 | ||
495 | if (m_irq & M_CMD_DONE_EN) { | |
496 | if (mas->cur_mcmd == CMD_XFER) | |
497 | spi_finalize_current_transfer(spi); | |
498 | else if (mas->cur_mcmd == CMD_CS) | |
499 | complete(&mas->xfer_done); | |
500 | mas->cur_mcmd = CMD_NONE; | |
501 | /* | |
502 | * If this happens, then a CMD_DONE came before all the Tx | |
503 | * buffer bytes were sent out. This is unusual, log this | |
504 | * condition and disable the WM interrupt to prevent the | |
505 | * system from stalling due an interrupt storm. | |
506 | * If this happens when all Rx bytes haven't been received, log | |
507 | * the condition. | |
508 | * The only known time this can happen is if bits_per_word != 8 | |
509 | * and some registers that expect xfer lengths in num spi_words | |
510 | * weren't written correctly. | |
511 | */ | |
512 | if (mas->tx_rem_bytes) { | |
513 | writel(0, se->base + SE_GENI_TX_WATERMARK_REG); | |
514 | dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", | |
515 | mas->tx_rem_bytes, mas->cur_bits_per_word); | |
516 | } | |
517 | if (mas->rx_rem_bytes) | |
518 | dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", | |
519 | mas->rx_rem_bytes, mas->cur_bits_per_word); | |
520 | } | |
521 | ||
522 | if ((m_irq & M_CMD_CANCEL_EN) || (m_irq & M_CMD_ABORT_EN)) { | |
523 | mas->cur_mcmd = CMD_NONE; | |
524 | complete(&mas->xfer_done); | |
525 | } | |
526 | ||
527 | writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); | |
528 | spin_unlock_irqrestore(&mas->lock, flags); | |
0dccff3c | 529 | return IRQ_HANDLED; |
561de45f GM |
530 | } |
531 | ||
532 | static int spi_geni_probe(struct platform_device *pdev) | |
533 | { | |
6a34e285 | 534 | int ret, irq; |
561de45f GM |
535 | struct spi_master *spi; |
536 | struct spi_geni_master *mas; | |
537 | struct resource *res; | |
6a34e285 AC |
538 | void __iomem *base; |
539 | struct clk *clk; | |
540 | ||
541 | irq = platform_get_irq(pdev, 0); | |
542 | if (irq < 0) { | |
543 | dev_err(&pdev->dev, "Err getting IRQ %d\n", irq); | |
544 | return irq; | |
545 | } | |
546 | ||
547 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
548 | base = devm_ioremap_resource(&pdev->dev, res); | |
549 | if (IS_ERR(base)) | |
550 | return PTR_ERR(base); | |
551 | ||
552 | clk = devm_clk_get(&pdev->dev, "se"); | |
553 | if (IS_ERR(clk)) { | |
554 | dev_err(&pdev->dev, "Err getting SE Core clk %ld\n", | |
555 | PTR_ERR(clk)); | |
556 | return PTR_ERR(clk); | |
557 | } | |
561de45f GM |
558 | |
559 | spi = spi_alloc_master(&pdev->dev, sizeof(*mas)); | |
560 | if (!spi) | |
561 | return -ENOMEM; | |
562 | ||
563 | platform_set_drvdata(pdev, spi); | |
564 | mas = spi_master_get_devdata(spi); | |
6a34e285 | 565 | mas->irq = irq; |
561de45f GM |
566 | mas->dev = &pdev->dev; |
567 | mas->se.dev = &pdev->dev; | |
568 | mas->se.wrapper = dev_get_drvdata(pdev->dev.parent); | |
6a34e285 AC |
569 | mas->se.base = base; |
570 | mas->se.clk = clk; | |
561de45f GM |
571 | |
572 | spi->bus_num = -1; | |
573 | spi->dev.of_node = pdev->dev.of_node; | |
561de45f GM |
574 | spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; |
575 | spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
576 | spi->num_chipselect = 4; | |
577 | spi->max_speed_hz = 50000000; | |
578 | spi->prepare_message = spi_geni_prepare_message; | |
579 | spi->transfer_one = spi_geni_transfer_one; | |
580 | spi->auto_runtime_pm = true; | |
581 | spi->handle_err = handle_fifo_timeout; | |
582 | spi->set_cs = spi_geni_set_cs; | |
583 | ||
584 | init_completion(&mas->xfer_done); | |
585 | spin_lock_init(&mas->lock); | |
586 | pm_runtime_enable(&pdev->dev); | |
587 | ||
588 | ret = spi_geni_init(mas); | |
589 | if (ret) | |
590 | goto spi_geni_probe_runtime_disable; | |
591 | ||
561de45f GM |
592 | ret = request_irq(mas->irq, geni_spi_isr, |
593 | IRQF_TRIGGER_HIGH, "spi_geni", spi); | |
594 | if (ret) | |
595 | goto spi_geni_probe_runtime_disable; | |
596 | ||
597 | ret = spi_register_master(spi); | |
598 | if (ret) | |
599 | goto spi_geni_probe_free_irq; | |
600 | ||
601 | return 0; | |
602 | spi_geni_probe_free_irq: | |
603 | free_irq(mas->irq, spi); | |
604 | spi_geni_probe_runtime_disable: | |
605 | pm_runtime_disable(&pdev->dev); | |
561de45f GM |
606 | spi_master_put(spi); |
607 | return ret; | |
608 | } | |
609 | ||
610 | static int spi_geni_remove(struct platform_device *pdev) | |
611 | { | |
612 | struct spi_master *spi = platform_get_drvdata(pdev); | |
613 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
614 | ||
615 | /* Unregister _before_ disabling pm_runtime() so we stop transfers */ | |
616 | spi_unregister_master(spi); | |
617 | ||
618 | free_irq(mas->irq, spi); | |
619 | pm_runtime_disable(&pdev->dev); | |
620 | return 0; | |
621 | } | |
622 | ||
623 | static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) | |
624 | { | |
625 | struct spi_master *spi = dev_get_drvdata(dev); | |
626 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
627 | ||
628 | return geni_se_resources_off(&mas->se); | |
629 | } | |
630 | ||
631 | static int __maybe_unused spi_geni_runtime_resume(struct device *dev) | |
632 | { | |
633 | struct spi_master *spi = dev_get_drvdata(dev); | |
634 | struct spi_geni_master *mas = spi_master_get_devdata(spi); | |
635 | ||
636 | return geni_se_resources_on(&mas->se); | |
637 | } | |
638 | ||
639 | static int __maybe_unused spi_geni_suspend(struct device *dev) | |
640 | { | |
641 | struct spi_master *spi = dev_get_drvdata(dev); | |
642 | int ret; | |
643 | ||
644 | ret = spi_master_suspend(spi); | |
645 | if (ret) | |
646 | return ret; | |
647 | ||
648 | ret = pm_runtime_force_suspend(dev); | |
649 | if (ret) | |
650 | spi_master_resume(spi); | |
651 | ||
652 | return ret; | |
653 | } | |
654 | ||
655 | static int __maybe_unused spi_geni_resume(struct device *dev) | |
656 | { | |
657 | struct spi_master *spi = dev_get_drvdata(dev); | |
658 | int ret; | |
659 | ||
660 | ret = pm_runtime_force_resume(dev); | |
661 | if (ret) | |
662 | return ret; | |
663 | ||
664 | ret = spi_master_resume(spi); | |
665 | if (ret) | |
666 | pm_runtime_force_suspend(dev); | |
667 | ||
668 | return ret; | |
669 | } | |
670 | ||
671 | static const struct dev_pm_ops spi_geni_pm_ops = { | |
672 | SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, | |
673 | spi_geni_runtime_resume, NULL) | |
674 | SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) | |
675 | }; | |
676 | ||
677 | static const struct of_device_id spi_geni_dt_match[] = { | |
678 | { .compatible = "qcom,geni-spi" }, | |
679 | {} | |
680 | }; | |
681 | MODULE_DEVICE_TABLE(of, spi_geni_dt_match); | |
682 | ||
683 | static struct platform_driver spi_geni_driver = { | |
684 | .probe = spi_geni_probe, | |
685 | .remove = spi_geni_remove, | |
686 | .driver = { | |
687 | .name = "geni_spi", | |
688 | .pm = &spi_geni_pm_ops, | |
689 | .of_match_table = spi_geni_dt_match, | |
690 | }, | |
691 | }; | |
692 | module_platform_driver(spi_geni_driver); | |
693 | ||
694 | MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); | |
695 | MODULE_LICENSE("GPL v2"); |