Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
ccf06998 | 2 | /* |
b36ece83 | 3 | * Freescale SPI controller driver. |
ccf06998 KG |
4 | * |
5 | * Maintainer: Kumar Gala | |
6 | * | |
7 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 8 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 9 | * |
4c1fba44 AV |
10 | * CPM SPI and QE buffer descriptors mode support: |
11 | * Copyright (c) 2009 MontaVista Software, Inc. | |
12 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
13 | * | |
447b0c7b AL |
14 | * GRLIB support: |
15 | * Copyright (c) 2012 Aeroflex Gaisler AB. | |
16 | * Author: Andreas Larsson <andreas@gaisler.com> | |
ccf06998 | 17 | */ |
ccf06998 | 18 | #include <linux/delay.h> |
4c1fba44 | 19 | #include <linux/dma-mapping.h> |
a3108360 | 20 | #include <linux/fsl_devices.h> |
0f0581b2 | 21 | #include <linux/gpio/consumer.h> |
a3108360 XL |
22 | #include <linux/interrupt.h> |
23 | #include <linux/irq.h> | |
24 | #include <linux/kernel.h> | |
4c1fba44 | 25 | #include <linux/mm.h> |
a3108360 | 26 | #include <linux/module.h> |
4c1fba44 | 27 | #include <linux/mutex.h> |
35b4b3c0 | 28 | #include <linux/of.h> |
e8beacbb AL |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
a3108360 XL |
31 | #include <linux/of_platform.h> |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/spi/spi.h> | |
34 | #include <linux/spi/spi_bitbang.h> | |
35 | #include <linux/types.h> | |
ccf06998 | 36 | |
69b921ac RV |
37 | #ifdef CONFIG_FSL_SOC |
38 | #include <sysdev/fsl_soc.h> | |
39 | #endif | |
40 | ||
41 | /* Specific to the MPC8306/MPC8309 */ | |
42 | #define IMMR_SPI_CS_OFFSET 0x14c | |
43 | #define SPI_BOOT_SEL_BIT 0x80000000 | |
44 | ||
ca632f55 | 45 | #include "spi-fsl-lib.h" |
e8beacbb AL |
46 | #include "spi-fsl-cpm.h" |
47 | #include "spi-fsl-spi.h" | |
ccf06998 | 48 | |
c3f3e771 | 49 | #define TYPE_FSL 0 |
447b0c7b | 50 | #define TYPE_GRLIB 1 |
c3f3e771 AL |
51 | |
52 | struct fsl_spi_match_data { | |
53 | int type; | |
54 | }; | |
55 | ||
56 | static struct fsl_spi_match_data of_fsl_spi_fsl_config = { | |
57 | .type = TYPE_FSL, | |
58 | }; | |
59 | ||
447b0c7b AL |
60 | static struct fsl_spi_match_data of_fsl_spi_grlib_config = { |
61 | .type = TYPE_GRLIB, | |
62 | }; | |
63 | ||
3aea901d | 64 | static const struct of_device_id of_fsl_spi_match[] = { |
c3f3e771 AL |
65 | { |
66 | .compatible = "fsl,spi", | |
67 | .data = &of_fsl_spi_fsl_config, | |
68 | }, | |
447b0c7b AL |
69 | { |
70 | .compatible = "aeroflexgaisler,spictrl", | |
71 | .data = &of_fsl_spi_grlib_config, | |
72 | }, | |
c3f3e771 AL |
73 | {} |
74 | }; | |
75 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); | |
76 | ||
77 | static int fsl_spi_get_type(struct device *dev) | |
78 | { | |
79 | const struct of_device_id *match; | |
80 | ||
81 | if (dev->of_node) { | |
82 | match = of_match_node(of_fsl_spi_match, dev->of_node); | |
83 | if (match && match->data) | |
84 | return ((struct fsl_spi_match_data *)match->data)->type; | |
85 | } | |
86 | return TYPE_FSL; | |
87 | } | |
88 | ||
b36ece83 | 89 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
90 | { |
91 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
92 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
dd67de8c | 93 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
b36ece83 | 94 | __be32 __iomem *mode = ®_base->mode; |
a35c1710 AV |
95 | unsigned long flags; |
96 | ||
97 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
98 | return; | |
99 | ||
100 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
101 | local_irq_save(flags); | |
102 | ||
103 | /* Turn off SPI unit prior changing mode */ | |
104 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 105 | |
4c1fba44 AV |
106 | /* When in CPM mode, we need to reinit tx and rx. */ |
107 | if (mspi->flags & SPI_CPM_MODE) { | |
e8beacbb | 108 | fsl_spi_cpm_reinit_txrx(mspi); |
4c1fba44 | 109 | } |
f9218c2a | 110 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
111 | local_irq_restore(flags); |
112 | } | |
113 | ||
b36ece83 | 114 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 115 | { |
575c5807 | 116 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
5039a869 | 117 | struct fsl_spi_platform_data *pdata; |
364fdbc0 | 118 | bool pol = spi->mode & SPI_CS_HIGH; |
575c5807 | 119 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 120 | |
5039a869 KE |
121 | pdata = spi->dev.parent->parent->platform_data; |
122 | ||
ccf06998 | 123 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
124 | if (pdata->cs_control) |
125 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
126 | } |
127 | ||
128 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
129 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
130 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
131 | mpc8xxx_spi->get_rx = cs->get_rx; | |
132 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 133 | |
b36ece83 | 134 | fsl_spi_change_mode(spi); |
a35c1710 | 135 | |
364fdbc0 AV |
136 | if (pdata->cs_control) |
137 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
138 | } |
139 | } | |
140 | ||
b48c4e3c AL |
141 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
142 | int bits_per_word, int msb_first) | |
143 | { | |
144 | *rx_shift = 0; | |
145 | *tx_shift = 0; | |
146 | if (msb_first) { | |
147 | if (bits_per_word <= 8) { | |
148 | *rx_shift = 16; | |
149 | *tx_shift = 24; | |
150 | } else if (bits_per_word <= 16) { | |
151 | *rx_shift = 16; | |
152 | *tx_shift = 16; | |
153 | } | |
154 | } else { | |
155 | if (bits_per_word <= 8) | |
156 | *rx_shift = 8; | |
157 | } | |
158 | } | |
159 | ||
447b0c7b AL |
160 | static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, |
161 | int bits_per_word, int msb_first) | |
162 | { | |
163 | *rx_shift = 0; | |
164 | *tx_shift = 0; | |
165 | if (bits_per_word <= 16) { | |
166 | if (msb_first) { | |
167 | *rx_shift = 16; /* LSB in bit 16 */ | |
168 | *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ | |
169 | } else { | |
170 | *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ | |
171 | } | |
172 | } | |
173 | } | |
174 | ||
b36ece83 MH |
175 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
176 | struct spi_device *spi, | |
177 | struct mpc8xxx_spi *mpc8xxx_spi, | |
178 | int bits_per_word) | |
ccf06998 | 179 | { |
c9bfcb31 JT |
180 | cs->rx_shift = 0; |
181 | cs->tx_shift = 0; | |
ccf06998 | 182 | if (bits_per_word <= 8) { |
575c5807 AV |
183 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
184 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
ccf06998 | 185 | } else if (bits_per_word <= 16) { |
575c5807 AV |
186 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
187 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
ccf06998 | 188 | } else if (bits_per_word <= 32) { |
575c5807 AV |
189 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
190 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
191 | } else |
192 | return -EINVAL; | |
193 | ||
b48c4e3c AL |
194 | if (mpc8xxx_spi->set_shifts) |
195 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, | |
196 | bits_per_word, | |
197 | !(spi->mode & SPI_LSB_FIRST)); | |
198 | ||
575c5807 AV |
199 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
200 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
201 | mpc8xxx_spi->get_rx = cs->get_rx; | |
202 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 203 | |
0398fb70 JT |
204 | return bits_per_word; |
205 | } | |
206 | ||
b36ece83 MH |
207 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
208 | struct spi_device *spi, | |
209 | int bits_per_word) | |
0398fb70 JT |
210 | { |
211 | /* QE uses Little Endian for words > 8 | |
212 | * so transform all words > 8 into 8 bits | |
213 | * Unfortnatly that doesn't work for LSB so | |
214 | * reject these for now */ | |
215 | /* Note: 32 bits word, LSB works iff | |
216 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
217 | if (spi->mode & SPI_LSB_FIRST && | |
218 | bits_per_word > 8) | |
219 | return -EINVAL; | |
220 | if (bits_per_word > 8) | |
221 | return 8; /* pretend its 8 bits */ | |
222 | return bits_per_word; | |
223 | } | |
224 | ||
b36ece83 MH |
225 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
226 | struct spi_transfer *t) | |
0398fb70 JT |
227 | { |
228 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 229 | int bits_per_word = 0; |
0398fb70 | 230 | u8 pm; |
b36ece83 | 231 | u32 hz = 0; |
0398fb70 JT |
232 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
233 | ||
234 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
235 | ||
236 | if (t) { | |
237 | bits_per_word = t->bits_per_word; | |
238 | hz = t->speed_hz; | |
0398fb70 JT |
239 | } |
240 | ||
241 | /* spi_transfer level calls that work per-word */ | |
242 | if (!bits_per_word) | |
243 | bits_per_word = spi->bits_per_word; | |
244 | ||
0398fb70 JT |
245 | if (!hz) |
246 | hz = spi->max_speed_hz; | |
247 | ||
248 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
249 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
250 | mpc8xxx_spi, | |
251 | bits_per_word); | |
252 | else if (mpc8xxx_spi->flags & SPI_QE) | |
253 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
254 | bits_per_word); | |
255 | ||
256 | if (bits_per_word < 0) | |
257 | return bits_per_word; | |
258 | ||
ccf06998 KG |
259 | if (bits_per_word == 32) |
260 | bits_per_word = 0; | |
261 | else | |
262 | bits_per_word = bits_per_word - 1; | |
263 | ||
32421daa | 264 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
265 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
266 | | SPMODE_PM(0xF)); | |
267 | ||
268 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
269 | ||
575c5807 | 270 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 271 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 272 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
31ae7794 ME |
273 | WARN_ONCE(pm > 16, |
274 | "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", | |
275 | dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); | |
fd8a11e1 | 276 | if (pm > 16) |
53604dbe | 277 | pm = 16; |
b36ece83 | 278 | } else { |
4f4517c4 | 279 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 280 | } |
a61f5345 CG |
281 | if (pm) |
282 | pm--; | |
283 | ||
284 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 285 | |
b36ece83 | 286 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
287 | return 0; |
288 | } | |
ccf06998 | 289 | |
b36ece83 | 290 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
291 | struct spi_transfer *t, unsigned int len) |
292 | { | |
293 | u32 word; | |
dd67de8c | 294 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
4c1fba44 AV |
295 | |
296 | mspi->count = len; | |
297 | ||
298 | /* enable rx ints */ | |
b36ece83 | 299 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
300 | |
301 | /* transmit word */ | |
302 | word = mspi->get_tx(mspi); | |
b36ece83 | 303 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
b36ece83 | 308 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
309 | bool is_dma_mapped) |
310 | { | |
311 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
dd67de8c | 312 | struct fsl_spi_reg __iomem *reg_base; |
4c1fba44 AV |
313 | unsigned int len = t->len; |
314 | u8 bits_per_word; | |
315 | int ret; | |
c9bfcb31 | 316 | |
b36ece83 | 317 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
318 | bits_per_word = spi->bits_per_word; |
319 | if (t->bits_per_word) | |
320 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 321 | |
aa77d96b PK |
322 | if (bits_per_word > 8) { |
323 | /* invalid length? */ | |
324 | if (len & 1) | |
325 | return -EINVAL; | |
c9bfcb31 | 326 | len /= 2; |
aa77d96b PK |
327 | } |
328 | if (bits_per_word > 16) { | |
329 | /* invalid length? */ | |
330 | if (len & 1) | |
331 | return -EINVAL; | |
c9bfcb31 | 332 | len /= 2; |
aa77d96b | 333 | } |
aa77d96b | 334 | |
4c1fba44 AV |
335 | mpc8xxx_spi->tx = t->tx_buf; |
336 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 337 | |
16735d02 | 338 | reinit_completion(&mpc8xxx_spi->done); |
c9bfcb31 | 339 | |
4c1fba44 | 340 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 341 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 342 | else |
b36ece83 | 343 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
344 | if (ret) |
345 | return ret; | |
c9bfcb31 | 346 | |
575c5807 | 347 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
348 | |
349 | /* disable rx ints */ | |
b36ece83 | 350 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 351 | |
4c1fba44 | 352 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 353 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 354 | |
575c5807 | 355 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
356 | } |
357 | ||
c592becb HK |
358 | static int fsl_spi_do_one_msg(struct spi_master *master, |
359 | struct spi_message *m) | |
c9bfcb31 | 360 | { |
af0e6242 | 361 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
b9b9af11 | 362 | struct spi_device *spi = m->spi; |
4302a596 | 363 | struct spi_transfer *t, *first; |
b9b9af11 AV |
364 | unsigned int cs_change; |
365 | const int nsecs = 50; | |
a798a708 | 366 | int status, last_bpw; |
b9b9af11 | 367 | |
af0e6242 RV |
368 | /* |
369 | * In CPU mode, optimize large byte transfers to use larger | |
370 | * bits_per_word values to reduce number of interrupts taken. | |
371 | */ | |
372 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { | |
373 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
374 | if (t->len < 256 || t->bits_per_word != 8) | |
375 | continue; | |
376 | if ((t->len & 3) == 0) | |
377 | t->bits_per_word = 32; | |
378 | else if ((t->len & 1) == 0) | |
379 | t->bits_per_word = 16; | |
380 | } | |
381 | } | |
382 | ||
4302a596 | 383 | /* Don't allow changes if CS is active */ |
17ecffa2 | 384 | cs_change = 1; |
b9b9af11 | 385 | list_for_each_entry(t, &m->transfers, transfer_list) { |
17ecffa2 RV |
386 | if (cs_change) |
387 | first = t; | |
388 | cs_change = t->cs_change; | |
a798a708 | 389 | if (first->speed_hz != t->speed_hz) { |
4302a596 | 390 | dev_err(&spi->dev, |
a798a708 | 391 | "speed_hz cannot change while CS is active\n"); |
75c41088 | 392 | return -EINVAL; |
4302a596 SR |
393 | } |
394 | } | |
b9b9af11 | 395 | |
a798a708 | 396 | last_bpw = -1; |
4302a596 SR |
397 | cs_change = 1; |
398 | status = -EINVAL; | |
399 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
a798a708 | 400 | if (cs_change || last_bpw != t->bits_per_word) |
24c36362 RV |
401 | status = fsl_spi_setup_transfer(spi, t); |
402 | if (status < 0) | |
403 | break; | |
a798a708 | 404 | last_bpw = t->bits_per_word; |
c9bfcb31 | 405 | |
b9b9af11 | 406 | if (cs_change) { |
b36ece83 | 407 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
408 | ndelay(nsecs); |
409 | } | |
410 | cs_change = t->cs_change; | |
411 | if (t->len) | |
b36ece83 | 412 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
413 | if (status) { |
414 | status = -EMSGSIZE; | |
415 | break; | |
c9bfcb31 | 416 | } |
b9b9af11 | 417 | m->actual_length += t->len; |
c9bfcb31 | 418 | |
e74dc5c7 | 419 | spi_transfer_delay_exec(t); |
c9bfcb31 | 420 | |
b9b9af11 | 421 | if (cs_change) { |
c9bfcb31 | 422 | ndelay(nsecs); |
b36ece83 | 423 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 424 | ndelay(nsecs); |
c9bfcb31 | 425 | } |
b9b9af11 AV |
426 | } |
427 | ||
428 | m->status = status; | |
b9b9af11 AV |
429 | |
430 | if (status || !cs_change) { | |
431 | ndelay(nsecs); | |
b36ece83 | 432 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
433 | } |
434 | ||
b36ece83 | 435 | fsl_spi_setup_transfer(spi, NULL); |
44a04218 | 436 | spi_finalize_current_message(master); |
c592becb | 437 | return 0; |
ccf06998 KG |
438 | } |
439 | ||
b36ece83 | 440 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 441 | { |
575c5807 | 442 | struct mpc8xxx_spi *mpc8xxx_spi; |
dd67de8c | 443 | struct fsl_spi_reg __iomem *reg_base; |
ccf06998 | 444 | int retval; |
c9bfcb31 | 445 | u32 hw_mode; |
d9f26748 | 446 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
ccf06998 KG |
447 | |
448 | if (!spi->max_speed_hz) | |
449 | return -EINVAL; | |
450 | ||
c9bfcb31 | 451 | if (!cs) { |
d9f26748 | 452 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
c9bfcb31 JT |
453 | if (!cs) |
454 | return -ENOMEM; | |
d9f26748 | 455 | spi_set_ctldata(spi, cs); |
c9bfcb31 | 456 | } |
575c5807 | 457 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 458 | |
b36ece83 MH |
459 | reg_base = mpc8xxx_spi->reg_base; |
460 | ||
88393161 | 461 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 462 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
463 | /* mask out bits we are going to set */ |
464 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
465 | | SPMODE_REV | SPMODE_LOOP); | |
466 | ||
467 | if (spi->mode & SPI_CPHA) | |
468 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
469 | if (spi->mode & SPI_CPOL) | |
470 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
471 | if (!(spi->mode & SPI_LSB_FIRST)) | |
472 | cs->hw_mode |= SPMODE_REV; | |
473 | if (spi->mode & SPI_LOOP) | |
474 | cs->hw_mode |= SPMODE_LOOP; | |
475 | ||
b36ece83 | 476 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
477 | if (retval < 0) { |
478 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 479 | return retval; |
c9bfcb31 | 480 | } |
f482cd0f AL |
481 | |
482 | /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ | |
483 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
484 | ||
ccf06998 KG |
485 | return 0; |
486 | } | |
487 | ||
76a7498f AL |
488 | static void fsl_spi_cleanup(struct spi_device *spi) |
489 | { | |
d9f26748 | 490 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
76a7498f | 491 | |
d9f26748 AL |
492 | kfree(cs); |
493 | spi_set_ctldata(spi, NULL); | |
76a7498f AL |
494 | } |
495 | ||
b36ece83 | 496 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 497 | { |
dd67de8c | 498 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
b36ece83 | 499 | |
4c1fba44 AV |
500 | /* We need handle RX first */ |
501 | if (events & SPIE_NE) { | |
b36ece83 | 502 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
503 | |
504 | if (mspi->rx) | |
505 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
506 | } |
507 | ||
4c1fba44 | 508 | if ((events & SPIE_NF) == 0) |
ccf06998 | 509 | /* spin until TX is done */ |
4c1fba44 | 510 | while (((events = |
b36ece83 | 511 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 512 | SPIE_NF) == 0) |
9effb959 | 513 | cpu_relax(); |
ccf06998 | 514 | |
4c1fba44 | 515 | /* Clear the events */ |
b36ece83 | 516 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
517 | |
518 | mspi->count -= 1; | |
519 | if (mspi->count) { | |
520 | u32 word = mspi->get_tx(mspi); | |
521 | ||
b36ece83 | 522 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 523 | } else { |
4c1fba44 | 524 | complete(&mspi->done); |
ccf06998 | 525 | } |
4c1fba44 | 526 | } |
ccf06998 | 527 | |
b36ece83 | 528 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
529 | { |
530 | struct mpc8xxx_spi *mspi = context_data; | |
531 | irqreturn_t ret = IRQ_NONE; | |
532 | u32 events; | |
dd67de8c | 533 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
4c1fba44 AV |
534 | |
535 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 536 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
537 | if (events) |
538 | ret = IRQ_HANDLED; | |
539 | ||
540 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
541 | ||
542 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 543 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 544 | else |
b36ece83 | 545 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
546 | |
547 | return ret; | |
548 | } | |
4c1fba44 | 549 | |
447b0c7b AL |
550 | static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) |
551 | { | |
552 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
dd67de8c | 553 | struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; |
447b0c7b AL |
554 | u32 slvsel; |
555 | u16 cs = spi->chip_select; | |
556 | ||
0f0581b2 LW |
557 | if (spi->cs_gpiod) { |
558 | gpiod_set_value(spi->cs_gpiod, on); | |
76a7498f AL |
559 | } else if (cs < mpc8xxx_spi->native_chipselects) { |
560 | slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); | |
561 | slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); | |
562 | mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); | |
563 | } | |
447b0c7b AL |
564 | } |
565 | ||
566 | static void fsl_spi_grlib_probe(struct device *dev) | |
567 | { | |
8074cf06 | 568 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
447b0c7b AL |
569 | struct spi_master *master = dev_get_drvdata(dev); |
570 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
dd67de8c | 571 | struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; |
447b0c7b AL |
572 | int mbits; |
573 | u32 capabilities; | |
574 | ||
575 | capabilities = mpc8xxx_spi_read_reg(®_base->cap); | |
576 | ||
577 | mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; | |
578 | mbits = SPCAP_MAXWLEN(capabilities); | |
579 | if (mbits) | |
580 | mpc8xxx_spi->max_bits_per_word = mbits + 1; | |
581 | ||
76a7498f | 582 | mpc8xxx_spi->native_chipselects = 0; |
447b0c7b | 583 | if (SPCAP_SSEN(capabilities)) { |
76a7498f | 584 | mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); |
447b0c7b AL |
585 | mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); |
586 | } | |
76a7498f | 587 | master->num_chipselect = mpc8xxx_spi->native_chipselects; |
447b0c7b AL |
588 | pdata->cs_control = fsl_spi_grlib_cs_control; |
589 | } | |
590 | ||
7cb88afb | 591 | static struct spi_master *fsl_spi_probe(struct device *dev, |
b36ece83 | 592 | struct resource *mem, unsigned int irq) |
ccf06998 | 593 | { |
8074cf06 | 594 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
ccf06998 | 595 | struct spi_master *master; |
575c5807 | 596 | struct mpc8xxx_spi *mpc8xxx_spi; |
dd67de8c | 597 | struct fsl_spi_reg __iomem *reg_base; |
ccf06998 KG |
598 | u32 regval; |
599 | int ret = 0; | |
600 | ||
575c5807 | 601 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
602 | if (master == NULL) { |
603 | ret = -ENOMEM; | |
604 | goto err; | |
605 | } | |
606 | ||
35b4b3c0 | 607 | dev_set_drvdata(dev, master); |
ccf06998 | 608 | |
c592becb | 609 | mpc8xxx_spi_probe(dev, mem, irq); |
e7db06b5 | 610 | |
b36ece83 | 611 | master->setup = fsl_spi_setup; |
76a7498f | 612 | master->cleanup = fsl_spi_cleanup; |
c592becb | 613 | master->transfer_one_message = fsl_spi_do_one_msg; |
f1069049 | 614 | master->use_gpio_descriptors = true; |
575c5807 AV |
615 | |
616 | mpc8xxx_spi = spi_master_get_devdata(master); | |
8922a366 | 617 | mpc8xxx_spi->max_bits_per_word = 32; |
c3f3e771 | 618 | mpc8xxx_spi->type = fsl_spi_get_type(dev); |
575c5807 | 619 | |
b36ece83 | 620 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
621 | if (ret) |
622 | goto err_cpm_init; | |
623 | ||
4178b6b1 | 624 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
625 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
626 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
4178b6b1 | 627 | goto err_probe; |
447b0c7b AL |
628 | } |
629 | ||
630 | if (mpc8xxx_spi->type == TYPE_GRLIB) | |
631 | fsl_spi_grlib_probe(dev); | |
632 | ||
f734394d AL |
633 | master->bits_per_word_mask = |
634 | (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & | |
635 | SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); | |
636 | ||
b48c4e3c AL |
637 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
638 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; | |
639 | ||
640 | if (mpc8xxx_spi->set_shifts) | |
641 | /* 8 bits per word and MSB first */ | |
642 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, | |
643 | &mpc8xxx_spi->tx_shift, 8, 1); | |
f29ba280 | 644 | |
ccf06998 | 645 | /* Register for SPI Interrupt */ |
4178b6b1 HK |
646 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, |
647 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
648 | |
649 | if (ret != 0) | |
4178b6b1 | 650 | goto err_probe; |
ccf06998 | 651 | |
b36ece83 | 652 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
653 | |
654 | /* SPI controller initializations */ | |
b36ece83 MH |
655 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
656 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
657 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
658 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
659 | |
660 | /* Enable SPI interface */ | |
661 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
8922a366 AL |
662 | if (mpc8xxx_spi->max_bits_per_word < 8) { |
663 | regval &= ~SPMODE_LEN(0xF); | |
664 | regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); | |
665 | } | |
87ec0e98 | 666 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
667 | regval |= SPMODE_OP; |
668 | ||
b36ece83 | 669 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 | 670 | |
4178b6b1 | 671 | ret = devm_spi_register_master(dev, master); |
c9bfcb31 | 672 | if (ret < 0) |
4178b6b1 | 673 | goto err_probe; |
ccf06998 | 674 | |
b36ece83 | 675 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 676 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 677 | |
35b4b3c0 | 678 | return master; |
ccf06998 | 679 | |
4178b6b1 | 680 | err_probe: |
b36ece83 | 681 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 682 | err_cpm_init: |
ccf06998 | 683 | spi_master_put(master); |
ccf06998 | 684 | err: |
35b4b3c0 | 685 | return ERR_PTR(ret); |
ccf06998 KG |
686 | } |
687 | ||
b36ece83 | 688 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 | 689 | { |
0f0581b2 LW |
690 | if (spi->cs_gpiod) { |
691 | gpiod_set_value(spi->cs_gpiod, on); | |
69b921ac | 692 | } else { |
0f0581b2 LW |
693 | struct device *dev = spi->dev.parent->parent; |
694 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
695 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
696 | ||
697 | if (WARN_ON_ONCE(!pinfo->immr_spi_cs)) | |
69b921ac RV |
698 | return; |
699 | iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs); | |
700 | } | |
35b4b3c0 AV |
701 | } |
702 | ||
fd4a319b | 703 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
704 | { |
705 | struct device *dev = &ofdev->dev; | |
61c7a080 | 706 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
707 | struct spi_master *master; |
708 | struct resource mem; | |
2f3d8035 CL |
709 | int irq, type; |
710 | int ret; | |
35b4b3c0 | 711 | |
18d306d1 | 712 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
713 | if (ret) |
714 | return ret; | |
35b4b3c0 | 715 | |
447b0c7b AL |
716 | type = fsl_spi_get_type(&ofdev->dev); |
717 | if (type == TYPE_FSL) { | |
0f0581b2 LW |
718 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
719 | #if IS_ENABLED(CONFIG_FSL_SOC) | |
720 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
721 | bool spisel_boot = of_property_read_bool(np, "fsl,spisel_boot"); | |
722 | ||
723 | if (spisel_boot) { | |
724 | pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); | |
2f3d8035 CL |
725 | if (!pinfo->immr_spi_cs) |
726 | return -ENOMEM; | |
0f0581b2 LW |
727 | } |
728 | #endif | |
7251953d LW |
729 | /* |
730 | * Handle the case where we have one hardwired (always selected) | |
731 | * device on the first "chipselect". Else we let the core code | |
732 | * handle any GPIOs or native chip selects and assign the | |
733 | * appropriate callback for dealing with the CS lines. This isn't | |
734 | * supported on the GRLIB variant. | |
735 | */ | |
736 | ret = gpiod_count(dev, "cs"); | |
737 | if (ret <= 0) | |
738 | pdata->max_chipselect = 1; | |
739 | else | |
740 | pdata->cs_control = fsl_spi_cs_control; | |
447b0c7b | 741 | } |
35b4b3c0 AV |
742 | |
743 | ret = of_address_to_resource(np, 0, &mem); | |
744 | if (ret) | |
2f3d8035 | 745 | return ret; |
35b4b3c0 | 746 | |
63aa6a69 | 747 | irq = platform_get_irq(ofdev, 0); |
2f3d8035 CL |
748 | if (irq < 0) |
749 | return irq; | |
35b4b3c0 | 750 | |
e8beacbb | 751 | master = fsl_spi_probe(dev, &mem, irq); |
35b4b3c0 | 752 | |
2f3d8035 | 753 | return PTR_ERR_OR_ZERO(master); |
35b4b3c0 AV |
754 | } |
755 | ||
fd4a319b | 756 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 | 757 | { |
24b5a82c | 758 | struct spi_master *master = platform_get_drvdata(ofdev); |
447b0c7b | 759 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
35b4b3c0 | 760 | |
3c5395b6 | 761 | fsl_spi_cpm_free(mpc8xxx_spi); |
35b4b3c0 AV |
762 | return 0; |
763 | } | |
764 | ||
18d306d1 | 765 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 766 | .driver = { |
b36ece83 | 767 | .name = "fsl_spi", |
b36ece83 | 768 | .of_match_table = of_fsl_spi_match, |
4018294b | 769 | }, |
b36ece83 | 770 | .probe = of_fsl_spi_probe, |
fd4a319b | 771 | .remove = of_fsl_spi_remove, |
35b4b3c0 AV |
772 | }; |
773 | ||
774 | #ifdef CONFIG_MPC832x_RDB | |
775 | /* | |
b36ece83 | 776 | * XXX XXX XXX |
35b4b3c0 AV |
777 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
778 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
779 | * tree can work with OpenFirmware driver. But for now we support old trees | |
780 | * as well. | |
781 | */ | |
fd4a319b | 782 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
783 | { |
784 | struct resource *mem; | |
e9a172f0 | 785 | int irq; |
35b4b3c0 AV |
786 | struct spi_master *master; |
787 | ||
8074cf06 | 788 | if (!dev_get_platdata(&pdev->dev)) |
35b4b3c0 AV |
789 | return -EINVAL; |
790 | ||
791 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
792 | if (!mem) | |
793 | return -EINVAL; | |
794 | ||
795 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 796 | if (irq <= 0) |
35b4b3c0 AV |
797 | return -EINVAL; |
798 | ||
b36ece83 | 799 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
8c6ffba0 | 800 | return PTR_ERR_OR_ZERO(master); |
35b4b3c0 AV |
801 | } |
802 | ||
fd4a319b | 803 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 804 | { |
3c5395b6 HK |
805 | struct spi_master *master = platform_get_drvdata(pdev); |
806 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
807 | ||
808 | fsl_spi_cpm_free(mpc8xxx_spi); | |
809 | ||
810 | return 0; | |
35b4b3c0 AV |
811 | } |
812 | ||
575c5807 AV |
813 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
814 | static struct platform_driver mpc8xxx_spi_driver = { | |
815 | .probe = plat_mpc8xxx_spi_probe, | |
fd4a319b | 816 | .remove = plat_mpc8xxx_spi_remove, |
ccf06998 | 817 | .driver = { |
575c5807 | 818 | .name = "mpc8xxx_spi", |
ccf06998 KG |
819 | }, |
820 | }; | |
821 | ||
35b4b3c0 AV |
822 | static bool legacy_driver_failed; |
823 | ||
824 | static void __init legacy_driver_register(void) | |
825 | { | |
575c5807 | 826 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
827 | } |
828 | ||
829 | static void __exit legacy_driver_unregister(void) | |
830 | { | |
831 | if (legacy_driver_failed) | |
832 | return; | |
575c5807 | 833 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
834 | } |
835 | #else | |
836 | static void __init legacy_driver_register(void) {} | |
837 | static void __exit legacy_driver_unregister(void) {} | |
838 | #endif /* CONFIG_MPC832x_RDB */ | |
839 | ||
b36ece83 | 840 | static int __init fsl_spi_init(void) |
ccf06998 | 841 | { |
35b4b3c0 | 842 | legacy_driver_register(); |
18d306d1 | 843 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 844 | } |
b36ece83 | 845 | module_init(fsl_spi_init); |
ccf06998 | 846 | |
b36ece83 | 847 | static void __exit fsl_spi_exit(void) |
ccf06998 | 848 | { |
18d306d1 | 849 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 850 | legacy_driver_unregister(); |
ccf06998 | 851 | } |
b36ece83 | 852 | module_exit(fsl_spi_exit); |
ccf06998 KG |
853 | |
854 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 855 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 856 | MODULE_LICENSE("GPL"); |