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84d04318 FS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | ||
3 | /* | |
4 | * Freescale QuadSPI driver. | |
5 | * | |
6 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | |
7 | * Copyright (C) 2018 Bootlin | |
8 | * Copyright (C) 2018 exceet electronics GmbH | |
9 | * Copyright (C) 2018 Kontron Electronics GmbH | |
10 | * | |
11 | * Transition to SPI MEM interface: | |
12 | * Authors: | |
c55d0e8c | 13 | * Boris Brezillon <bbrezillon@kernel.org> |
84d04318 FS |
14 | * Frieder Schrempf <frieder.schrempf@kontron.de> |
15 | * Yogesh Gaur <yogeshnarayan.gaur@nxp.com> | |
16 | * Suresh Gupta <suresh.gupta@nxp.com> | |
17 | * | |
3e84cdd4 | 18 | * Based on the original fsl-quadspi.c SPI NOR driver: |
84d04318 FS |
19 | * Author: Freescale Semiconductor, Inc. |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/bitops.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/completion.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/iopoll.h> | |
32 | #include <linux/jiffies.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/mutex.h> | |
36 | #include <linux/of.h> | |
84d04318 FS |
37 | #include <linux/platform_device.h> |
38 | #include <linux/pm_qos.h> | |
39 | #include <linux/sizes.h> | |
40 | ||
41 | #include <linux/spi/spi.h> | |
42 | #include <linux/spi/spi-mem.h> | |
43 | ||
44 | /* | |
45 | * The driver only uses one single LUT entry, that is updated on | |
46 | * each call of exec_op(). Index 0 is preset at boot with a basic | |
47 | * read operation, so let's use the last entry (15). | |
48 | */ | |
49 | #define SEQID_LUT 15 | |
50 | ||
51 | /* Registers used by the driver */ | |
52 | #define QUADSPI_MCR 0x00 | |
53 | #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) | |
54 | #define QUADSPI_MCR_MDIS_MASK BIT(14) | |
55 | #define QUADSPI_MCR_CLR_TXF_MASK BIT(11) | |
56 | #define QUADSPI_MCR_CLR_RXF_MASK BIT(10) | |
57 | #define QUADSPI_MCR_DDR_EN_MASK BIT(7) | |
58 | #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) | |
59 | #define QUADSPI_MCR_SWRSTHD_MASK BIT(1) | |
60 | #define QUADSPI_MCR_SWRSTSD_MASK BIT(0) | |
61 | ||
62 | #define QUADSPI_IPCR 0x08 | |
63 | #define QUADSPI_IPCR_SEQID(x) ((x) << 24) | |
64 | ||
f6910679 FS |
65 | #define QUADSPI_FLSHCR 0x0c |
66 | #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) | |
67 | #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) | |
68 | #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) | |
69 | ||
16c3e058 KS |
70 | #define QUADSPI_BUF0CR 0x10 |
71 | #define QUADSPI_BUF1CR 0x14 | |
72 | #define QUADSPI_BUF2CR 0x18 | |
73 | #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe | |
74 | ||
84d04318 FS |
75 | #define QUADSPI_BUF3CR 0x1c |
76 | #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) | |
77 | #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) | |
78 | #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) | |
79 | ||
80 | #define QUADSPI_BFGENCR 0x20 | |
81 | #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) | |
82 | ||
83 | #define QUADSPI_BUF0IND 0x30 | |
84 | #define QUADSPI_BUF1IND 0x34 | |
85 | #define QUADSPI_BUF2IND 0x38 | |
86 | #define QUADSPI_SFAR 0x100 | |
87 | ||
88 | #define QUADSPI_SMPR 0x108 | |
89 | #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16) | |
90 | #define QUADSPI_SMPR_FSDLY_MASK BIT(6) | |
91 | #define QUADSPI_SMPR_FSPHS_MASK BIT(5) | |
92 | #define QUADSPI_SMPR_HSENA_MASK BIT(0) | |
93 | ||
94 | #define QUADSPI_RBCT 0x110 | |
95 | #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0) | |
96 | #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) | |
97 | ||
98 | #define QUADSPI_TBDR 0x154 | |
99 | ||
100 | #define QUADSPI_SR 0x15c | |
101 | #define QUADSPI_SR_IP_ACC_MASK BIT(1) | |
102 | #define QUADSPI_SR_AHB_ACC_MASK BIT(2) | |
103 | ||
104 | #define QUADSPI_FR 0x160 | |
105 | #define QUADSPI_FR_TFF_MASK BIT(0) | |
106 | ||
f6910679 FS |
107 | #define QUADSPI_RSER 0x164 |
108 | #define QUADSPI_RSER_TFIE BIT(0) | |
109 | ||
84d04318 FS |
110 | #define QUADSPI_SPTRCLR 0x16c |
111 | #define QUADSPI_SPTRCLR_IPPTRC BIT(8) | |
112 | #define QUADSPI_SPTRCLR_BFPTRC BIT(0) | |
113 | ||
114 | #define QUADSPI_SFA1AD 0x180 | |
115 | #define QUADSPI_SFA2AD 0x184 | |
116 | #define QUADSPI_SFB1AD 0x188 | |
117 | #define QUADSPI_SFB2AD 0x18c | |
118 | #define QUADSPI_RBDR(x) (0x200 + ((x) * 4)) | |
119 | ||
120 | #define QUADSPI_LUTKEY 0x300 | |
121 | #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0 | |
122 | ||
123 | #define QUADSPI_LCKCR 0x304 | |
124 | #define QUADSPI_LCKER_LOCK BIT(0) | |
125 | #define QUADSPI_LCKER_UNLOCK BIT(1) | |
126 | ||
84d04318 FS |
127 | #define QUADSPI_LUT_BASE 0x310 |
128 | #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) | |
129 | #define QUADSPI_LUT_REG(idx) \ | |
130 | (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4) | |
131 | ||
132 | /* Instruction set for the LUT register */ | |
133 | #define LUT_STOP 0 | |
134 | #define LUT_CMD 1 | |
135 | #define LUT_ADDR 2 | |
136 | #define LUT_DUMMY 3 | |
137 | #define LUT_MODE 4 | |
138 | #define LUT_MODE2 5 | |
139 | #define LUT_MODE4 6 | |
140 | #define LUT_FSL_READ 7 | |
141 | #define LUT_FSL_WRITE 8 | |
142 | #define LUT_JMP_ON_CS 9 | |
143 | #define LUT_ADDR_DDR 10 | |
144 | #define LUT_MODE_DDR 11 | |
145 | #define LUT_MODE2_DDR 12 | |
146 | #define LUT_MODE4_DDR 13 | |
147 | #define LUT_FSL_READ_DDR 14 | |
148 | #define LUT_FSL_WRITE_DDR 15 | |
149 | #define LUT_DATA_LEARN 16 | |
150 | ||
151 | /* | |
152 | * The PAD definitions for LUT register. | |
153 | * | |
154 | * The pad stands for the number of IO lines [0:3]. | |
155 | * For example, the quad read needs four IO lines, | |
156 | * so you should use LUT_PAD(4). | |
157 | */ | |
158 | #define LUT_PAD(x) (fls(x) - 1) | |
159 | ||
160 | /* | |
161 | * Macro for constructing the LUT entries with the following | |
162 | * register layout: | |
163 | * | |
164 | * --------------------------------------------------- | |
165 | * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | | |
166 | * --------------------------------------------------- | |
167 | */ | |
168 | #define LUT_DEF(idx, ins, pad, opr) \ | |
169 | ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16)) | |
170 | ||
171 | /* Controller needs driver to swap endianness */ | |
172 | #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) | |
173 | ||
174 | /* Controller needs 4x internal clock */ | |
175 | #define QUADSPI_QUIRK_4X_INT_CLK BIT(1) | |
176 | ||
177 | /* | |
178 | * TKT253890, the controller needs the driver to fill the txfifo with | |
179 | * 16 bytes at least to trigger a data transfer, even though the extra | |
180 | * data won't be transferred. | |
181 | */ | |
182 | #define QUADSPI_QUIRK_TKT253890 BIT(2) | |
183 | ||
184 | /* TKT245618, the controller cannot wake up from wait mode */ | |
185 | #define QUADSPI_QUIRK_TKT245618 BIT(3) | |
186 | ||
187 | /* | |
188 | * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) | |
189 | * internally. No need to add it when setting SFXXAD and SFAR registers | |
190 | */ | |
191 | #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) | |
192 | ||
f6910679 FS |
193 | /* |
194 | * Controller uses TDH bits in register QUADSPI_FLSHCR. | |
195 | * They need to be set in accordance with the DDR/SDR mode. | |
196 | */ | |
197 | #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) | |
198 | ||
84d04318 FS |
199 | struct fsl_qspi_devtype_data { |
200 | unsigned int rxfifo; | |
201 | unsigned int txfifo; | |
16c3e058 | 202 | int invalid_mstrid; |
84d04318 FS |
203 | unsigned int ahb_buf_size; |
204 | unsigned int quirks; | |
205 | bool little_endian; | |
206 | }; | |
207 | ||
208 | static const struct fsl_qspi_devtype_data vybrid_data = { | |
209 | .rxfifo = SZ_128, | |
210 | .txfifo = SZ_64, | |
16c3e058 | 211 | .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
84d04318 FS |
212 | .ahb_buf_size = SZ_1K, |
213 | .quirks = QUADSPI_QUIRK_SWAP_ENDIAN, | |
214 | .little_endian = true, | |
215 | }; | |
216 | ||
217 | static const struct fsl_qspi_devtype_data imx6sx_data = { | |
218 | .rxfifo = SZ_128, | |
219 | .txfifo = SZ_512, | |
16c3e058 | 220 | .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
84d04318 FS |
221 | .ahb_buf_size = SZ_1K, |
222 | .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, | |
223 | .little_endian = true, | |
224 | }; | |
225 | ||
226 | static const struct fsl_qspi_devtype_data imx7d_data = { | |
d6b197a1 | 227 | .rxfifo = SZ_128, |
84d04318 | 228 | .txfifo = SZ_512, |
16c3e058 | 229 | .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
84d04318 | 230 | .ahb_buf_size = SZ_1K, |
f6910679 FS |
231 | .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
232 | QUADSPI_QUIRK_USE_TDH_SETTING, | |
84d04318 FS |
233 | .little_endian = true, |
234 | }; | |
235 | ||
236 | static const struct fsl_qspi_devtype_data imx6ul_data = { | |
237 | .rxfifo = SZ_128, | |
238 | .txfifo = SZ_512, | |
16c3e058 | 239 | .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
84d04318 | 240 | .ahb_buf_size = SZ_1K, |
f6910679 FS |
241 | .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
242 | QUADSPI_QUIRK_USE_TDH_SETTING, | |
84d04318 FS |
243 | .little_endian = true, |
244 | }; | |
245 | ||
246 | static const struct fsl_qspi_devtype_data ls1021a_data = { | |
247 | .rxfifo = SZ_128, | |
248 | .txfifo = SZ_64, | |
16c3e058 | 249 | .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
84d04318 FS |
250 | .ahb_buf_size = SZ_1K, |
251 | .quirks = 0, | |
252 | .little_endian = false, | |
253 | }; | |
254 | ||
255 | static const struct fsl_qspi_devtype_data ls2080a_data = { | |
256 | .rxfifo = SZ_128, | |
257 | .txfifo = SZ_64, | |
258 | .ahb_buf_size = SZ_1K, | |
16c3e058 | 259 | .invalid_mstrid = 0x0, |
84d04318 FS |
260 | .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, |
261 | .little_endian = true, | |
262 | }; | |
263 | ||
264 | struct fsl_qspi { | |
265 | void __iomem *iobase; | |
266 | void __iomem *ahb_addr; | |
267 | u32 memmap_phy; | |
268 | struct clk *clk, *clk_en; | |
269 | struct device *dev; | |
270 | struct completion c; | |
271 | const struct fsl_qspi_devtype_data *devtype_data; | |
272 | struct mutex lock; | |
273 | struct pm_qos_request pm_qos_req; | |
274 | int selected; | |
275 | }; | |
276 | ||
277 | static inline int needs_swap_endian(struct fsl_qspi *q) | |
278 | { | |
279 | return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; | |
280 | } | |
281 | ||
282 | static inline int needs_4x_clock(struct fsl_qspi *q) | |
283 | { | |
284 | return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; | |
285 | } | |
286 | ||
287 | static inline int needs_fill_txfifo(struct fsl_qspi *q) | |
288 | { | |
289 | return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; | |
290 | } | |
291 | ||
292 | static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) | |
293 | { | |
294 | return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; | |
295 | } | |
296 | ||
297 | static inline int needs_amba_base_offset(struct fsl_qspi *q) | |
298 | { | |
299 | return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); | |
300 | } | |
301 | ||
f6910679 FS |
302 | static inline int needs_tdh_setting(struct fsl_qspi *q) |
303 | { | |
304 | return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; | |
305 | } | |
306 | ||
84d04318 FS |
307 | /* |
308 | * An IC bug makes it necessary to rearrange the 32-bit data. | |
309 | * Later chips, such as IMX6SLX, have fixed this bug. | |
310 | */ | |
311 | static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) | |
312 | { | |
313 | return needs_swap_endian(q) ? __swab32(a) : a; | |
314 | } | |
315 | ||
316 | /* | |
317 | * R/W functions for big- or little-endian registers: | |
318 | * The QSPI controller's endianness is independent of | |
319 | * the CPU core's endianness. So far, although the CPU | |
320 | * core is little-endian the QSPI controller can use | |
321 | * big-endian or little-endian. | |
322 | */ | |
323 | static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) | |
324 | { | |
325 | if (q->devtype_data->little_endian) | |
326 | iowrite32(val, addr); | |
327 | else | |
328 | iowrite32be(val, addr); | |
329 | } | |
330 | ||
331 | static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) | |
332 | { | |
333 | if (q->devtype_data->little_endian) | |
334 | return ioread32(addr); | |
335 | ||
336 | return ioread32be(addr); | |
337 | } | |
338 | ||
339 | static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) | |
340 | { | |
341 | struct fsl_qspi *q = dev_id; | |
342 | u32 reg; | |
343 | ||
344 | /* clear interrupt */ | |
345 | reg = qspi_readl(q, q->iobase + QUADSPI_FR); | |
346 | qspi_writel(q, reg, q->iobase + QUADSPI_FR); | |
347 | ||
348 | if (reg & QUADSPI_FR_TFF_MASK) | |
349 | complete(&q->c); | |
350 | ||
351 | dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg); | |
352 | return IRQ_HANDLED; | |
353 | } | |
354 | ||
355 | static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) | |
356 | { | |
357 | switch (width) { | |
358 | case 1: | |
359 | case 2: | |
360 | case 4: | |
361 | return 0; | |
362 | } | |
363 | ||
364 | return -ENOTSUPP; | |
365 | } | |
366 | ||
367 | static bool fsl_qspi_supports_op(struct spi_mem *mem, | |
368 | const struct spi_mem_op *op) | |
369 | { | |
ec6a7952 | 370 | struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); |
84d04318 FS |
371 | int ret; |
372 | ||
373 | ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth); | |
374 | ||
375 | if (op->addr.nbytes) | |
376 | ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth); | |
377 | ||
378 | if (op->dummy.nbytes) | |
379 | ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth); | |
380 | ||
381 | if (op->data.nbytes) | |
382 | ret |= fsl_qspi_check_buswidth(q, op->data.buswidth); | |
383 | ||
384 | if (ret) | |
385 | return false; | |
386 | ||
387 | /* | |
388 | * The number of instructions needed for the op, needs | |
389 | * to fit into a single LUT entry. | |
390 | */ | |
391 | if (op->addr.nbytes + | |
392 | (op->dummy.nbytes ? 1:0) + | |
393 | (op->data.nbytes ? 1:0) > 6) | |
394 | return false; | |
395 | ||
396 | /* Max 64 dummy clock cycles supported */ | |
397 | if (op->dummy.nbytes && | |
398 | (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) | |
399 | return false; | |
400 | ||
401 | /* Max data length, check controller limits and alignment */ | |
402 | if (op->data.dir == SPI_MEM_DATA_IN && | |
403 | (op->data.nbytes > q->devtype_data->ahb_buf_size || | |
404 | (op->data.nbytes > q->devtype_data->rxfifo - 4 && | |
405 | !IS_ALIGNED(op->data.nbytes, 8)))) | |
406 | return false; | |
407 | ||
408 | if (op->data.dir == SPI_MEM_DATA_OUT && | |
409 | op->data.nbytes > q->devtype_data->txfifo) | |
410 | return false; | |
411 | ||
b0177aca | 412 | return spi_mem_default_supports_op(mem, op); |
84d04318 FS |
413 | } |
414 | ||
415 | static void fsl_qspi_prepare_lut(struct fsl_qspi *q, | |
416 | const struct spi_mem_op *op) | |
417 | { | |
418 | void __iomem *base = q->iobase; | |
419 | u32 lutval[4] = {}; | |
420 | int lutidx = 1, i; | |
421 | ||
422 | lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), | |
423 | op->cmd.opcode); | |
424 | ||
425 | /* | |
426 | * For some unknown reason, using LUT_ADDR doesn't work in some | |
427 | * cases (at least with only one byte long addresses), so | |
428 | * let's use LUT_MODE to write the address bytes one by one | |
429 | */ | |
430 | for (i = 0; i < op->addr.nbytes; i++) { | |
431 | u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); | |
432 | ||
433 | lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE, | |
434 | LUT_PAD(op->addr.buswidth), | |
435 | addrbyte); | |
436 | lutidx++; | |
437 | } | |
438 | ||
439 | if (op->dummy.nbytes) { | |
440 | lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, | |
441 | LUT_PAD(op->dummy.buswidth), | |
442 | op->dummy.nbytes * 8 / | |
443 | op->dummy.buswidth); | |
444 | lutidx++; | |
445 | } | |
446 | ||
447 | if (op->data.nbytes) { | |
448 | lutval[lutidx / 2] |= LUT_DEF(lutidx, | |
449 | op->data.dir == SPI_MEM_DATA_IN ? | |
450 | LUT_FSL_READ : LUT_FSL_WRITE, | |
451 | LUT_PAD(op->data.buswidth), | |
452 | 0); | |
453 | lutidx++; | |
454 | } | |
455 | ||
456 | lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); | |
457 | ||
458 | /* unlock LUT */ | |
459 | qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); | |
460 | qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); | |
461 | ||
462 | /* fill LUT */ | |
463 | for (i = 0; i < ARRAY_SIZE(lutval); i++) | |
464 | qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); | |
465 | ||
466 | /* lock LUT */ | |
467 | qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); | |
468 | qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); | |
469 | } | |
470 | ||
471 | static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) | |
472 | { | |
473 | int ret; | |
474 | ||
475 | ret = clk_prepare_enable(q->clk_en); | |
476 | if (ret) | |
477 | return ret; | |
478 | ||
479 | ret = clk_prepare_enable(q->clk); | |
480 | if (ret) { | |
481 | clk_disable_unprepare(q->clk_en); | |
482 | return ret; | |
483 | } | |
484 | ||
485 | if (needs_wakeup_wait_mode(q)) | |
c4c632e9 | 486 | cpu_latency_qos_add_request(&q->pm_qos_req, 0); |
84d04318 FS |
487 | |
488 | return 0; | |
489 | } | |
490 | ||
491 | static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) | |
492 | { | |
493 | if (needs_wakeup_wait_mode(q)) | |
c4c632e9 | 494 | cpu_latency_qos_remove_request(&q->pm_qos_req); |
84d04318 FS |
495 | |
496 | clk_disable_unprepare(q->clk); | |
497 | clk_disable_unprepare(q->clk_en); | |
498 | } | |
499 | ||
500 | /* | |
501 | * If we have changed the content of the flash by writing or erasing, or if we | |
502 | * read from flash with a different offset into the page buffer, we need to | |
503 | * invalidate the AHB buffer. If we do not do so, we may read out the wrong | |
504 | * data. The spec tells us reset the AHB domain and Serial Flash domain at | |
505 | * the same time. | |
506 | */ | |
507 | static void fsl_qspi_invalidate(struct fsl_qspi *q) | |
508 | { | |
509 | u32 reg; | |
510 | ||
511 | reg = qspi_readl(q, q->iobase + QUADSPI_MCR); | |
512 | reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; | |
513 | qspi_writel(q, reg, q->iobase + QUADSPI_MCR); | |
514 | ||
515 | /* | |
516 | * The minimum delay : 1 AHB + 2 SFCK clocks. | |
517 | * Delay 1 us is enough. | |
518 | */ | |
519 | udelay(1); | |
520 | ||
521 | reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); | |
522 | qspi_writel(q, reg, q->iobase + QUADSPI_MCR); | |
523 | } | |
524 | ||
525 | static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi) | |
526 | { | |
527 | unsigned long rate = spi->max_speed_hz; | |
528 | int ret; | |
529 | ||
9e264f3f | 530 | if (q->selected == spi_get_chipselect(spi, 0)) |
84d04318 FS |
531 | return; |
532 | ||
533 | if (needs_4x_clock(q)) | |
534 | rate *= 4; | |
535 | ||
536 | fsl_qspi_clk_disable_unprep(q); | |
537 | ||
538 | ret = clk_set_rate(q->clk, rate); | |
539 | if (ret) | |
540 | return; | |
541 | ||
542 | ret = fsl_qspi_clk_prep_enable(q); | |
543 | if (ret) | |
544 | return; | |
545 | ||
9e264f3f | 546 | q->selected = spi_get_chipselect(spi, 0); |
84d04318 FS |
547 | |
548 | fsl_qspi_invalidate(q); | |
549 | } | |
550 | ||
551 | static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) | |
552 | { | |
553 | memcpy_fromio(op->data.buf.in, | |
554 | q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, | |
555 | op->data.nbytes); | |
556 | } | |
557 | ||
558 | static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, | |
559 | const struct spi_mem_op *op) | |
560 | { | |
561 | void __iomem *base = q->iobase; | |
562 | int i; | |
563 | u32 val; | |
564 | ||
565 | for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { | |
566 | memcpy(&val, op->data.buf.out + i, 4); | |
567 | val = fsl_qspi_endian_xchg(q, val); | |
568 | qspi_writel(q, val, base + QUADSPI_TBDR); | |
569 | } | |
570 | ||
571 | if (i < op->data.nbytes) { | |
572 | memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); | |
573 | val = fsl_qspi_endian_xchg(q, val); | |
574 | qspi_writel(q, val, base + QUADSPI_TBDR); | |
575 | } | |
576 | ||
577 | if (needs_fill_txfifo(q)) { | |
578 | for (i = op->data.nbytes; i < 16; i += 4) | |
579 | qspi_writel(q, 0, base + QUADSPI_TBDR); | |
580 | } | |
581 | } | |
582 | ||
583 | static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, | |
584 | const struct spi_mem_op *op) | |
585 | { | |
586 | void __iomem *base = q->iobase; | |
587 | int i; | |
588 | u8 *buf = op->data.buf.in; | |
589 | u32 val; | |
590 | ||
591 | for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { | |
592 | val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); | |
593 | val = fsl_qspi_endian_xchg(q, val); | |
594 | memcpy(buf + i, &val, 4); | |
595 | } | |
596 | ||
597 | if (i < op->data.nbytes) { | |
598 | val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); | |
599 | val = fsl_qspi_endian_xchg(q, val); | |
600 | memcpy(buf + i, &val, op->data.nbytes - i); | |
601 | } | |
602 | } | |
603 | ||
604 | static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) | |
605 | { | |
606 | void __iomem *base = q->iobase; | |
607 | int err = 0; | |
608 | ||
609 | init_completion(&q->c); | |
610 | ||
611 | /* | |
612 | * Always start the sequence at the same index since we update | |
613 | * the LUT at each exec_op() call. And also specify the DATA | |
614 | * length, since it's has not been specified in the LUT. | |
615 | */ | |
616 | qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT), | |
617 | base + QUADSPI_IPCR); | |
618 | ||
619 | /* Wait for the interrupt. */ | |
620 | if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) | |
621 | err = -ETIMEDOUT; | |
622 | ||
623 | if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) | |
624 | fsl_qspi_read_rxfifo(q, op); | |
625 | ||
626 | return err; | |
627 | } | |
628 | ||
629 | static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, | |
630 | u32 mask, u32 delay_us, u32 timeout_us) | |
631 | { | |
632 | u32 reg; | |
633 | ||
634 | if (!q->devtype_data->little_endian) | |
635 | mask = (u32)cpu_to_be32(mask); | |
636 | ||
637 | return readl_poll_timeout(base, reg, !(reg & mask), delay_us, | |
638 | timeout_us); | |
639 | } | |
640 | ||
641 | static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) | |
642 | { | |
ec6a7952 | 643 | struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); |
84d04318 FS |
644 | void __iomem *base = q->iobase; |
645 | u32 addr_offset = 0; | |
646 | int err = 0; | |
16c3e058 | 647 | int invalid_mstrid = q->devtype_data->invalid_mstrid; |
84d04318 FS |
648 | |
649 | mutex_lock(&q->lock); | |
650 | ||
651 | /* wait for the controller being ready */ | |
652 | fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | | |
653 | QUADSPI_SR_AHB_ACC_MASK), 10, 1000); | |
654 | ||
655 | fsl_qspi_select_mem(q, mem->spi); | |
656 | ||
657 | if (needs_amba_base_offset(q)) | |
658 | addr_offset = q->memmap_phy; | |
659 | ||
660 | qspi_writel(q, | |
661 | q->selected * q->devtype_data->ahb_buf_size + addr_offset, | |
662 | base + QUADSPI_SFAR); | |
663 | ||
664 | qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | | |
665 | QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK, | |
666 | base + QUADSPI_MCR); | |
667 | ||
668 | qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, | |
669 | base + QUADSPI_SPTRCLR); | |
670 | ||
16c3e058 KS |
671 | qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR); |
672 | qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR); | |
673 | qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR); | |
674 | ||
84d04318 FS |
675 | fsl_qspi_prepare_lut(q, op); |
676 | ||
677 | /* | |
678 | * If we have large chunks of data, we read them through the AHB bus | |
679 | * by accessing the mapped memory. In all other cases we use | |
680 | * IP commands to access the flash. | |
681 | */ | |
682 | if (op->data.nbytes > (q->devtype_data->rxfifo - 4) && | |
683 | op->data.dir == SPI_MEM_DATA_IN) { | |
684 | fsl_qspi_read_ahb(q, op); | |
685 | } else { | |
686 | qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | | |
687 | QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); | |
688 | ||
689 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) | |
690 | fsl_qspi_fill_txfifo(q, op); | |
691 | ||
692 | err = fsl_qspi_do_op(q, op); | |
693 | } | |
694 | ||
695 | /* Invalidate the data in the AHB buffer. */ | |
696 | fsl_qspi_invalidate(q); | |
697 | ||
698 | mutex_unlock(&q->lock); | |
699 | ||
700 | return err; | |
701 | } | |
702 | ||
703 | static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) | |
704 | { | |
ec6a7952 | 705 | struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); |
84d04318 FS |
706 | |
707 | if (op->data.dir == SPI_MEM_DATA_OUT) { | |
708 | if (op->data.nbytes > q->devtype_data->txfifo) | |
709 | op->data.nbytes = q->devtype_data->txfifo; | |
710 | } else { | |
711 | if (op->data.nbytes > q->devtype_data->ahb_buf_size) | |
712 | op->data.nbytes = q->devtype_data->ahb_buf_size; | |
713 | else if (op->data.nbytes > (q->devtype_data->rxfifo - 4)) | |
714 | op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | static int fsl_qspi_default_setup(struct fsl_qspi *q) | |
721 | { | |
722 | void __iomem *base = q->iobase; | |
723 | u32 reg, addr_offset = 0; | |
724 | int ret; | |
725 | ||
726 | /* disable and unprepare clock to avoid glitch pass to controller */ | |
727 | fsl_qspi_clk_disable_unprep(q); | |
728 | ||
729 | /* the default frequency, we will change it later if necessary. */ | |
730 | ret = clk_set_rate(q->clk, 66000000); | |
731 | if (ret) | |
732 | return ret; | |
733 | ||
734 | ret = fsl_qspi_clk_prep_enable(q); | |
735 | if (ret) | |
736 | return ret; | |
737 | ||
738 | /* Reset the module */ | |
739 | qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, | |
740 | base + QUADSPI_MCR); | |
741 | udelay(1); | |
742 | ||
743 | /* Disable the module */ | |
744 | qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, | |
745 | base + QUADSPI_MCR); | |
746 | ||
f6910679 FS |
747 | /* |
748 | * Previous boot stages (BootROM, bootloader) might have used DDR | |
749 | * mode and did not clear the TDH bits. As we currently use SDR mode | |
750 | * only, clear the TDH bits if necessary. | |
751 | */ | |
752 | if (needs_tdh_setting(q)) | |
753 | qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & | |
754 | ~QUADSPI_FLSHCR_TDH_MASK, | |
755 | base + QUADSPI_FLSHCR); | |
756 | ||
84d04318 FS |
757 | reg = qspi_readl(q, base + QUADSPI_SMPR); |
758 | qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK | |
759 | | QUADSPI_SMPR_FSPHS_MASK | |
760 | | QUADSPI_SMPR_HSENA_MASK | |
761 | | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); | |
762 | ||
763 | /* We only use the buffer3 for AHB read */ | |
764 | qspi_writel(q, 0, base + QUADSPI_BUF0IND); | |
765 | qspi_writel(q, 0, base + QUADSPI_BUF1IND); | |
766 | qspi_writel(q, 0, base + QUADSPI_BUF2IND); | |
767 | ||
768 | qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT), | |
769 | q->iobase + QUADSPI_BFGENCR); | |
770 | qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); | |
771 | qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | | |
772 | QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8), | |
773 | base + QUADSPI_BUF3CR); | |
774 | ||
775 | if (needs_amba_base_offset(q)) | |
776 | addr_offset = q->memmap_phy; | |
777 | ||
778 | /* | |
779 | * In HW there can be a maximum of four chips on two buses with | |
780 | * two chip selects on each bus. We use four chip selects in SW | |
781 | * to differentiate between the four chips. | |
782 | * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, | |
783 | * SFB2AD accordingly. | |
784 | */ | |
785 | qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, | |
786 | base + QUADSPI_SFA1AD); | |
787 | qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, | |
788 | base + QUADSPI_SFA2AD); | |
789 | qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, | |
790 | base + QUADSPI_SFB1AD); | |
791 | qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, | |
792 | base + QUADSPI_SFB2AD); | |
793 | ||
794 | q->selected = -1; | |
795 | ||
796 | /* Enable the module */ | |
797 | qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, | |
798 | base + QUADSPI_MCR); | |
799 | ||
800 | /* clear all interrupt status */ | |
801 | qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR); | |
802 | ||
803 | /* enable the interrupt */ | |
804 | qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static const char *fsl_qspi_get_name(struct spi_mem *mem) | |
810 | { | |
ec6a7952 | 811 | struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); |
84d04318 FS |
812 | struct device *dev = &mem->spi->dev; |
813 | const char *name; | |
814 | ||
815 | /* | |
816 | * In order to keep mtdparts compatible with the old MTD driver at | |
817 | * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the | |
818 | * platform_device of the controller. | |
819 | */ | |
820 | if (of_get_available_child_count(q->dev->of_node) == 1) | |
821 | return dev_name(q->dev); | |
822 | ||
823 | name = devm_kasprintf(dev, GFP_KERNEL, | |
824 | "%s-%d", dev_name(q->dev), | |
9e264f3f | 825 | spi_get_chipselect(mem->spi, 0)); |
84d04318 FS |
826 | |
827 | if (!name) { | |
828 | dev_err(dev, "failed to get memory for custom flash name\n"); | |
829 | return ERR_PTR(-ENOMEM); | |
830 | } | |
831 | ||
832 | return name; | |
833 | } | |
834 | ||
835 | static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { | |
836 | .adjust_op_size = fsl_qspi_adjust_op_size, | |
837 | .supports_op = fsl_qspi_supports_op, | |
838 | .exec_op = fsl_qspi_exec_op, | |
839 | .get_name = fsl_qspi_get_name, | |
840 | }; | |
841 | ||
842 | static int fsl_qspi_probe(struct platform_device *pdev) | |
843 | { | |
844 | struct spi_controller *ctlr; | |
845 | struct device *dev = &pdev->dev; | |
846 | struct device_node *np = dev->of_node; | |
847 | struct resource *res; | |
848 | struct fsl_qspi *q; | |
849 | int ret; | |
850 | ||
ec6a7952 | 851 | ctlr = spi_alloc_host(&pdev->dev, sizeof(*q)); |
84d04318 FS |
852 | if (!ctlr) |
853 | return -ENOMEM; | |
854 | ||
855 | ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | | |
856 | SPI_TX_DUAL | SPI_TX_QUAD; | |
857 | ||
858 | q = spi_controller_get_devdata(ctlr); | |
859 | q->dev = dev; | |
860 | q->devtype_data = of_device_get_match_data(dev); | |
861 | if (!q->devtype_data) { | |
862 | ret = -ENODEV; | |
863 | goto err_put_ctrl; | |
864 | } | |
865 | ||
866 | platform_set_drvdata(pdev, q); | |
867 | ||
868 | /* find the resources */ | |
fc13b5a2 | 869 | q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI"); |
84d04318 FS |
870 | if (IS_ERR(q->iobase)) { |
871 | ret = PTR_ERR(q->iobase); | |
872 | goto err_put_ctrl; | |
873 | } | |
874 | ||
875 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
876 | "QuadSPI-memory"); | |
a2b331ac YY |
877 | if (!res) { |
878 | ret = -EINVAL; | |
879 | goto err_put_ctrl; | |
880 | } | |
858e26a5 AK |
881 | q->memmap_phy = res->start; |
882 | /* Since there are 4 cs, map size required is 4 times ahb_buf_size */ | |
883 | q->ahb_addr = devm_ioremap(dev, q->memmap_phy, | |
884 | (q->devtype_data->ahb_buf_size * 4)); | |
f58dcab6 WY |
885 | if (!q->ahb_addr) { |
886 | ret = -ENOMEM; | |
84d04318 FS |
887 | goto err_put_ctrl; |
888 | } | |
889 | ||
84d04318 FS |
890 | /* find the clocks */ |
891 | q->clk_en = devm_clk_get(dev, "qspi_en"); | |
892 | if (IS_ERR(q->clk_en)) { | |
893 | ret = PTR_ERR(q->clk_en); | |
894 | goto err_put_ctrl; | |
895 | } | |
896 | ||
897 | q->clk = devm_clk_get(dev, "qspi"); | |
898 | if (IS_ERR(q->clk)) { | |
899 | ret = PTR_ERR(q->clk); | |
900 | goto err_put_ctrl; | |
901 | } | |
902 | ||
903 | ret = fsl_qspi_clk_prep_enable(q); | |
904 | if (ret) { | |
905 | dev_err(dev, "can not enable the clock\n"); | |
906 | goto err_put_ctrl; | |
907 | } | |
908 | ||
909 | /* find the irq */ | |
910 | ret = platform_get_irq(pdev, 0); | |
6b8ac10e | 911 | if (ret < 0) |
84d04318 | 912 | goto err_disable_clk; |
84d04318 FS |
913 | |
914 | ret = devm_request_irq(dev, ret, | |
915 | fsl_qspi_irq_handler, 0, pdev->name, q); | |
916 | if (ret) { | |
917 | dev_err(dev, "failed to request irq: %d\n", ret); | |
918 | goto err_disable_clk; | |
919 | } | |
920 | ||
921 | mutex_init(&q->lock); | |
922 | ||
923 | ctlr->bus_num = -1; | |
924 | ctlr->num_chipselect = 4; | |
925 | ctlr->mem_ops = &fsl_qspi_mem_ops; | |
926 | ||
927 | fsl_qspi_default_setup(q); | |
928 | ||
929 | ctlr->dev.of_node = np; | |
930 | ||
8fcb830a | 931 | ret = devm_spi_register_controller(dev, ctlr); |
84d04318 FS |
932 | if (ret) |
933 | goto err_destroy_mutex; | |
934 | ||
935 | return 0; | |
936 | ||
937 | err_destroy_mutex: | |
938 | mutex_destroy(&q->lock); | |
939 | ||
940 | err_disable_clk: | |
941 | fsl_qspi_clk_disable_unprep(q); | |
942 | ||
943 | err_put_ctrl: | |
944 | spi_controller_put(ctlr); | |
945 | ||
946 | dev_err(dev, "Freescale QuadSPI probe failed\n"); | |
947 | return ret; | |
948 | } | |
949 | ||
94f44509 | 950 | static void fsl_qspi_remove(struct platform_device *pdev) |
84d04318 FS |
951 | { |
952 | struct fsl_qspi *q = platform_get_drvdata(pdev); | |
953 | ||
954 | /* disable the hardware */ | |
955 | qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); | |
956 | qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); | |
957 | ||
958 | fsl_qspi_clk_disable_unprep(q); | |
959 | ||
960 | mutex_destroy(&q->lock); | |
84d04318 FS |
961 | } |
962 | ||
963 | static int fsl_qspi_suspend(struct device *dev) | |
964 | { | |
965 | return 0; | |
966 | } | |
967 | ||
968 | static int fsl_qspi_resume(struct device *dev) | |
969 | { | |
970 | struct fsl_qspi *q = dev_get_drvdata(dev); | |
971 | ||
972 | fsl_qspi_default_setup(q); | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | static const struct of_device_id fsl_qspi_dt_ids[] = { | |
978 | { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, }, | |
979 | { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, }, | |
980 | { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, }, | |
981 | { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, }, | |
982 | { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, }, | |
983 | { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, }, | |
984 | { /* sentinel */ } | |
985 | }; | |
986 | MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); | |
987 | ||
988 | static const struct dev_pm_ops fsl_qspi_pm_ops = { | |
989 | .suspend = fsl_qspi_suspend, | |
990 | .resume = fsl_qspi_resume, | |
991 | }; | |
992 | ||
993 | static struct platform_driver fsl_qspi_driver = { | |
994 | .driver = { | |
995 | .name = "fsl-quadspi", | |
996 | .of_match_table = fsl_qspi_dt_ids, | |
997 | .pm = &fsl_qspi_pm_ops, | |
998 | }, | |
999 | .probe = fsl_qspi_probe, | |
94f44509 | 1000 | .remove_new = fsl_qspi_remove, |
84d04318 FS |
1001 | }; |
1002 | module_platform_driver(fsl_qspi_driver); | |
1003 | ||
1004 | MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver"); | |
1005 | MODULE_AUTHOR("Freescale Semiconductor Inc."); | |
c55d0e8c | 1006 | MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); |
84d04318 FS |
1007 | MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); |
1008 | MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>"); | |
1009 | MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>"); | |
1010 | MODULE_LICENSE("GPL v2"); |