[linux-2.6-block.git] / drivers / spi / spi-fsl-lpspi.c

// SPDX-License-Identifier: GPL-2.0+
//
// Freescale i.MX7ULP LPSPI driver
//
// Copyright 2016 Freescale Semiconductor, Inc.
// Copyright 2018 NXP Semiconductors

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/types.h>

#define DRIVER_NAME "fsl_lpspi"

/* i.MX7ULP LPSPI registers */
#define IMX7ULP_VERID	0x0
#define IMX7ULP_PARAM	0x4
#define IMX7ULP_CR	0x10
#define IMX7ULP_SR	0x14
#define IMX7ULP_IER	0x18
#define IMX7ULP_DER	0x1c
#define IMX7ULP_CFGR0	0x20
#define IMX7ULP_CFGR1	0x24
#define IMX7ULP_DMR0	0x30
#define IMX7ULP_DMR1	0x34
#define IMX7ULP_CCR	0x40
#define IMX7ULP_FCR	0x58
#define IMX7ULP_FSR	0x5c
#define IMX7ULP_TCR	0x60
#define IMX7ULP_TDR	0x64
#define IMX7ULP_RSR	0x70
#define IMX7ULP_RDR	0x74

/* General control register field define */
#define CR_RRF		BIT(9)
#define CR_RTF		BIT(8)
#define CR_RST		BIT(1)
#define CR_MEN		BIT(0)
#define SR_MBF		BIT(24)
#define SR_TCF		BIT(10)
#define SR_FCF		BIT(9)
#define SR_RDF		BIT(1)
#define SR_TDF		BIT(0)
#define IER_TCIE	BIT(10)
#define IER_FCIE	BIT(9)
#define IER_RDIE	BIT(1)
#define IER_TDIE	BIT(0)
#define CFGR1_PCSCFG	BIT(27)
#define CFGR1_PINCFG	(BIT(24)|BIT(25))
#define CFGR1_PCSPOL	BIT(8)
#define CFGR1_NOSTALL	BIT(3)
#define CFGR1_MASTER	BIT(0)
#define FSR_RXCOUNT	(BIT(16)|BIT(17)|BIT(18))
#define RSR_RXEMPTY	BIT(1)
#define TCR_CPOL	BIT(31)
#define TCR_CPHA	BIT(30)
#define TCR_CONT	BIT(21)
#define TCR_CONTC	BIT(20)
#define TCR_RXMSK	BIT(19)
#define TCR_TXMSK	BIT(18)

static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};

struct lpspi_config {
	u8 bpw;
	u8 chip_select;
	u8 prescale;
	u16 mode;
	u32 speed_hz;
};

struct fsl_lpspi_data {
	struct device *dev;
	void __iomem *base;
	struct clk *clk;
	bool is_slave;

	void *rx_buf;
	const void *tx_buf;
	void (*tx)(struct fsl_lpspi_data *);
	void (*rx)(struct fsl_lpspi_data *);

	u32 remain;
	u8 watermark;
	u8 txfifosize;
	u8 rxfifosize;

	struct lpspi_config config;
	struct completion xfer_done;

	bool slave_aborted;
};

static const struct of_device_id fsl_lpspi_dt_ids[] = {
	{ .compatible = "fsl,imx7ulp-spi", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);

#define LPSPI_BUF_RX(type)						\
static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)	\
{									\
	unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);	\
									\
	if (fsl_lpspi->rx_buf) {					\
		*(type *)fsl_lpspi->rx_buf = val;			\
		fsl_lpspi->rx_buf += sizeof(type);                      \
	}								\
}

#define LPSPI_BUF_TX(type)						\
static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)	\
{									\
	type val = 0;							\
									\
	if (fsl_lpspi->tx_buf) {					\
		val = *(type *)fsl_lpspi->tx_buf;			\
		fsl_lpspi->tx_buf += sizeof(type);			\
	}								\
									\
	fsl_lpspi->remain -= sizeof(type);				\
	writel(val, fsl_lpspi->base + IMX7ULP_TDR);			\
}

LPSPI_BUF_RX(u8)
LPSPI_BUF_TX(u8)
LPSPI_BUF_RX(u16)
LPSPI_BUF_TX(u16)
LPSPI_BUF_RX(u32)
LPSPI_BUF_TX(u32)

static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
			      unsigned int enable)
{
	writel(enable, fsl_lpspi->base + IMX7ULP_IER);
}

static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);

	return clk_prepare_enable(fsl_lpspi->clk);
}

static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);

	clk_disable_unprepare(fsl_lpspi->clk);

	return 0;
}

static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
{
	u8 txfifo_cnt;
	u32 temp;

	txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;

	while (txfifo_cnt < fsl_lpspi->txfifosize) {
		if (!fsl_lpspi->remain)
			break;
		fsl_lpspi->tx(fsl_lpspi);
		txfifo_cnt++;
	}

	if (txfifo_cnt < fsl_lpspi->txfifosize) {
		if (!fsl_lpspi->is_slave) {
			temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
			temp &= ~TCR_CONTC;
			writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
		}

		fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
	} else
		fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
}

static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
{
	while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
		fsl_lpspi->rx(fsl_lpspi);
}

static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
			      bool is_first_xfer)
{
	u32 temp = 0;

	temp |= fsl_lpspi->config.bpw - 1;
	temp |= (fsl_lpspi->config.mode & 0x3) << 30;
	if (!fsl_lpspi->is_slave) {
		temp |= fsl_lpspi->config.prescale << 27;
		temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;

		/*
		 * Set TCR_CONT will keep SS asserted after current transfer.
		 * For the first transfer, clear TCR_CONTC to assert SS.
		 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
		 */
		temp |= TCR_CONT;
		if (is_first_xfer)
			temp &= ~TCR_CONTC;
		else
			temp |= TCR_CONTC;
	}
	writel(temp, fsl_lpspi->base + IMX7ULP_TCR);

	dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
}

static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
{
	u32 temp;

	temp = fsl_lpspi->watermark >> 1 | (fsl_lpspi->watermark >> 1) << 16;

	writel(temp, fsl_lpspi->base + IMX7ULP_FCR);

	dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
}

static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
{
	struct lpspi_config config = fsl_lpspi->config;
	unsigned int perclk_rate, scldiv;
	u8 prescale;

	perclk_rate = clk_get_rate(fsl_lpspi->clk);
	for (prescale = 0; prescale < 8; prescale++) {
		scldiv = perclk_rate /
			 (clkdivs[prescale] * config.speed_hz) - 2;
		if (scldiv < 256) {
			fsl_lpspi->config.prescale = prescale;
			break;
		}
	}

	if (prescale == 8 && scldiv >= 256)
		return -EINVAL;

	writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
					fsl_lpspi->base + IMX7ULP_CCR);

	dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
		perclk_rate, config.speed_hz, prescale, scldiv);

	return 0;
}

static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
{
	u32 temp;
	int ret;

	if (!fsl_lpspi->is_slave) {
		ret = fsl_lpspi_set_bitrate(fsl_lpspi);
		if (ret)
			return ret;
	}

	fsl_lpspi_set_watermark(fsl_lpspi);

	if (!fsl_lpspi->is_slave)
		temp = CFGR1_MASTER;
	else
		temp = CFGR1_PINCFG;
	if (fsl_lpspi->config.mode & SPI_CS_HIGH)
		temp |= CFGR1_PCSPOL;
	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);

	temp = readl(fsl_lpspi->base + IMX7ULP_CR);
	temp |= CR_RRF | CR_RTF | CR_MEN;
	writel(temp, fsl_lpspi->base + IMX7ULP_CR);

	return 0;
}

static void fsl_lpspi_setup_transfer(struct spi_device *spi,
				     struct spi_transfer *t)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(spi->controller);

	fsl_lpspi->config.mode = spi->mode;
	fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
	fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
	fsl_lpspi->config.chip_select = spi->chip_select;

	if (!fsl_lpspi->config.speed_hz)
		fsl_lpspi->config.speed_hz = spi->max_speed_hz;
	if (!fsl_lpspi->config.bpw)
		fsl_lpspi->config.bpw = spi->bits_per_word;

	/* Initialize the functions for transfer */
	if (fsl_lpspi->config.bpw <= 8) {
		fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
		fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
	} else if (fsl_lpspi->config.bpw <= 16) {
		fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
		fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
	} else {
		fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
		fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
	}

	if (t->len <= fsl_lpspi->txfifosize)
		fsl_lpspi->watermark = t->len;
	else
		fsl_lpspi->watermark = fsl_lpspi->txfifosize;

	fsl_lpspi_config(fsl_lpspi);
}

static int fsl_lpspi_slave_abort(struct spi_controller *controller)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);

	fsl_lpspi->slave_aborted = true;
	complete(&fsl_lpspi->xfer_done);
	return 0;
}

static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);

	if (fsl_lpspi->is_slave) {
		if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
			fsl_lpspi->slave_aborted) {
			dev_dbg(fsl_lpspi->dev, "interrupted\n");
			return -EINTR;
		}
	} else {
		if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
			dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
{
	u32 temp;

	/* Disable all interrupt */
	fsl_lpspi_intctrl(fsl_lpspi, 0);

	/* W1C for all flags in SR */
	temp = 0x3F << 8;
	writel(temp, fsl_lpspi->base + IMX7ULP_SR);

	/* Clear FIFO and disable module */
	temp = CR_RRF | CR_RTF;
	writel(temp, fsl_lpspi->base + IMX7ULP_CR);

	return 0;
}

static int fsl_lpspi_transfer_one(struct spi_controller *controller,
				  struct spi_device *spi,
				  struct spi_transfer *t)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);
	int ret;

	fsl_lpspi->tx_buf = t->tx_buf;
	fsl_lpspi->rx_buf = t->rx_buf;
	fsl_lpspi->remain = t->len;

	reinit_completion(&fsl_lpspi->xfer_done);
	fsl_lpspi->slave_aborted = false;

	fsl_lpspi_write_tx_fifo(fsl_lpspi);

	ret = fsl_lpspi_wait_for_completion(controller);
	if (ret)
		return ret;

	fsl_lpspi_reset(fsl_lpspi);

	return 0;
}

static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
				      struct spi_message *msg)
{
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);
	struct spi_device *spi = msg->spi;
	struct spi_transfer *xfer;
	bool is_first_xfer = true;
	int ret = 0;

	msg->status = 0;
	msg->actual_length = 0;

	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
		fsl_lpspi_setup_transfer(spi, xfer);
		fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);

		is_first_xfer = false;

		ret = fsl_lpspi_transfer_one(controller, spi, xfer);
		if (ret < 0)
			goto complete;

		msg->actual_length += xfer->len;
	}

complete:
	msg->status = ret;
	spi_finalize_current_message(controller);

	return ret;
}

static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
{
	u32 temp_SR, temp_IER;
	struct fsl_lpspi_data *fsl_lpspi = dev_id;

	temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
	fsl_lpspi_intctrl(fsl_lpspi, 0);
	temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);

	fsl_lpspi_read_rx_fifo(fsl_lpspi);

	if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
		fsl_lpspi_write_tx_fifo(fsl_lpspi);
		return IRQ_HANDLED;
	}

	if (temp_SR & SR_MBF ||
	    readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
		writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
		fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
		return IRQ_HANDLED;
	}

	if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
		writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
			complete(&fsl_lpspi->xfer_done);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int fsl_lpspi_probe(struct platform_device *pdev)
{
	struct fsl_lpspi_data *fsl_lpspi;
	struct spi_controller *controller;
	struct resource *res;
	int ret, irq;
	u32 temp;

	if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
		controller = spi_alloc_slave(&pdev->dev,
					sizeof(struct fsl_lpspi_data));
	else
		controller = spi_alloc_master(&pdev->dev,
					sizeof(struct fsl_lpspi_data));

	if (!controller)
		return -ENOMEM;

	platform_set_drvdata(pdev, controller);

	controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
	controller->bus_num = pdev->id;

	fsl_lpspi = spi_controller_get_devdata(controller);
	fsl_lpspi->dev = &pdev->dev;
	fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
						    "spi-slave");

	controller->transfer_one_message = fsl_lpspi_transfer_one_msg;
	controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
	controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
	controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
	controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
	controller->dev.of_node = pdev->dev.of_node;
	controller->bus_num = pdev->id;
	controller->slave_abort = fsl_lpspi_slave_abort;

	init_completion(&fsl_lpspi->xfer_done);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(fsl_lpspi->base)) {
		ret = PTR_ERR(fsl_lpspi->base);
		goto out_controller_put;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = irq;
		goto out_controller_put;
	}

	ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
			       dev_name(&pdev->dev), fsl_lpspi);
	if (ret) {
		dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
		goto out_controller_put;
	}

	fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(fsl_lpspi->clk)) {
		ret = PTR_ERR(fsl_lpspi->clk);
		goto out_controller_put;
	}

	ret = clk_prepare_enable(fsl_lpspi->clk);
	if (ret) {
		dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
		goto out_controller_put;
	}

	temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
	fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);

	clk_disable_unprepare(fsl_lpspi->clk);

	ret = devm_spi_register_controller(&pdev->dev, controller);
	if (ret < 0) {
		dev_err(&pdev->dev, "spi_register_controller error.\n");
		goto out_controller_put;
	}

	return 0;

out_controller_put:
	spi_controller_put(controller);

	return ret;
}

static int fsl_lpspi_remove(struct platform_device *pdev)
{
	struct spi_controller *controller = platform_get_drvdata(pdev);
	struct fsl_lpspi_data *fsl_lpspi =
				spi_controller_get_devdata(controller);

	clk_disable_unprepare(fsl_lpspi->clk);

	return 0;
}

static struct platform_driver fsl_lpspi_driver = {
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = fsl_lpspi_dt_ids,
	},
	.probe = fsl_lpspi_probe,
	.remove = fsl_lpspi_remove,
};
module_platform_driver(fsl_lpspi_driver);

MODULE_DESCRIPTION("LPSPI Controller driver");
MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
6126fd83 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Freescale i.MX7ULP LPSPI driver
	4	//
	5	// Copyright 2016 Freescale Semiconductor, Inc.
07d71557	6	// Copyright 2018 NXP Semiconductors
5314987d GP	7
	8	#include <linux/clk.h>
	9	#include <linux/completion.h>
	10	#include <linux/delay.h>
	11	#include <linux/err.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/irq.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
	21	#include <linux/spi/spi.h>
	22	#include <linux/spi/spi_bitbang.h>
	23	#include <linux/types.h>
	24
	25	#define DRIVER_NAME "fsl_lpspi"
	26
	27	/* i.MX7ULP LPSPI registers */
	28	#define IMX7ULP_VERID 0x0
	29	#define IMX7ULP_PARAM 0x4
	30	#define IMX7ULP_CR 0x10
	31	#define IMX7ULP_SR 0x14
	32	#define IMX7ULP_IER 0x18
	33	#define IMX7ULP_DER 0x1c
	34	#define IMX7ULP_CFGR0 0x20
	35	#define IMX7ULP_CFGR1 0x24
	36	#define IMX7ULP_DMR0 0x30
	37	#define IMX7ULP_DMR1 0x34
	38	#define IMX7ULP_CCR 0x40
	39	#define IMX7ULP_FCR 0x58
	40	#define IMX7ULP_FSR 0x5c
	41	#define IMX7ULP_TCR 0x60
	42	#define IMX7ULP_TDR 0x64
	43	#define IMX7ULP_RSR 0x70
	44	#define IMX7ULP_RDR 0x74
	45
	46	/* General control register field define */
	47	#define CR_RRF BIT(9)
	48	#define CR_RTF BIT(8)
	49	#define CR_RST BIT(1)
	50	#define CR_MEN BIT(0)
6a130448	51	#define SR_MBF BIT(24)
5314987d	52	#define SR_TCF BIT(10)
c23fdef8	53	#define SR_FCF BIT(9)
5314987d GP	54	#define SR_RDF BIT(1)
	55	#define SR_TDF BIT(0)
	56	#define IER_TCIE BIT(10)
c23fdef8	57	#define IER_FCIE BIT(9)
5314987d GP	58	#define IER_RDIE BIT(1)
	59	#define IER_TDIE BIT(0)
	60	#define CFGR1_PCSCFG BIT(27)
bcd87317	61	#define CFGR1_PINCFG (BIT(24)\|BIT(25))
5314987d GP	62	#define CFGR1_PCSPOL BIT(8)
	63	#define CFGR1_NOSTALL BIT(3)
	64	#define CFGR1_MASTER BIT(0)
6a130448	65	#define FSR_RXCOUNT (BIT(16)\|BIT(17)\|BIT(18))
5314987d GP	66	#define RSR_RXEMPTY BIT(1)
	67	#define TCR_CPOL BIT(31)
	68	#define TCR_CPHA BIT(30)
	69	#define TCR_CONT BIT(21)
	70	#define TCR_CONTC BIT(20)
	71	#define TCR_RXMSK BIT(19)
	72	#define TCR_TXMSK BIT(18)
	73
	74	static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
	75
	76	struct lpspi_config {
	77	u8 bpw;
	78	u8 chip_select;
	79	u8 prescale;
	80	u16 mode;
	81	u32 speed_hz;
	82	};
	83
	84	struct fsl_lpspi_data {
	85	struct device *dev;
	86	void __iomem *base;
	87	struct clk *clk;
bcd87317	88	bool is_slave;
5314987d GP	89
	90	void *rx_buf;
	91	const void *tx_buf;
	92	void (tx)(struct fsl_lpspi_data );
	93	void (rx)(struct fsl_lpspi_data );
	94
	95	u32 remain;
cf86874b	96	u8 watermark;
5314987d GP	97	u8 txfifosize;
	98	u8 rxfifosize;
	99
	100	struct lpspi_config config;
	101	struct completion xfer_done;
bcd87317 CW	102
bcd87317 CW	103	bool slave_aborted;
5314987d GP	104	};
	105
	106	static const struct of_device_id fsl_lpspi_dt_ids[] = {
	107	{ .compatible = "fsl,imx7ulp-spi", },
	108	{ /* sentinel */ }
	109	};
	110	MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
	111
	112	#define LPSPI_BUF_RX(type) \
	113	static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
	114	{ \
	115	unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
	116	\
	117	if (fsl_lpspi->rx_buf) { \
	118	(type )fsl_lpspi->rx_buf = val; \
	119	fsl_lpspi->rx_buf += sizeof(type); \
	120	} \
	121	}
	122
	123	#define LPSPI_BUF_TX(type) \
	124	static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
	125	{ \
	126	type val = 0; \
	127	\
	128	if (fsl_lpspi->tx_buf) { \
	129	val = (type )fsl_lpspi->tx_buf; \
	130	fsl_lpspi->tx_buf += sizeof(type); \
	131	} \
	132	\
	133	fsl_lpspi->remain -= sizeof(type); \
	134	writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
	135	}
	136
	137	LPSPI_BUF_RX(u8)
	138	LPSPI_BUF_TX(u8)
	139	LPSPI_BUF_RX(u16)
	140	LPSPI_BUF_TX(u16)
	141	LPSPI_BUF_RX(u32)
	142	LPSPI_BUF_TX(u32)
	143
	144	static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
	145	unsigned int enable)
	146	{
	147	writel(enable, fsl_lpspi->base + IMX7ULP_IER);
	148	}
	149
07d71557	150	static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
5314987d	151	{
07d71557 CW	152	struct fsl_lpspi_data *fsl_lpspi =
07d71557 CW	153	spi_controller_get_devdata(controller);
5314987d GP	154
	155	return clk_prepare_enable(fsl_lpspi->clk);
	156	}
	157
07d71557	158	static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
5314987d	159	{
07d71557 CW	160	struct fsl_lpspi_data *fsl_lpspi =
07d71557 CW	161	spi_controller_get_devdata(controller);
5314987d GP	162
	163	clk_disable_unprepare(fsl_lpspi->clk);
	164
	165	return 0;
	166	}
	167
5314987d GP	168	static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
	169	{
	170	u8 txfifo_cnt;
c23fdef8	171	u32 temp;
5314987d GP	172
	173	txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
	174
	175	while (txfifo_cnt < fsl_lpspi->txfifosize) {
	176	if (!fsl_lpspi->remain)
	177	break;
	178	fsl_lpspi->tx(fsl_lpspi);
	179	txfifo_cnt++;
	180	}
	181
c23fdef8 CW	182	if (txfifo_cnt < fsl_lpspi->txfifosize) {
	183	if (!fsl_lpspi->is_slave) {
	184	temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
	185	temp &= ~TCR_CONTC;
	186	writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
	187	}
	188
	189	fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
	190	} else
5314987d GP	191	fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
	192	}
	193
	194	static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
	195	{
	196	while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
	197	fsl_lpspi->rx(fsl_lpspi);
	198	}
	199
	200	static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
	201	bool is_first_xfer)
	202	{
	203	u32 temp = 0;
	204
	205	temp \|= fsl_lpspi->config.bpw - 1;
e3a49390	206	temp \|= (fsl_lpspi->config.mode & 0x3) << 30;
bcd87317 CW	207	if (!fsl_lpspi->is_slave) {
	208	temp \|= fsl_lpspi->config.prescale << 27;
	209	temp \|= (fsl_lpspi->config.chip_select & 0x3) << 24;
	210
	211	/*
	212	* Set TCR_CONT will keep SS asserted after current transfer.
	213	* For the first transfer, clear TCR_CONTC to assert SS.
	214	* For subsequent transfer, set TCR_CONTC to keep SS asserted.
	215	*/
	216	temp \|= TCR_CONT;
	217	if (is_first_xfer)
	218	temp &= ~TCR_CONTC;
	219	else
	220	temp \|= TCR_CONTC;
	221	}
5314987d GP	222	writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
	223
	224	dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
	225	}
	226
	227	static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
	228	{
5314987d GP	229	u32 temp;
5314987d GP	230
cf86874b	231	temp = fsl_lpspi->watermark >> 1 \| (fsl_lpspi->watermark >> 1) << 16;
5314987d GP	232
	233	writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
	234
	235	dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
	236	}
	237
	238	static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
	239	{
	240	struct lpspi_config config = fsl_lpspi->config;
	241	unsigned int perclk_rate, scldiv;
	242	u8 prescale;
	243
	244	perclk_rate = clk_get_rate(fsl_lpspi->clk);
	245	for (prescale = 0; prescale < 8; prescale++) {
	246	scldiv = perclk_rate /
	247	(clkdivs[prescale] * config.speed_hz) - 2;
	248	if (scldiv < 256) {
	249	fsl_lpspi->config.prescale = prescale;
	250	break;
	251	}
	252	}
	253
	254	if (prescale == 8 && scldiv >= 256)
	255	return -EINVAL;
	256
cf86874b CW	257	writel(scldiv \| (scldiv << 8) \| ((scldiv >> 1) << 16),
cf86874b CW	258	fsl_lpspi->base + IMX7ULP_CCR);
5314987d GP	259
	260	dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
	261	perclk_rate, config.speed_hz, prescale, scldiv);
	262
	263	return 0;
	264	}
	265
	266	static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
	267	{
	268	u32 temp;
	269	int ret;
	270
bcd87317 CW	271	if (!fsl_lpspi->is_slave) {
	272	ret = fsl_lpspi_set_bitrate(fsl_lpspi);
	273	if (ret)
	274	return ret;
	275	}
5314987d GP	276
	277	fsl_lpspi_set_watermark(fsl_lpspi);
	278
bcd87317 CW	279	if (!fsl_lpspi->is_slave)
	280	temp = CFGR1_MASTER;
	281	else
	282	temp = CFGR1_PINCFG;
5314987d GP	283	if (fsl_lpspi->config.mode & SPI_CS_HIGH)
	284	temp \|= CFGR1_PCSPOL;
	285	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
	286
	287	temp = readl(fsl_lpspi->base + IMX7ULP_CR);
	288	temp \|= CR_RRF \| CR_RTF \| CR_MEN;
	289	writel(temp, fsl_lpspi->base + IMX7ULP_CR);
	290
	291	return 0;
	292	}
	293
	294	static void fsl_lpspi_setup_transfer(struct spi_device *spi,
	295	struct spi_transfer *t)
	296	{
07d71557 CW	297	struct fsl_lpspi_data *fsl_lpspi =
07d71557 CW	298	spi_controller_get_devdata(spi->controller);
5314987d GP	299
	300	fsl_lpspi->config.mode = spi->mode;
	301	fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
	302	fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
	303	fsl_lpspi->config.chip_select = spi->chip_select;
	304
	305	if (!fsl_lpspi->config.speed_hz)
	306	fsl_lpspi->config.speed_hz = spi->max_speed_hz;
	307	if (!fsl_lpspi->config.bpw)
	308	fsl_lpspi->config.bpw = spi->bits_per_word;
	309
	310	/* Initialize the functions for transfer */
	311	if (fsl_lpspi->config.bpw <= 8) {
	312	fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
	313	fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
	314	} else if (fsl_lpspi->config.bpw <= 16) {
	315	fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
	316	fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
	317	} else {
	318	fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
	319	fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
	320	}
	321
cf86874b CW	322	if (t->len <= fsl_lpspi->txfifosize)
	323	fsl_lpspi->watermark = t->len;
	324	else
	325	fsl_lpspi->watermark = fsl_lpspi->txfifosize;
	326
5314987d GP	327	fsl_lpspi_config(fsl_lpspi);
	328	}
	329
bcd87317 CW	330	static int fsl_lpspi_slave_abort(struct spi_controller *controller)
	331	{
	332	struct fsl_lpspi_data *fsl_lpspi =
	333	spi_controller_get_devdata(controller);
	334
	335	fsl_lpspi->slave_aborted = true;
	336	complete(&fsl_lpspi->xfer_done);
	337	return 0;
	338	}
	339
	340	static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
	341	{
	342	struct fsl_lpspi_data *fsl_lpspi =
	343	spi_controller_get_devdata(controller);
	344
	345	if (fsl_lpspi->is_slave) {
	346	if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) \|\|
	347	fsl_lpspi->slave_aborted) {
	348	dev_dbg(fsl_lpspi->dev, "interrupted\n");
	349	return -EINTR;
	350	}
	351	} else {
	352	if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
	353	dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
	354	return -ETIMEDOUT;
	355	}
	356	}
	357
	358	return 0;
	359	}
	360
a15dc3d6 CW	361	static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
	362	{
	363	u32 temp;
	364
	365	/* Disable all interrupt */
	366	fsl_lpspi_intctrl(fsl_lpspi, 0);
	367
	368	/* W1C for all flags in SR */
	369	temp = 0x3F << 8;
	370	writel(temp, fsl_lpspi->base + IMX7ULP_SR);
	371
	372	/* Clear FIFO and disable module */
	373	temp = CR_RRF \| CR_RTF;
	374	writel(temp, fsl_lpspi->base + IMX7ULP_CR);
	375
	376	return 0;
	377	}
	378
07d71557	379	static int fsl_lpspi_transfer_one(struct spi_controller *controller,
5314987d GP	380	struct spi_device *spi,
	381	struct spi_transfer *t)
	382	{
07d71557 CW	383	struct fsl_lpspi_data *fsl_lpspi =
07d71557 CW	384	spi_controller_get_devdata(controller);
5314987d GP	385	int ret;
	386
	387	fsl_lpspi->tx_buf = t->tx_buf;
	388	fsl_lpspi->rx_buf = t->rx_buf;
	389	fsl_lpspi->remain = t->len;
	390
	391	reinit_completion(&fsl_lpspi->xfer_done);
bcd87317 CW	392	fsl_lpspi->slave_aborted = false;
bcd87317 CW	393
5314987d	394	fsl_lpspi_write_tx_fifo(fsl_lpspi);
d2ad0a62	395
bcd87317 CW	396	ret = fsl_lpspi_wait_for_completion(controller);
	397	if (ret)
	398	return ret;
5314987d	399
a15dc3d6 CW	400	fsl_lpspi_reset(fsl_lpspi);
a15dc3d6 CW	401
d989eed2	402	return 0;
5314987d GP	403	}
5314987d GP	404
07d71557	405	static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
5314987d GP	406	struct spi_message *msg)
5314987d GP	407	{
07d71557 CW	408	struct fsl_lpspi_data *fsl_lpspi =
07d71557 CW	409	spi_controller_get_devdata(controller);
5314987d GP	410	struct spi_device *spi = msg->spi;
	411	struct spi_transfer *xfer;
	412	bool is_first_xfer = true;
cc4a7ffe	413	int ret = 0;
5314987d GP	414
	415	msg->status = 0;
	416	msg->actual_length = 0;
	417
	418	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
	419	fsl_lpspi_setup_transfer(spi, xfer);
	420	fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);
	421
	422	is_first_xfer = false;
	423
07d71557	424	ret = fsl_lpspi_transfer_one(controller, spi, xfer);
5314987d GP	425	if (ret < 0)
	426	goto complete;
	427
	428	msg->actual_length += xfer->len;
	429	}
	430
	431	complete:
5314987d	432	msg->status = ret;
07d71557	433	spi_finalize_current_message(controller);
5314987d GP	434
	435	return ret;
	436	}
	437
	438	static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
	439	{
c23fdef8	440	u32 temp_SR, temp_IER;
5314987d	441	struct fsl_lpspi_data *fsl_lpspi = dev_id;
5314987d	442
c23fdef8	443	temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
5314987d	444	fsl_lpspi_intctrl(fsl_lpspi, 0);
c23fdef8	445	temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
5314987d GP	446
	447	fsl_lpspi_read_rx_fifo(fsl_lpspi);
	448
c23fdef8	449	if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
5314987d	450	fsl_lpspi_write_tx_fifo(fsl_lpspi);
c23fdef8 CW	451	return IRQ_HANDLED;
c23fdef8 CW	452	}
5314987d	453
6a130448 CW	454	if (temp_SR & SR_MBF \|\|
	455	readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
	456	writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
	457	fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
	458	return IRQ_HANDLED;
	459	}
	460
c23fdef8 CW	461	if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
c23fdef8 CW	462	writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
5314987d	463	complete(&fsl_lpspi->xfer_done);
5314987d GP	464	return IRQ_HANDLED;
	465	}
	466
	467	return IRQ_NONE;
	468	}
	469
	470	static int fsl_lpspi_probe(struct platform_device *pdev)
	471	{
	472	struct fsl_lpspi_data *fsl_lpspi;
07d71557	473	struct spi_controller *controller;
5314987d GP	474	struct resource *res;
5314987d GP	475	int ret, irq;
b88a0dea	476	u32 temp;
5314987d	477
bcd87317 CW	478	if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
	479	controller = spi_alloc_slave(&pdev->dev,
	480	sizeof(struct fsl_lpspi_data));
	481	else
	482	controller = spi_alloc_master(&pdev->dev,
07d71557	483	sizeof(struct fsl_lpspi_data));
bcd87317	484
07d71557	485	if (!controller)
5314987d GP	486	return -ENOMEM;
5314987d GP	487
07d71557	488	platform_set_drvdata(pdev, controller);
5314987d	489
07d71557 CW	490	controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
07d71557 CW	491	controller->bus_num = pdev->id;
5314987d	492
07d71557	493	fsl_lpspi = spi_controller_get_devdata(controller);
5314987d	494	fsl_lpspi->dev = &pdev->dev;
bcd87317 CW	495	fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
bcd87317 CW	496	"spi-slave");
5314987d	497
07d71557 CW	498	controller->transfer_one_message = fsl_lpspi_transfer_one_msg;
	499	controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
	500	controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
	501	controller->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	502	controller->flags = SPI_MASTER_MUST_RX \| SPI_MASTER_MUST_TX;
	503	controller->dev.of_node = pdev->dev.of_node;
	504	controller->bus_num = pdev->id;
bcd87317	505	controller->slave_abort = fsl_lpspi_slave_abort;
5314987d GP	506
	507	init_completion(&fsl_lpspi->xfer_done);
	508
	509	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	510	fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
	511	if (IS_ERR(fsl_lpspi->base)) {
	512	ret = PTR_ERR(fsl_lpspi->base);
07d71557	513	goto out_controller_put;
5314987d GP	514	}
	515
	516	irq = platform_get_irq(pdev, 0);
	517	if (irq < 0) {
	518	ret = irq;
07d71557	519	goto out_controller_put;
5314987d GP	520	}
	521
	522	ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
	523	dev_name(&pdev->dev), fsl_lpspi);
	524	if (ret) {
	525	dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
07d71557	526	goto out_controller_put;
5314987d GP	527	}
	528
	529	fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
	530	if (IS_ERR(fsl_lpspi->clk)) {
	531	ret = PTR_ERR(fsl_lpspi->clk);
07d71557	532	goto out_controller_put;
5314987d GP	533	}
5314987d GP	534
b88a0dea GP	535	ret = clk_prepare_enable(fsl_lpspi->clk);
	536	if (ret) {
	537	dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
07d71557	538	goto out_controller_put;
b88a0dea GP	539	}
	540
	541	temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
	542	fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
	543	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
	544
	545	clk_disable_unprepare(fsl_lpspi->clk);
	546
07d71557	547	ret = devm_spi_register_controller(&pdev->dev, controller);
5314987d	548	if (ret < 0) {
07d71557 CW	549	dev_err(&pdev->dev, "spi_register_controller error.\n");
07d71557 CW	550	goto out_controller_put;
5314987d GP	551	}
	552
	553	return 0;
	554
07d71557 CW	555	out_controller_put:
07d71557 CW	556	spi_controller_put(controller);
5314987d GP	557
	558	return ret;
	559	}
	560
	561	static int fsl_lpspi_remove(struct platform_device *pdev)
	562	{
07d71557 CW	563	struct spi_controller *controller = platform_get_drvdata(pdev);
	564	struct fsl_lpspi_data *fsl_lpspi =
	565	spi_controller_get_devdata(controller);
5314987d GP	566
	567	clk_disable_unprepare(fsl_lpspi->clk);
	568
	569	return 0;
	570	}
	571
	572	static struct platform_driver fsl_lpspi_driver = {
	573	.driver = {
102ecc47 GP	574	.name = DRIVER_NAME,
	575	.of_match_table = fsl_lpspi_dt_ids,
	576	},
5314987d GP	577	.probe = fsl_lpspi_probe,
	578	.remove = fsl_lpspi_remove,
	579	};
	580	module_platform_driver(fsl_lpspi_driver);
	581
07d71557	582	MODULE_DESCRIPTION("LPSPI Controller driver");
5314987d	583	MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
b6787b68	584	MODULE_LICENSE("GPL");