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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
b36ece83 MH |
2 | /* |
3 | * Freescale SPI/eSPI controller driver library. | |
4 | * | |
5 | * Maintainer: Kumar Gala | |
6 | * | |
7 | * Copyright (C) 2006 Polycom, Inc. | |
8 | * | |
9 | * CPM SPI and QE buffer descriptors mode support: | |
10 | * Copyright (c) 2009 MontaVista Software, Inc. | |
11 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
12 | * | |
13 | * Copyright 2010 Freescale Semiconductor, Inc. | |
b36ece83 | 14 | */ |
b36ece83 | 15 | #include <linux/dma-mapping.h> |
a3108360 XL |
16 | #include <linux/fsl_devices.h> |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/kernel.h> | |
b36ece83 | 19 | #include <linux/mm.h> |
38455d7a | 20 | #include <linux/module.h> |
b36ece83 | 21 | #include <linux/of_platform.h> |
d57a4282 | 22 | #include <linux/spi/spi.h> |
e8beacbb | 23 | #ifdef CONFIG_FSL_SOC |
b36ece83 | 24 | #include <sysdev/fsl_soc.h> |
e8beacbb | 25 | #endif |
b36ece83 | 26 | |
ca632f55 | 27 | #include "spi-fsl-lib.h" |
b36ece83 MH |
28 | |
29 | #define MPC8XXX_SPI_RX_BUF(type) \ | |
30 | void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \ | |
31 | { \ | |
32 | type *rx = mpc8xxx_spi->rx; \ | |
33 | *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \ | |
34 | mpc8xxx_spi->rx = rx; \ | |
38455d7a EH |
35 | } \ |
36 | EXPORT_SYMBOL_GPL(mpc8xxx_spi_rx_buf_##type); | |
b36ece83 MH |
37 | |
38 | #define MPC8XXX_SPI_TX_BUF(type) \ | |
39 | u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \ | |
40 | { \ | |
41 | u32 data; \ | |
42 | const type *tx = mpc8xxx_spi->tx; \ | |
43 | if (!tx) \ | |
44 | return 0; \ | |
45 | data = *tx++ << mpc8xxx_spi->tx_shift; \ | |
46 | mpc8xxx_spi->tx = tx; \ | |
47 | return data; \ | |
38455d7a EH |
48 | } \ |
49 | EXPORT_SYMBOL_GPL(mpc8xxx_spi_tx_buf_##type); | |
b36ece83 MH |
50 | |
51 | MPC8XXX_SPI_RX_BUF(u8) | |
52 | MPC8XXX_SPI_RX_BUF(u16) | |
53 | MPC8XXX_SPI_RX_BUF(u32) | |
54 | MPC8XXX_SPI_TX_BUF(u8) | |
55 | MPC8XXX_SPI_TX_BUF(u16) | |
56 | MPC8XXX_SPI_TX_BUF(u32) | |
57 | ||
58 | struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata) | |
59 | { | |
60 | return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata); | |
61 | } | |
38455d7a | 62 | EXPORT_SYMBOL_GPL(to_of_pinfo); |
b36ece83 | 63 | |
b36ece83 MH |
64 | const char *mpc8xxx_spi_strmode(unsigned int flags) |
65 | { | |
66 | if (flags & SPI_QE_CPU_MODE) { | |
67 | return "QE CPU"; | |
68 | } else if (flags & SPI_CPM_MODE) { | |
69 | if (flags & SPI_QE) | |
70 | return "QE"; | |
71 | else if (flags & SPI_CPM2) | |
72 | return "CPM2"; | |
73 | else | |
74 | return "CPM1"; | |
75 | } | |
76 | return "CPU"; | |
77 | } | |
38455d7a | 78 | EXPORT_SYMBOL_GPL(mpc8xxx_spi_strmode); |
b36ece83 | 79 | |
c592becb | 80 | void mpc8xxx_spi_probe(struct device *dev, struct resource *mem, |
b36ece83 MH |
81 | unsigned int irq) |
82 | { | |
8074cf06 | 83 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
b36ece83 MH |
84 | struct spi_master *master; |
85 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 MH |
86 | |
87 | master = dev_get_drvdata(dev); | |
88 | ||
89 | /* the spi->mode bits understood by this driver: */ | |
90 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
91 | | SPI_LSB_FIRST | SPI_LOOP; | |
92 | ||
b36ece83 MH |
93 | master->dev.of_node = dev->of_node; |
94 | ||
95 | mpc8xxx_spi = spi_master_get_devdata(master); | |
96 | mpc8xxx_spi->dev = dev; | |
97 | mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8; | |
98 | mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8; | |
99 | mpc8xxx_spi->flags = pdata->flags; | |
100 | mpc8xxx_spi->spibrg = pdata->sysclk; | |
101 | mpc8xxx_spi->irq = irq; | |
102 | ||
103 | mpc8xxx_spi->rx_shift = 0; | |
104 | mpc8xxx_spi->tx_shift = 0; | |
105 | ||
b36ece83 MH |
106 | master->bus_num = pdata->bus_num; |
107 | master->num_chipselect = pdata->max_chipselect; | |
108 | ||
b36ece83 | 109 | init_completion(&mpc8xxx_spi->done); |
b36ece83 | 110 | } |
38455d7a | 111 | EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe); |
b36ece83 | 112 | |
fd4a319b | 113 | int of_mpc8xxx_spi_probe(struct platform_device *ofdev) |
b36ece83 MH |
114 | { |
115 | struct device *dev = &ofdev->dev; | |
116 | struct device_node *np = ofdev->dev.of_node; | |
117 | struct mpc8xxx_spi_probe_info *pinfo; | |
118 | struct fsl_spi_platform_data *pdata; | |
119 | const void *prop; | |
120 | int ret = -ENOMEM; | |
121 | ||
7282326b | 122 | pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL); |
b36ece83 | 123 | if (!pinfo) |
ef4bbdec | 124 | return ret; |
b36ece83 MH |
125 | |
126 | pdata = &pinfo->pdata; | |
127 | dev->platform_data = pdata; | |
128 | ||
129 | /* Allocate bus num dynamically. */ | |
130 | pdata->bus_num = -1; | |
131 | ||
e8beacbb | 132 | #ifdef CONFIG_FSL_SOC |
b36ece83 MH |
133 | /* SPI controller is either clocked from QE or SoC clock. */ |
134 | pdata->sysclk = get_brgfreq(); | |
135 | if (pdata->sysclk == -1) { | |
136 | pdata->sysclk = fsl_get_sys_freq(); | |
7282326b AL |
137 | if (pdata->sysclk == -1) |
138 | return -ENODEV; | |
b36ece83 | 139 | } |
e8beacbb AL |
140 | #else |
141 | ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk); | |
142 | if (ret) | |
7282326b | 143 | return ret; |
e8beacbb | 144 | #endif |
b36ece83 MH |
145 | |
146 | prop = of_get_property(np, "mode", NULL); | |
147 | if (prop && !strcmp(prop, "cpu-qe")) | |
148 | pdata->flags = SPI_QE_CPU_MODE; | |
149 | else if (prop && !strcmp(prop, "qe")) | |
150 | pdata->flags = SPI_CPM_MODE | SPI_QE; | |
151 | else if (of_device_is_compatible(np, "fsl,cpm2-spi")) | |
152 | pdata->flags = SPI_CPM_MODE | SPI_CPM2; | |
153 | else if (of_device_is_compatible(np, "fsl,cpm1-spi")) | |
154 | pdata->flags = SPI_CPM_MODE | SPI_CPM1; | |
155 | ||
156 | return 0; | |
b36ece83 | 157 | } |
38455d7a EH |
158 | EXPORT_SYMBOL_GPL(of_mpc8xxx_spi_probe); |
159 | ||
160 | MODULE_LICENSE("GPL"); |