projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Linux 4.1-rc1
[linux-2.6-block.git] / drivers / spi / spi-fsl-espi.c
CommitLineData
8b60d6c2
MH		 1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
8b60d6c2 11#include <linux/delay.h>
a3108360 12#include <linux/err.h>
8b60d6c2 13#include <linux/fsl_devices.h>
a3108360
XL		 14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/module.h>
8b60d6c2
MH		 17#include <linux/mm.h>
18#include <linux/of.h>
5af50730
RH		 19#include <linux/of_address.h>
20#include <linux/of_irq.h>
8b60d6c2 21#include <linux/of_platform.h>
a3108360
XL		 22#include <linux/platform_device.h>
23#include <linux/spi/spi.h>
8b60d6c2
MH		 24#include <sysdev/fsl_soc.h>
25
ca632f55 26#include "spi-fsl-lib.h"
8b60d6c2
MH		 27
28/* eSPI Controller registers */
29struct fsl_espi_reg {
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
38};
39
40struct fsl_espi_transfer {
41 const void *tx_buf;
42 void *rx_buf;
43 unsigned len;
44 unsigned n_tx;
45 unsigned n_rx;
46 unsigned actual_length;
47 int status;
48};
49
50/* eSPI Controller mode register definitions */
51#define SPMODE_ENABLE (1 << 31)
52#define SPMODE_LOOP (1 << 30)
53#define SPMODE_TXTHR(x) ((x) << 8)
54#define SPMODE_RXTHR(x) ((x) << 0)
55
56/* eSPI Controller CS mode register definitions */
57#define CSMODE_CI_INACTIVEHIGH (1 << 31)
58#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59#define CSMODE_REV (1 << 29)
60#define CSMODE_DIV16 (1 << 28)
61#define CSMODE_PM(x) ((x) << 24)
62#define CSMODE_POL_1 (1 << 20)
63#define CSMODE_LEN(x) ((x) << 16)
64#define CSMODE_BEF(x) ((x) << 12)
65#define CSMODE_AFT(x) ((x) << 8)
66#define CSMODE_CG(x) ((x) << 3)
67
68/* Default mode/csmode for eSPI controller */
69#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
72
73/* SPIE register values */
74#define SPIE_NE 0x00000200 /* Not empty */
75#define SPIE_NF 0x00000100 /* Not full */
76
77/* SPIM register values */
78#define SPIM_NE 0x00000200 /* Not empty */
79#define SPIM_NF 0x00000100 /* Not full */
80#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
82
83/* SPCOM register values */
84#define SPCOM_CS(x) ((x) << 30)
85#define SPCOM_TRANLEN(x) ((x) << 0)
86#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
87
88static void fsl_espi_change_mode(struct spi_device *spi)
89{
90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
91 struct spi_mpc8xxx_cs *cs = spi->controller_state;
92 struct fsl_espi_reg *reg_base = mspi->reg_base;
93 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
94 __be32 __iomem *espi_mode = &reg_base->mode;
95 u32 tmp;
96 unsigned long flags;
97
98 /* Turn off IRQs locally to minimize time that SPI is disabled. */
99 local_irq_save(flags);
100
101 /* Turn off SPI unit prior changing mode */
102 tmp = mpc8xxx_spi_read_reg(espi_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp);
106
107 local_irq_restore(flags);
108}
109
110static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
111{
112 u32 data;
113 u16 data_h;
114 u16 data_l;
115 const u32 *tx = mpc8xxx_spi->tx;
116
117 if (!tx)
118 return 0;
119
120 data = *tx++ << mpc8xxx_spi->tx_shift;
121 data_l = data & 0xffff;
122 data_h = (data >> 16) & 0xffff;
123 swab16s(&data_l);
124 swab16s(&data_h);
125 data = data_h | data_l;
126
127 mpc8xxx_spi->tx = tx;
128 return data;
129}
130
131static int fsl_espi_setup_transfer(struct spi_device *spi,
132 struct spi_transfer *t)
133{
134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
135 int bits_per_word = 0;
136 u8 pm;
137 u32 hz = 0;
138 struct spi_mpc8xxx_cs *cs = spi->controller_state;
139
140 if (t) {
141 bits_per_word = t->bits_per_word;
142 hz = t->speed_hz;
143 }
144
145 /* spi_transfer level calls that work per-word */
146 if (!bits_per_word)
147 bits_per_word = spi->bits_per_word;
148
8b60d6c2
MH		 149 if (!hz)
150 hz = spi->max_speed_hz;
151
152 cs->rx_shift = 0;
153 cs->tx_shift = 0;
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
156 if (bits_per_word <= 8) {
157 cs->rx_shift = 8 - bits_per_word;
51faed69 158 } else {
8b60d6c2
MH		 159 cs->rx_shift = 16 - bits_per_word;
160 if (spi->mode & SPI_LSB_FIRST)
161 cs->get_tx = fsl_espi_tx_buf_lsb;
8b60d6c2
MH		 162 }
163
164 mpc8xxx_spi->rx_shift = cs->rx_shift;
165 mpc8xxx_spi->tx_shift = cs->tx_shift;
166 mpc8xxx_spi->get_rx = cs->get_rx;
167 mpc8xxx_spi->get_tx = cs->get_tx;
168
169 bits_per_word = bits_per_word - 1;
170
171 /* mask out bits we are going to set */
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
173
174 cs->hw_mode |= CSMODE_LEN(bits_per_word);
175
176 if ((mpc8xxx_spi->spibrg / hz) > 64) {
177 cs->hw_mode |= CSMODE_DIV16;
35faa55c 178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
8b60d6c2 179
87bf5ab8 180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
8b60d6c2 181 "Will use %d Hz instead.\n", dev_name(&spi->dev),
87bf5ab8
SAS		 182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
183 if (pm > 33)
184 pm = 33;
8b60d6c2 185 } else {
35faa55c 186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
8b60d6c2
MH		 187 }
188 if (pm)
189 pm--;
87bf5ab8
SAS		 190 if (pm < 2)
191 pm = 2;
8b60d6c2
MH		 192
193 cs->hw_mode |= CSMODE_PM(pm);
194
195 fsl_espi_change_mode(spi);
196 return 0;
197}
198
199static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
200 unsigned int len)
201{
202 u32 word;
203 struct fsl_espi_reg *reg_base = mspi->reg_base;
204
205 mspi->count = len;
206
207 /* enable rx ints */
208 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
209
210 /* transmit word */
211 word = mspi->get_tx(mspi);
212 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
213
214 return 0;
215}
216
217static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
218{
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len;
8b60d6c2
MH		 222 int ret;
223
8b60d6c2
MH		 224 mpc8xxx_spi->len = t->len;
225 len = roundup(len, 4) / 4;
226
227 mpc8xxx_spi->tx = t->tx_buf;
228 mpc8xxx_spi->rx = t->rx_buf;
229
16735d02 230 reinit_completion(&mpc8xxx_spi->done);
8b60d6c2
MH		 231
232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
235 " beyond the SPCOM[TRANLEN] field\n", t->len);
236 return -EINVAL;
237 }
238 mpc8xxx_spi_write_reg(&reg_base->command,
239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
240
241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
242 if (ret)
243 return ret;
244
245 wait_for_completion(&mpc8xxx_spi->done);
246
247 /* disable rx ints */
248 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
249
250 return mpc8xxx_spi->count;
251}
252
0dd2c96f 253static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
8b60d6c2 254{
0dd2c96f 255 if (cmd) {
8b60d6c2
MH		 256 cmd[1] = (u8)(addr >> 16);
257 cmd[2] = (u8)(addr >> 8);
258 cmd[3] = (u8)(addr >> 0);
259 }
260}
261
0dd2c96f 262static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
8b60d6c2 263{
0dd2c96f 264 if (cmd)
8b60d6c2
MH		 265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
266
267 return 0;
268}
269
270static void fsl_espi_do_trans(struct spi_message *m,
271 struct fsl_espi_transfer *tr)
272{
273 struct spi_device *spi = m->spi;
274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
275 struct fsl_espi_transfer *espi_trans = tr;
276 struct spi_message message;
277 struct spi_transfer *t, *first, trans;
278 int status = 0;
279
280 spi_message_init(&message);
281 memset(&trans, 0, sizeof(trans));
282
283 first = list_first_entry(&m->transfers, struct spi_transfer,
284 transfer_list);
285 list_for_each_entry(t, &m->transfers, transfer_list) {
286 if ((first->bits_per_word != t->bits_per_word) ||
287 (first->speed_hz != t->speed_hz)) {
288 espi_trans->status = -EINVAL;
f6bd03a7
JN		 289 dev_err(mspi->dev,
290 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
8b60d6c2
MH		 291 return;
292 }
293
294 trans.speed_hz = t->speed_hz;
295 trans.bits_per_word = t->bits_per_word;
296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
297 }
298
299 trans.len = espi_trans->len;
300 trans.tx_buf = espi_trans->tx_buf;
301 trans.rx_buf = espi_trans->rx_buf;
302 spi_message_add_tail(&trans, &message);
303
304 list_for_each_entry(t, &message.transfers, transfer_list) {
305 if (t->bits_per_word || t->speed_hz) {
306 status = -EINVAL;
307
308 status = fsl_espi_setup_transfer(spi, t);
309 if (status < 0)
310 break;
311 }
312
313 if (t->len)
314 status = fsl_espi_bufs(spi, t);
315
316 if (status) {
317 status = -EMSGSIZE;
318 break;
319 }
320
321 if (t->delay_usecs)
322 udelay(t->delay_usecs);
323 }
324
325 espi_trans->status = status;
326 fsl_espi_setup_transfer(spi, NULL);
327}
328
329static void fsl_espi_cmd_trans(struct spi_message *m,
330 struct fsl_espi_transfer *trans, u8 *rx_buff)
331{
332 struct spi_transfer *t;
333 u8 *local_buf;
334 int i = 0;
335 struct fsl_espi_transfer *espi_trans = trans;
336
337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
338 if (!local_buf) {
339 espi_trans->status = -ENOMEM;
340 return;
341 }
342
343 list_for_each_entry(t, &m->transfers, transfer_list) {
344 if (t->tx_buf) {
345 memcpy(local_buf + i, t->tx_buf, t->len);
346 i += t->len;
347 }
348 }
349
350 espi_trans->tx_buf = local_buf;
a2cb1be1 351 espi_trans->rx_buf = local_buf;
8b60d6c2
MH		 352 fsl_espi_do_trans(m, espi_trans);
353
354 espi_trans->actual_length = espi_trans->len;
355 kfree(local_buf);
356}
357
358static void fsl_espi_rw_trans(struct spi_message *m,
359 struct fsl_espi_transfer *trans, u8 *rx_buff)
360{
361 struct fsl_espi_transfer *espi_trans = trans;
362 unsigned int n_tx = espi_trans->n_tx;
363 unsigned int n_rx = espi_trans->n_rx;
364 struct spi_transfer *t;
365 u8 *local_buf;
366 u8 *rx_buf = rx_buff;
367 unsigned int trans_len;
368 unsigned int addr;
369 int i, pos, loop;
370
371 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
372 if (!local_buf) {
373 espi_trans->status = -ENOMEM;
374 return;
375 }
376
377 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
378 trans_len = n_rx - pos;
379 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
380 trans_len = SPCOM_TRANLEN_MAX - n_tx;
381
382 i = 0;
383 list_for_each_entry(t, &m->transfers, transfer_list) {
384 if (t->tx_buf) {
385 memcpy(local_buf + i, t->tx_buf, t->len);
386 i += t->len;
387 }
388 }
389
0dd2c96f
MH		 390 if (pos > 0) {
391 addr = fsl_espi_cmd2addr(local_buf);
392 addr += pos;
393 fsl_espi_addr2cmd(addr, local_buf);
394 }
8b60d6c2
MH		 395
396 espi_trans->n_tx = n_tx;
397 espi_trans->n_rx = trans_len;
398 espi_trans->len = trans_len + n_tx;
399 espi_trans->tx_buf = local_buf;
a2cb1be1 400 espi_trans->rx_buf = local_buf;
8b60d6c2
MH		 401 fsl_espi_do_trans(m, espi_trans);
402
403 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
404
405 if (loop > 0)
406 espi_trans->actual_length += espi_trans->len - n_tx;
407 else
408 espi_trans->actual_length += espi_trans->len;
409 }
410
411 kfree(local_buf);
412}
413
c592becb
HK		 414static int fsl_espi_do_one_msg(struct spi_master *master,
415 struct spi_message *m)
8b60d6c2
MH		 416{
417 struct spi_transfer *t;
418 u8 *rx_buf = NULL;
419 unsigned int n_tx = 0;
420 unsigned int n_rx = 0;
421 struct fsl_espi_transfer espi_trans;
422
423 list_for_each_entry(t, &m->transfers, transfer_list) {
424 if (t->tx_buf)
425 n_tx += t->len;
426 if (t->rx_buf) {
427 n_rx += t->len;
428 rx_buf = t->rx_buf;
429 }
430 }
431
432 espi_trans.n_tx = n_tx;
433 espi_trans.n_rx = n_rx;
434 espi_trans.len = n_tx + n_rx;
435 espi_trans.actual_length = 0;
436 espi_trans.status = 0;
437
438 if (!rx_buf)
439 fsl_espi_cmd_trans(m, &espi_trans, NULL);
440 else
441 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
442
443 m->actual_length = espi_trans.actual_length;
444 m->status = espi_trans.status;
c592becb
HK		 445 spi_finalize_current_message(master);
446 return 0;
8b60d6c2
MH		 447}
448
449static int fsl_espi_setup(struct spi_device *spi)
450{
451 struct mpc8xxx_spi *mpc8xxx_spi;
452 struct fsl_espi_reg *reg_base;
453 int retval;
454 u32 hw_mode;
455 u32 loop_mode;
d9f26748 456 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
8b60d6c2
MH		 457
458 if (!spi->max_speed_hz)
459 return -EINVAL;
460
461 if (!cs) {
d9f26748 462 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
8b60d6c2
MH		 463 if (!cs)
464 return -ENOMEM;
d9f26748 465 spi_set_ctldata(spi, cs);
8b60d6c2
MH		 466 }
467
468 mpc8xxx_spi = spi_master_get_devdata(spi->master);
469 reg_base = mpc8xxx_spi->reg_base;
470
25985edc 471 hw_mode = cs->hw_mode; /* Save original settings */
8b60d6c2
MH		 472 cs->hw_mode = mpc8xxx_spi_read_reg(
473 &reg_base->csmode[spi->chip_select]);
474 /* mask out bits we are going to set */
475 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
476 | CSMODE_REV);
477
478 if (spi->mode & SPI_CPHA)
479 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
480 if (spi->mode & SPI_CPOL)
481 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
482 if (!(spi->mode & SPI_LSB_FIRST))
483 cs->hw_mode |= CSMODE_REV;
484
485 /* Handle the loop mode */
486 loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
487 loop_mode &= ~SPMODE_LOOP;
488 if (spi->mode & SPI_LOOP)
489 loop_mode |= SPMODE_LOOP;
490 mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
491
492 retval = fsl_espi_setup_transfer(spi, NULL);
493 if (retval < 0) {
494 cs->hw_mode = hw_mode; /* Restore settings */
495 return retval;
496 }
497 return 0;
498}
499
d9f26748
AL		 500static void fsl_espi_cleanup(struct spi_device *spi)
501{
502 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
503
504 kfree(cs);
505 spi_set_ctldata(spi, NULL);
506}
507
8b60d6c2
MH		 508void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
509{
510 struct fsl_espi_reg *reg_base = mspi->reg_base;
511
512 /* We need handle RX first */
513 if (events & SPIE_NE) {
e6289d63
MH		 514 u32 rx_data, tmp;
515 u8 rx_data_8;
8b60d6c2
MH		 516
517 /* Spin until RX is done */
518 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
519 cpu_relax();
520 events = mpc8xxx_spi_read_reg(&reg_base->event);
521 }
8b60d6c2 522
e6289d63
MH		 523 if (mspi->len >= 4) {
524 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
525 } else {
526 tmp = mspi->len;
527 rx_data = 0;
528 while (tmp--) {
529 rx_data_8 = in_8((u8 *)&reg_base->receive);
530 rx_data |= (rx_data_8 << (tmp * 8));
531 }
532
533 rx_data <<= (4 - mspi->len) * 8;
534 }
535
536 mspi->len -= 4;
8b60d6c2
MH		 537
538 if (mspi->rx)
539 mspi->get_rx(rx_data, mspi);
540 }
541
542 if (!(events & SPIE_NF)) {
543 int ret;
544
545 /* spin until TX is done */
546 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
547 &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
548 if (!ret) {
549 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
550 return;
551 }
552 }
553
554 /* Clear the events */
555 mpc8xxx_spi_write_reg(&reg_base->event, events);
556
557 mspi->count -= 1;
558 if (mspi->count) {
559 u32 word = mspi->get_tx(mspi);
560
561 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
562 } else {
563 complete(&mspi->done);
564 }
565}
566
567static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
568{
569 struct mpc8xxx_spi *mspi = context_data;
570 struct fsl_espi_reg *reg_base = mspi->reg_base;
571 irqreturn_t ret = IRQ_NONE;
572 u32 events;
573
574 /* Get interrupt events(tx/rx) */
575 events = mpc8xxx_spi_read_reg(&reg_base->event);
576 if (events)
577 ret = IRQ_HANDLED;
578
579 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
580
581 fsl_espi_cpu_irq(mspi, events);
582
583 return ret;
584}
585
586static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
587{
588 iounmap(mspi->reg_base);
589}
590
75506d0e
HK		 591static int fsl_espi_suspend(struct spi_master *master)
592{
593 struct mpc8xxx_spi *mpc8xxx_spi;
594 struct fsl_espi_reg *reg_base;
595 u32 regval;
596
597 mpc8xxx_spi = spi_master_get_devdata(master);
598 reg_base = mpc8xxx_spi->reg_base;
599
600 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
601 regval &= ~SPMODE_ENABLE;
602 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
603
604 return 0;
605}
606
607static int fsl_espi_resume(struct spi_master *master)
608{
609 struct mpc8xxx_spi *mpc8xxx_spi;
610 struct fsl_espi_reg *reg_base;
611 u32 regval;
612
613 mpc8xxx_spi = spi_master_get_devdata(master);
614 reg_base = mpc8xxx_spi->reg_base;
615
616 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
617 regval |= SPMODE_ENABLE;
618 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
619
620 return 0;
621}
622
fd4a319b 623static struct spi_master * fsl_espi_probe(struct device *dev,
8b60d6c2
MH		 624 struct resource *mem, unsigned int irq)
625{
8074cf06 626 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
8b60d6c2
MH		 627 struct spi_master *master;
628 struct mpc8xxx_spi *mpc8xxx_spi;
629 struct fsl_espi_reg *reg_base;
d0fb47a5
JW		 630 struct device_node *nc;
631 const __be32 *prop;
632 u32 regval, csmode;
633 int i, len, ret = 0;
8b60d6c2
MH		 634
635 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
636 if (!master) {
637 ret = -ENOMEM;
638 goto err;
639 }
640
641 dev_set_drvdata(dev, master);
642
c592becb 643 mpc8xxx_spi_probe(dev, mem, irq);
8b60d6c2 644
24778be2 645 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
8b60d6c2 646 master->setup = fsl_espi_setup;
d9f26748 647 master->cleanup = fsl_espi_cleanup;
c592becb 648 master->transfer_one_message = fsl_espi_do_one_msg;
75506d0e
HK		 649 master->prepare_transfer_hardware = fsl_espi_resume;
650 master->unprepare_transfer_hardware = fsl_espi_suspend;
8b60d6c2
MH		 651
652 mpc8xxx_spi = spi_master_get_devdata(master);
8b60d6c2
MH		 653 mpc8xxx_spi->spi_remove = fsl_espi_remove;
654
655 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
656 if (!mpc8xxx_spi->reg_base) {
657 ret = -ENOMEM;
658 goto err_probe;
659 }
660
661 reg_base = mpc8xxx_spi->reg_base;
662
663 /* Register for SPI Interrupt */
664 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
665 0, "fsl_espi", mpc8xxx_spi);
666 if (ret)
667 goto free_irq;
668
669 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
670 mpc8xxx_spi->rx_shift = 16;
671 mpc8xxx_spi->tx_shift = 24;
672 }
673
674 /* SPI controller initializations */
675 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
676 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
677 mpc8xxx_spi_write_reg(&reg_base->command, 0);
678 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
679
680 /* Init eSPI CS mode register */
d0fb47a5
JW		 681 for_each_available_child_of_node(master->dev.of_node, nc) {
682 /* get chip select */
683 prop = of_get_property(nc, "reg", &len);
684 if (!prop || len < sizeof(*prop))
685 continue;
686 i = be32_to_cpup(prop);
687 if (i < 0 || i >= pdata->max_chipselect)
688 continue;
689
690 csmode = CSMODE_INIT_VAL;
691 /* check if CSBEF is set in device tree */
692 prop = of_get_property(nc, "fsl,csbef", &len);
693 if (prop && len >= sizeof(*prop)) {
694 csmode &= ~(CSMODE_BEF(0xf));
695 csmode |= CSMODE_BEF(be32_to_cpup(prop));
696 }
697 /* check if CSAFT is set in device tree */
698 prop = of_get_property(nc, "fsl,csaft", &len);
699 if (prop && len >= sizeof(*prop)) {
700 csmode &= ~(CSMODE_AFT(0xf));
701 csmode |= CSMODE_AFT(be32_to_cpup(prop));
702 }
703 mpc8xxx_spi_write_reg(&reg_base->csmode[i], csmode);
704
705 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
706 }
8b60d6c2
MH		 707
708 /* Enable SPI interface */
709 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
710
711 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
712
713 ret = spi_register_master(master);
714 if (ret < 0)
715 goto unreg_master;
716
717 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
718
719 return master;
720
721unreg_master:
722 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
723free_irq:
724 iounmap(mpc8xxx_spi->reg_base);
725err_probe:
726 spi_master_put(master);
727err:
728 return ERR_PTR(ret);
729}
730
731static int of_fsl_espi_get_chipselects(struct device *dev)
732{
733 struct device_node *np = dev->of_node;
8074cf06 734 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
8b60d6c2
MH		 735 const u32 *prop;
736 int len;
737
738 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
739 if (!prop || len < sizeof(*prop)) {
740 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
741 return -EINVAL;
742 }
743
744 pdata->max_chipselect = *prop;
745 pdata->cs_control = NULL;
746
747 return 0;
748}
749
fd4a319b 750static int of_fsl_espi_probe(struct platform_device *ofdev)
8b60d6c2
MH		 751{
752 struct device *dev = &ofdev->dev;
753 struct device_node *np = ofdev->dev.of_node;
754 struct spi_master *master;
755 struct resource mem;
f7578496 756 unsigned int irq;
8b60d6c2
MH		 757 int ret = -ENOMEM;
758
18d306d1 759 ret = of_mpc8xxx_spi_probe(ofdev);
8b60d6c2
MH		 760 if (ret)
761 return ret;
762
763 ret = of_fsl_espi_get_chipselects(dev);
764 if (ret)
765 goto err;
766
767 ret = of_address_to_resource(np, 0, &mem);
768 if (ret)
769 goto err;
770
f7578496 771 irq = irq_of_parse_and_map(np, 0);
7227cd18 772 if (!irq) {
8b60d6c2
MH		 773 ret = -EINVAL;
774 goto err;
775 }
776
f7578496 777 master = fsl_espi_probe(dev, &mem, irq);
8b60d6c2
MH		 778 if (IS_ERR(master)) {
779 ret = PTR_ERR(master);
780 goto err;
781 }
782
783 return 0;
784
785err:
786 return ret;
787}
788
fd4a319b 789static int of_fsl_espi_remove(struct platform_device *dev)
8b60d6c2
MH		 790{
791 return mpc8xxx_spi_remove(&dev->dev);
792}
793
714bb654
HZ		 794#ifdef CONFIG_PM_SLEEP
795static int of_fsl_espi_suspend(struct device *dev)
796{
797 struct spi_master *master = dev_get_drvdata(dev);
714bb654
HZ		 798 int ret;
799
714bb654
HZ		 800 ret = spi_master_suspend(master);
801 if (ret) {
802 dev_warn(dev, "cannot suspend master\n");
803 return ret;
804 }
805
75506d0e 806 return fsl_espi_suspend(master);
714bb654
HZ		 807}
808
809static int of_fsl_espi_resume(struct device *dev)
810{
811 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
812 struct spi_master *master = dev_get_drvdata(dev);
813 struct mpc8xxx_spi *mpc8xxx_spi;
814 struct fsl_espi_reg *reg_base;
815 u32 regval;
816 int i;
817
818 mpc8xxx_spi = spi_master_get_devdata(master);
819 reg_base = mpc8xxx_spi->reg_base;
820
821 /* SPI controller initializations */
822 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
823 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
824 mpc8xxx_spi_write_reg(&reg_base->command, 0);
825 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
826
827 /* Init eSPI CS mode register */
828 for (i = 0; i < pdata->max_chipselect; i++)
829 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
830
831 /* Enable SPI interface */
832 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
833
834 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
835
836 return spi_master_resume(master);
837}
838#endif /* CONFIG_PM_SLEEP */
839
840static const struct dev_pm_ops espi_pm = {
841 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
842};
843
8b60d6c2
MH		 844static const struct of_device_id of_fsl_espi_match[] = {
845 { .compatible = "fsl,mpc8536-espi" },
846 {}
847};
848MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
849
18d306d1 850static struct platform_driver fsl_espi_driver = {
8b60d6c2
MH		 851 .driver = {
852 .name = "fsl_espi",
8b60d6c2 853 .of_match_table = of_fsl_espi_match,
714bb654 854 .pm = &espi_pm,
8b60d6c2
MH		 855 },
856 .probe = of_fsl_espi_probe,
fd4a319b 857 .remove = of_fsl_espi_remove,
8b60d6c2 858};
940ab889 859module_platform_driver(fsl_espi_driver);
8b60d6c2
MH		 860
861MODULE_AUTHOR("Mingkai Hu");
862MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
863MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)