Commit | Line | Data |
---|---|---|
8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
8b60d6c2 | 26 | /* eSPI Controller registers */ |
46afd38b HK |
27 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
28 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
29 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
30 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
31 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
32 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
33 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
34 | ||
35 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 36 | |
8b60d6c2 | 37 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
38 | #define SPMODE_ENABLE BIT(31) |
39 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
40 | #define SPMODE_TXTHR(x) ((x) << 8) |
41 | #define SPMODE_RXTHR(x) ((x) << 0) | |
42 | ||
43 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
44 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
45 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
46 | #define CSMODE_REV BIT(29) | |
47 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 48 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 49 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
50 | #define CSMODE_LEN(x) ((x) << 16) |
51 | #define CSMODE_BEF(x) ((x) << 12) | |
52 | #define CSMODE_AFT(x) ((x) << 8) | |
53 | #define CSMODE_CG(x) ((x) << 3) | |
54 | ||
54731265 | 55 | #define FSL_ESPI_FIFO_SIZE 32 |
e508cea4 | 56 | #define FSL_ESPI_RXTHR 15 |
54731265 | 57 | |
8b60d6c2 | 58 | /* Default mode/csmode for eSPI controller */ |
e508cea4 | 59 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR)) |
8b60d6c2 MH |
60 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ |
61 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
62 | ||
63 | /* SPIE register values */ | |
8b60d6c2 MH |
64 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
65 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
66 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
67 | #define SPIE_DON BIT(14) /* TX done */ | |
68 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
69 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
70 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
71 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
72 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
73 | ||
74 | /* SPIM register values */ | |
75 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
76 | #define SPIM_DON BIT(14) /* TX done */ | |
77 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
78 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
79 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
80 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
81 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
82 | |
83 | /* SPCOM register values */ | |
84 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
85 | #define SPCOM_DO BIT(28) /* Dual output */ |
86 | #define SPCOM_TO BIT(27) /* TX only */ | |
87 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 88 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 89 | |
5cfa1e4e | 90 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 91 | |
e9abb4db HK |
92 | #define AUTOSUSPEND_TIMEOUT 2000 |
93 | ||
35ab046b HK |
94 | struct fsl_espi { |
95 | struct device *dev; | |
96 | void __iomem *reg_base; | |
97 | ||
05823432 HK |
98 | struct list_head *m_transfers; |
99 | struct spi_transfer *tx_t; | |
100 | unsigned int tx_pos; | |
101 | bool tx_done; | |
dcb425f3 HK |
102 | struct spi_transfer *rx_t; |
103 | unsigned int rx_pos; | |
104 | bool rx_done; | |
05823432 | 105 | |
e1cdee73 | 106 | bool swab; |
35ab046b HK |
107 | unsigned int rxskip; |
108 | ||
35ab046b HK |
109 | spinlock_t lock; |
110 | ||
111 | u32 spibrg; /* SPIBRG input clock */ | |
112 | ||
113 | struct completion done; | |
114 | }; | |
115 | ||
219b5e3b HK |
116 | struct fsl_espi_cs { |
117 | u32 hw_mode; | |
118 | }; | |
119 | ||
35ab046b | 120 | static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset) |
46afd38b | 121 | { |
35ab046b | 122 | return ioread32be(espi->reg_base + offset); |
46afd38b HK |
123 | } |
124 | ||
dcb425f3 HK |
125 | static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset) |
126 | { | |
7e2ef003 | 127 | return ioread16be(espi->reg_base + offset); |
dcb425f3 HK |
128 | } |
129 | ||
35ab046b | 130 | static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset) |
46afd38b | 131 | { |
35ab046b | 132 | return ioread8(espi->reg_base + offset); |
46afd38b HK |
133 | } |
134 | ||
35ab046b | 135 | static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset, |
46afd38b HK |
136 | u32 val) |
137 | { | |
35ab046b | 138 | iowrite32be(val, espi->reg_base + offset); |
46afd38b HK |
139 | } |
140 | ||
05823432 HK |
141 | static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset, |
142 | u16 val) | |
143 | { | |
7e2ef003 | 144 | iowrite16be(val, espi->reg_base + offset); |
05823432 HK |
145 | } |
146 | ||
35ab046b | 147 | static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset, |
46afd38b HK |
148 | u8 val) |
149 | { | |
35ab046b | 150 | iowrite8(val, espi->reg_base + offset); |
46afd38b HK |
151 | } |
152 | ||
d3152cf1 HK |
153 | static int fsl_espi_check_message(struct spi_message *m) |
154 | { | |
35ab046b | 155 | struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); |
d3152cf1 HK |
156 | struct spi_transfer *t, *first; |
157 | ||
158 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
35ab046b | 159 | dev_err(espi->dev, "message too long, size is %u bytes\n", |
d3152cf1 HK |
160 | m->frame_length); |
161 | return -EMSGSIZE; | |
162 | } | |
163 | ||
164 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
165 | transfer_list); | |
e4be7053 | 166 | |
d3152cf1 HK |
167 | list_for_each_entry(t, &m->transfers, transfer_list) { |
168 | if (first->bits_per_word != t->bits_per_word || | |
169 | first->speed_hz != t->speed_hz) { | |
35ab046b | 170 | dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); |
d3152cf1 HK |
171 | return -EINVAL; |
172 | } | |
173 | } | |
174 | ||
e4be7053 HK |
175 | /* ESPI supports MSB-first transfers for word size 8 / 16 only */ |
176 | if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && | |
177 | first->bits_per_word != 16) { | |
35ab046b | 178 | dev_err(espi->dev, |
e4be7053 HK |
179 | "MSB-first transfer not supported for wordsize %u\n", |
180 | first->bits_per_word); | |
181 | return -EINVAL; | |
182 | } | |
183 | ||
d3152cf1 HK |
184 | return 0; |
185 | } | |
186 | ||
aca75157 HK |
187 | static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) |
188 | { | |
189 | struct spi_transfer *t; | |
190 | unsigned int i = 0, rxskip = 0; | |
191 | ||
192 | /* | |
193 | * prerequisites for ESPI rxskip mode: | |
194 | * - message has two transfers | |
195 | * - first transfer is a write and second is a read | |
196 | * | |
197 | * In addition the current low-level transfer mechanism requires | |
198 | * that the rxskip bytes fit into the TX FIFO. Else the transfer | |
199 | * would hang because after the first FSL_ESPI_FIFO_SIZE bytes | |
200 | * the TX FIFO isn't re-filled. | |
201 | */ | |
202 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
203 | if (i == 0) { | |
204 | if (!t->tx_buf || t->rx_buf || | |
205 | t->len > FSL_ESPI_FIFO_SIZE) | |
206 | return 0; | |
207 | rxskip = t->len; | |
208 | } else if (i == 1) { | |
209 | if (t->tx_buf || !t->rx_buf) | |
210 | return 0; | |
211 | } | |
212 | i++; | |
213 | } | |
214 | ||
215 | return i == 2 ? rxskip : 0; | |
216 | } | |
217 | ||
35ab046b | 218 | static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events) |
54731265 HK |
219 | { |
220 | u32 tx_fifo_avail; | |
05823432 HK |
221 | unsigned int tx_left; |
222 | const void *tx_buf; | |
54731265 HK |
223 | |
224 | /* if events is zero transfer has not started and tx fifo is empty */ | |
225 | tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE; | |
05823432 HK |
226 | start: |
227 | tx_left = espi->tx_t->len - espi->tx_pos; | |
228 | tx_buf = espi->tx_t->tx_buf; | |
229 | while (tx_fifo_avail >= min(4U, tx_left) && tx_left) { | |
230 | if (tx_left >= 4) { | |
231 | if (!tx_buf) | |
232 | fsl_espi_write_reg(espi, ESPI_SPITF, 0); | |
233 | else if (espi->swab) | |
234 | fsl_espi_write_reg(espi, ESPI_SPITF, | |
235 | swahb32p(tx_buf + espi->tx_pos)); | |
236 | else | |
237 | fsl_espi_write_reg(espi, ESPI_SPITF, | |
238 | *(u32 *)(tx_buf + espi->tx_pos)); | |
239 | espi->tx_pos += 4; | |
240 | tx_left -= 4; | |
54731265 | 241 | tx_fifo_avail -= 4; |
05823432 HK |
242 | } else if (tx_left >= 2 && tx_buf && espi->swab) { |
243 | fsl_espi_write_reg16(espi, ESPI_SPITF, | |
244 | swab16p(tx_buf + espi->tx_pos)); | |
245 | espi->tx_pos += 2; | |
246 | tx_left -= 2; | |
247 | tx_fifo_avail -= 2; | |
54731265 | 248 | } else { |
05823432 HK |
249 | if (!tx_buf) |
250 | fsl_espi_write_reg8(espi, ESPI_SPITF, 0); | |
251 | else | |
252 | fsl_espi_write_reg8(espi, ESPI_SPITF, | |
253 | *(u8 *)(tx_buf + espi->tx_pos)); | |
254 | espi->tx_pos += 1; | |
255 | tx_left -= 1; | |
54731265 HK |
256 | tx_fifo_avail -= 1; |
257 | } | |
05823432 HK |
258 | } |
259 | ||
260 | if (!tx_left) { | |
261 | /* Last transfer finished, in rxskip mode only one is needed */ | |
262 | if (list_is_last(&espi->tx_t->transfer_list, | |
263 | espi->m_transfers) || espi->rxskip) { | |
264 | espi->tx_done = true; | |
265 | return; | |
266 | } | |
267 | espi->tx_t = list_next_entry(espi->tx_t, transfer_list); | |
268 | espi->tx_pos = 0; | |
269 | /* continue with next transfer if tx fifo is not full */ | |
270 | if (tx_fifo_avail) | |
271 | goto start; | |
272 | } | |
54731265 HK |
273 | } |
274 | ||
35ab046b | 275 | static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events) |
f05689a6 HK |
276 | { |
277 | u32 rx_fifo_avail = SPIE_RXCNT(events); | |
dcb425f3 HK |
278 | unsigned int rx_left; |
279 | void *rx_buf; | |
f05689a6 | 280 | |
dcb425f3 HK |
281 | start: |
282 | rx_left = espi->rx_t->len - espi->rx_pos; | |
283 | rx_buf = espi->rx_t->rx_buf; | |
284 | while (rx_fifo_avail >= min(4U, rx_left) && rx_left) { | |
285 | if (rx_left >= 4) { | |
286 | u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF); | |
287 | ||
288 | if (rx_buf && espi->swab) | |
289 | *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val); | |
290 | else if (rx_buf) | |
291 | *(u32 *)(rx_buf + espi->rx_pos) = val; | |
292 | espi->rx_pos += 4; | |
293 | rx_left -= 4; | |
f05689a6 | 294 | rx_fifo_avail -= 4; |
dcb425f3 HK |
295 | } else if (rx_left >= 2 && rx_buf && espi->swab) { |
296 | u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF); | |
297 | ||
298 | *(u16 *)(rx_buf + espi->rx_pos) = swab16(val); | |
299 | espi->rx_pos += 2; | |
300 | rx_left -= 2; | |
301 | rx_fifo_avail -= 2; | |
f05689a6 | 302 | } else { |
dcb425f3 HK |
303 | u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF); |
304 | ||
305 | if (rx_buf) | |
306 | *(u8 *)(rx_buf + espi->rx_pos) = val; | |
307 | espi->rx_pos += 1; | |
308 | rx_left -= 1; | |
f05689a6 HK |
309 | rx_fifo_avail -= 1; |
310 | } | |
dcb425f3 HK |
311 | } |
312 | ||
313 | if (!rx_left) { | |
314 | if (list_is_last(&espi->rx_t->transfer_list, | |
315 | espi->m_transfers)) { | |
316 | espi->rx_done = true; | |
317 | return; | |
318 | } | |
319 | espi->rx_t = list_next_entry(espi->rx_t, transfer_list); | |
320 | espi->rx_pos = 0; | |
321 | /* continue with next transfer if rx fifo is not empty */ | |
322 | if (rx_fifo_avail) | |
323 | goto start; | |
324 | } | |
f05689a6 HK |
325 | } |
326 | ||
ea616ee2 | 327 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
328 | struct spi_transfer *t) |
329 | { | |
35ab046b | 330 | struct fsl_espi *espi = spi_master_get_devdata(spi->master); |
d198ebfb | 331 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
73aaf158 | 332 | u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz; |
219b5e3b | 333 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
8f3086d2 | 334 | u32 hw_mode_old = cs->hw_mode; |
8b60d6c2 | 335 | |
8b60d6c2 MH |
336 | /* mask out bits we are going to set */ |
337 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
338 | ||
a755af52 | 339 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 | 340 | |
35ab046b | 341 | pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1; |
73aaf158 PZ |
342 | |
343 | if (pm > 15) { | |
8b60d6c2 | 344 | cs->hw_mode |= CSMODE_DIV16; |
35ab046b | 345 | pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1; |
8b60d6c2 | 346 | } |
8b60d6c2 MH |
347 | |
348 | cs->hw_mode |= CSMODE_PM(pm); | |
349 | ||
8f3086d2 HK |
350 | /* don't write the mode register if the mode doesn't change */ |
351 | if (cs->hw_mode != hw_mode_old) | |
35ab046b | 352 | fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select), |
8f3086d2 | 353 | cs->hw_mode); |
8b60d6c2 MH |
354 | } |
355 | ||
8b60d6c2 MH |
356 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
357 | { | |
35ab046b | 358 | struct fsl_espi *espi = spi_master_get_devdata(spi->master); |
dcb425f3 | 359 | unsigned int rx_len = t->len; |
aca75157 | 360 | u32 mask, spcom; |
8b60d6c2 MH |
361 | int ret; |
362 | ||
35ab046b | 363 | reinit_completion(&espi->done); |
8b60d6c2 MH |
364 | |
365 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
aca75157 HK |
366 | spcom = SPCOM_CS(spi->chip_select); |
367 | spcom |= SPCOM_TRANLEN(t->len - 1); | |
368 | ||
369 | /* configure RXSKIP mode */ | |
35ab046b HK |
370 | if (espi->rxskip) { |
371 | spcom |= SPCOM_RXSKIP(espi->rxskip); | |
dcb425f3 | 372 | rx_len = t->len - espi->rxskip; |
8263cb33 HK |
373 | if (t->rx_nbits == SPI_NBITS_DUAL) |
374 | spcom |= SPCOM_DO; | |
aca75157 HK |
375 | } |
376 | ||
35ab046b | 377 | fsl_espi_write_reg(espi, ESPI_SPCOM, spcom); |
8b60d6c2 | 378 | |
e508cea4 HK |
379 | /* enable interrupts */ |
380 | mask = SPIM_DON; | |
dcb425f3 | 381 | if (rx_len > FSL_ESPI_FIFO_SIZE) |
e508cea4 | 382 | mask |= SPIM_RXT; |
35ab046b | 383 | fsl_espi_write_reg(espi, ESPI_SPIM, mask); |
5bcc6a2f | 384 | |
54731265 | 385 | /* Prevent filling the fifo from getting interrupted */ |
35ab046b HK |
386 | spin_lock_irq(&espi->lock); |
387 | fsl_espi_fill_tx_fifo(espi, 0); | |
388 | spin_unlock_irq(&espi->lock); | |
8b60d6c2 | 389 | |
aa70e567 | 390 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
35ab046b | 391 | ret = wait_for_completion_timeout(&espi->done, 2 * HZ); |
aa70e567 | 392 | if (ret == 0) |
05823432 | 393 | dev_err(espi->dev, "Transfer timed out!\n"); |
8b60d6c2 MH |
394 | |
395 | /* disable rx ints */ | |
35ab046b | 396 | fsl_espi_write_reg(espi, ESPI_SPIM, 0); |
8b60d6c2 | 397 | |
db1b049f | 398 | return ret == 0 ? -ETIMEDOUT : 0; |
8b60d6c2 MH |
399 | } |
400 | ||
38d003f1 | 401 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 402 | { |
35ab046b | 403 | struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 404 | struct spi_device *spi = m->spi; |
38d003f1 | 405 | int ret; |
8b60d6c2 | 406 | |
e1cdee73 HK |
407 | /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ |
408 | espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8; | |
409 | ||
05823432 HK |
410 | espi->m_transfers = &m->transfers; |
411 | espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer, | |
412 | transfer_list); | |
413 | espi->tx_pos = 0; | |
414 | espi->tx_done = false; | |
dcb425f3 HK |
415 | espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer, |
416 | transfer_list); | |
417 | espi->rx_pos = 0; | |
418 | espi->rx_done = false; | |
05823432 | 419 | |
35ab046b HK |
420 | espi->rxskip = fsl_espi_check_rxskip_mode(m); |
421 | if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) { | |
422 | dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n"); | |
8263cb33 HK |
423 | return -EINVAL; |
424 | } | |
425 | ||
dcb425f3 HK |
426 | /* In RXSKIP mode skip first transfer for reads */ |
427 | if (espi->rxskip) | |
428 | espi->rx_t = list_next_entry(espi->rx_t, transfer_list); | |
429 | ||
faceef39 | 430 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 431 | |
06af115d | 432 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 433 | |
faceef39 HK |
434 | if (trans->delay_usecs) |
435 | udelay(trans->delay_usecs); | |
8b60d6c2 | 436 | |
e33a3ade | 437 | return ret; |
8b60d6c2 MH |
438 | } |
439 | ||
c592becb HK |
440 | static int fsl_espi_do_one_msg(struct spi_master *master, |
441 | struct spi_message *m) | |
8b60d6c2 | 442 | { |
8263cb33 | 443 | unsigned int delay_usecs = 0, rx_nbits = 0; |
faceef39 | 444 | struct spi_transfer *t, trans = {}; |
e33a3ade | 445 | int ret; |
8b60d6c2 | 446 | |
d3152cf1 HK |
447 | ret = fsl_espi_check_message(m); |
448 | if (ret) | |
449 | goto out; | |
450 | ||
8b60d6c2 | 451 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
452 | if (t->delay_usecs > delay_usecs) |
453 | delay_usecs = t->delay_usecs; | |
8263cb33 HK |
454 | if (t->rx_nbits > rx_nbits) |
455 | rx_nbits = t->rx_nbits; | |
8b60d6c2 MH |
456 | } |
457 | ||
96361faf HK |
458 | t = list_first_entry(&m->transfers, struct spi_transfer, |
459 | transfer_list); | |
460 | ||
06af115d | 461 | trans.len = m->frame_length; |
96361faf HK |
462 | trans.speed_hz = t->speed_hz; |
463 | trans.bits_per_word = t->bits_per_word; | |
464 | trans.delay_usecs = delay_usecs; | |
8263cb33 | 465 | trans.rx_nbits = rx_nbits; |
8b60d6c2 | 466 | |
06af115d HK |
467 | if (trans.len) |
468 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 469 | |
faceef39 | 470 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 471 | out: |
0319d499 HK |
472 | if (m->status == -EINPROGRESS) |
473 | m->status = ret; | |
474 | ||
c592becb | 475 | spi_finalize_current_message(master); |
0319d499 HK |
476 | |
477 | return ret; | |
8b60d6c2 MH |
478 | } |
479 | ||
480 | static int fsl_espi_setup(struct spi_device *spi) | |
481 | { | |
35ab046b | 482 | struct fsl_espi *espi; |
8b60d6c2 | 483 | u32 loop_mode; |
219b5e3b | 484 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 | 485 | |
8b60d6c2 | 486 | if (!cs) { |
d9f26748 | 487 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
488 | if (!cs) |
489 | return -ENOMEM; | |
d9f26748 | 490 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
491 | } |
492 | ||
35ab046b | 493 | espi = spi_master_get_devdata(spi->master); |
8b60d6c2 | 494 | |
35ab046b | 495 | pm_runtime_get_sync(espi->dev); |
e9abb4db | 496 | |
35ab046b | 497 | cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select)); |
8b60d6c2 MH |
498 | /* mask out bits we are going to set */ |
499 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
500 | | CSMODE_REV); | |
501 | ||
502 | if (spi->mode & SPI_CPHA) | |
503 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
504 | if (spi->mode & SPI_CPOL) | |
505 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
506 | if (!(spi->mode & SPI_LSB_FIRST)) | |
507 | cs->hw_mode |= CSMODE_REV; | |
508 | ||
509 | /* Handle the loop mode */ | |
35ab046b | 510 | loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE); |
8b60d6c2 MH |
511 | loop_mode &= ~SPMODE_LOOP; |
512 | if (spi->mode & SPI_LOOP) | |
513 | loop_mode |= SPMODE_LOOP; | |
35ab046b | 514 | fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 515 | |
ea616ee2 | 516 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db | 517 | |
35ab046b HK |
518 | pm_runtime_mark_last_busy(espi->dev); |
519 | pm_runtime_put_autosuspend(espi->dev); | |
e9abb4db | 520 | |
8b60d6c2 MH |
521 | return 0; |
522 | } | |
523 | ||
d9f26748 AL |
524 | static void fsl_espi_cleanup(struct spi_device *spi) |
525 | { | |
219b5e3b | 526 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
d9f26748 AL |
527 | |
528 | kfree(cs); | |
529 | spi_set_ctldata(spi, NULL); | |
530 | } | |
531 | ||
35ab046b | 532 | static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events) |
8b60d6c2 | 533 | { |
dcb425f3 | 534 | if (!espi->rx_done) |
35ab046b | 535 | fsl_espi_read_rx_fifo(espi, events); |
8b60d6c2 | 536 | |
05823432 | 537 | if (!espi->tx_done) |
35ab046b | 538 | fsl_espi_fill_tx_fifo(espi, events); |
8b60d6c2 | 539 | |
dcb425f3 | 540 | if (!espi->tx_done || !espi->rx_done) |
db1b049f HK |
541 | return; |
542 | ||
543 | /* we're done, but check for errors before returning */ | |
35ab046b | 544 | events = fsl_espi_read_reg(espi, ESPI_SPIE); |
db1b049f HK |
545 | |
546 | if (!(events & SPIE_DON)) | |
35ab046b | 547 | dev_err(espi->dev, |
db1b049f HK |
548 | "Transfer done but SPIE_DON isn't set!\n"); |
549 | ||
550 | if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) | |
35ab046b | 551 | dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); |
db1b049f | 552 | |
35ab046b | 553 | complete(&espi->done); |
8b60d6c2 MH |
554 | } |
555 | ||
556 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
557 | { | |
35ab046b | 558 | struct fsl_espi *espi = context_data; |
8b60d6c2 MH |
559 | u32 events; |
560 | ||
35ab046b | 561 | spin_lock(&espi->lock); |
54731265 | 562 | |
8b60d6c2 | 563 | /* Get interrupt events(tx/rx) */ |
35ab046b | 564 | events = fsl_espi_read_reg(espi, ESPI_SPIE); |
54731265 | 565 | if (!events) { |
35ab046b | 566 | spin_unlock(&espi->lock); |
35f5d71e | 567 | return IRQ_NONE; |
54731265 | 568 | } |
8b60d6c2 | 569 | |
35ab046b | 570 | dev_vdbg(espi->dev, "%s: events %x\n", __func__, events); |
8b60d6c2 | 571 | |
35ab046b | 572 | fsl_espi_cpu_irq(espi, events); |
8b60d6c2 | 573 | |
35f5d71e | 574 | /* Clear the events */ |
35ab046b | 575 | fsl_espi_write_reg(espi, ESPI_SPIE, events); |
35f5d71e | 576 | |
35ab046b | 577 | spin_unlock(&espi->lock); |
54731265 | 578 | |
35f5d71e | 579 | return IRQ_HANDLED; |
8b60d6c2 MH |
580 | } |
581 | ||
e9abb4db HK |
582 | #ifdef CONFIG_PM |
583 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 584 | { |
e9abb4db | 585 | struct spi_master *master = dev_get_drvdata(dev); |
35ab046b | 586 | struct fsl_espi *espi = spi_master_get_devdata(master); |
75506d0e HK |
587 | u32 regval; |
588 | ||
35ab046b | 589 | regval = fsl_espi_read_reg(espi, ESPI_SPMODE); |
75506d0e | 590 | regval &= ~SPMODE_ENABLE; |
35ab046b | 591 | fsl_espi_write_reg(espi, ESPI_SPMODE, regval); |
75506d0e HK |
592 | |
593 | return 0; | |
594 | } | |
595 | ||
e9abb4db | 596 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 597 | { |
e9abb4db | 598 | struct spi_master *master = dev_get_drvdata(dev); |
35ab046b | 599 | struct fsl_espi *espi = spi_master_get_devdata(master); |
75506d0e HK |
600 | u32 regval; |
601 | ||
35ab046b | 602 | regval = fsl_espi_read_reg(espi, ESPI_SPMODE); |
75506d0e | 603 | regval |= SPMODE_ENABLE; |
35ab046b | 604 | fsl_espi_write_reg(espi, ESPI_SPMODE, regval); |
75506d0e HK |
605 | |
606 | return 0; | |
607 | } | |
e9abb4db | 608 | #endif |
75506d0e | 609 | |
02a595d5 | 610 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
611 | { |
612 | return SPCOM_TRANLEN_MAX; | |
613 | } | |
614 | ||
456c742b HK |
615 | static void fsl_espi_init_regs(struct device *dev, bool initial) |
616 | { | |
617 | struct spi_master *master = dev_get_drvdata(dev); | |
35ab046b | 618 | struct fsl_espi *espi = spi_master_get_devdata(master); |
456c742b HK |
619 | struct device_node *nc; |
620 | u32 csmode, cs, prop; | |
621 | int ret; | |
622 | ||
623 | /* SPI controller initializations */ | |
35ab046b HK |
624 | fsl_espi_write_reg(espi, ESPI_SPMODE, 0); |
625 | fsl_espi_write_reg(espi, ESPI_SPIM, 0); | |
626 | fsl_espi_write_reg(espi, ESPI_SPCOM, 0); | |
627 | fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff); | |
456c742b HK |
628 | |
629 | /* Init eSPI CS mode register */ | |
630 | for_each_available_child_of_node(master->dev.of_node, nc) { | |
631 | /* get chip select */ | |
632 | ret = of_property_read_u32(nc, "reg", &cs); | |
633 | if (ret || cs >= master->num_chipselect) | |
634 | continue; | |
635 | ||
636 | csmode = CSMODE_INIT_VAL; | |
637 | ||
638 | /* check if CSBEF is set in device tree */ | |
639 | ret = of_property_read_u32(nc, "fsl,csbef", &prop); | |
640 | if (!ret) { | |
641 | csmode &= ~(CSMODE_BEF(0xf)); | |
642 | csmode |= CSMODE_BEF(prop); | |
643 | } | |
644 | ||
645 | /* check if CSAFT is set in device tree */ | |
646 | ret = of_property_read_u32(nc, "fsl,csaft", &prop); | |
647 | if (!ret) { | |
648 | csmode &= ~(CSMODE_AFT(0xf)); | |
649 | csmode |= CSMODE_AFT(prop); | |
650 | } | |
651 | ||
35ab046b | 652 | fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode); |
456c742b HK |
653 | |
654 | if (initial) | |
655 | dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); | |
656 | } | |
657 | ||
658 | /* Enable SPI interface */ | |
35ab046b | 659 | fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE); |
456c742b HK |
660 | } |
661 | ||
604042af | 662 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
7454346b | 663 | unsigned int irq, unsigned int num_cs) |
8b60d6c2 | 664 | { |
8b60d6c2 | 665 | struct spi_master *master; |
35ab046b | 666 | struct fsl_espi *espi; |
b497eb02 | 667 | int ret; |
8b60d6c2 | 668 | |
35ab046b | 669 | master = spi_alloc_master(dev, sizeof(struct fsl_espi)); |
604042af HK |
670 | if (!master) |
671 | return -ENOMEM; | |
8b60d6c2 MH |
672 | |
673 | dev_set_drvdata(dev, master); | |
674 | ||
7cb55577 HK |
675 | master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
676 | SPI_LSB_FIRST | SPI_LOOP; | |
677 | master->dev.of_node = dev->of_node; | |
24778be2 | 678 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 679 | master->setup = fsl_espi_setup; |
d9f26748 | 680 | master->cleanup = fsl_espi_cleanup; |
c592becb | 681 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 682 | master->auto_runtime_pm = true; |
02a595d5 | 683 | master->max_message_size = fsl_espi_max_message_size; |
7454346b | 684 | master->num_chipselect = num_cs; |
8b60d6c2 | 685 | |
35ab046b HK |
686 | espi = spi_master_get_devdata(master); |
687 | spin_lock_init(&espi->lock); | |
8b60d6c2 | 688 | |
35ab046b HK |
689 | espi->dev = dev; |
690 | espi->spibrg = fsl_get_sys_freq(); | |
691 | if (espi->spibrg == -1) { | |
7cb55577 HK |
692 | dev_err(dev, "Can't get sys frequency!\n"); |
693 | ret = -EINVAL; | |
694 | goto err_probe; | |
695 | } | |
f254e65c HK |
696 | /* determined by clock divider fields DIV16/PM in register SPMODEx */ |
697 | master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16); | |
698 | master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4); | |
7cb55577 | 699 | |
35ab046b | 700 | init_completion(&espi->done); |
7cb55577 | 701 | |
35ab046b HK |
702 | espi->reg_base = devm_ioremap_resource(dev, mem); |
703 | if (IS_ERR(espi->reg_base)) { | |
704 | ret = PTR_ERR(espi->reg_base); | |
8b60d6c2 MH |
705 | goto err_probe; |
706 | } | |
707 | ||
8b60d6c2 | 708 | /* Register for SPI Interrupt */ |
35ab046b | 709 | ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi); |
8b60d6c2 | 710 | if (ret) |
4178b6b1 | 711 | goto err_probe; |
8b60d6c2 | 712 | |
456c742b | 713 | fsl_espi_init_regs(dev, true); |
8b60d6c2 | 714 | |
e9abb4db HK |
715 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
716 | pm_runtime_use_autosuspend(dev); | |
717 | pm_runtime_set_active(dev); | |
718 | pm_runtime_enable(dev); | |
719 | pm_runtime_get_sync(dev); | |
720 | ||
4178b6b1 | 721 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 722 | if (ret < 0) |
e9abb4db | 723 | goto err_pm; |
8b60d6c2 | 724 | |
35ab046b | 725 | dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq); |
8b60d6c2 | 726 | |
e9abb4db HK |
727 | pm_runtime_mark_last_busy(dev); |
728 | pm_runtime_put_autosuspend(dev); | |
729 | ||
604042af | 730 | return 0; |
8b60d6c2 | 731 | |
e9abb4db HK |
732 | err_pm: |
733 | pm_runtime_put_noidle(dev); | |
734 | pm_runtime_disable(dev); | |
735 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
736 | err_probe: |
737 | spi_master_put(master); | |
604042af | 738 | return ret; |
8b60d6c2 MH |
739 | } |
740 | ||
741 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
742 | { | |
743 | struct device_node *np = dev->of_node; | |
b497eb02 HK |
744 | u32 num_cs; |
745 | int ret; | |
8b60d6c2 | 746 | |
b497eb02 HK |
747 | ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); |
748 | if (ret) { | |
8b60d6c2 | 749 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); |
7454346b | 750 | return 0; |
8b60d6c2 MH |
751 | } |
752 | ||
7454346b | 753 | return num_cs; |
8b60d6c2 MH |
754 | } |
755 | ||
fd4a319b | 756 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
757 | { |
758 | struct device *dev = &ofdev->dev; | |
759 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 760 | struct resource mem; |
7454346b | 761 | unsigned int irq, num_cs; |
acf69219 | 762 | int ret; |
8b60d6c2 | 763 | |
e3ce4f44 HK |
764 | if (of_property_read_bool(np, "mode")) { |
765 | dev_err(dev, "mode property is not supported on ESPI!\n"); | |
766 | return -EINVAL; | |
767 | } | |
768 | ||
7454346b HK |
769 | num_cs = of_fsl_espi_get_chipselects(dev); |
770 | if (!num_cs) | |
771 | return -EINVAL; | |
8b60d6c2 MH |
772 | |
773 | ret = of_address_to_resource(np, 0, &mem); | |
774 | if (ret) | |
acf69219 | 775 | return ret; |
8b60d6c2 | 776 | |
f7578496 | 777 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
778 | if (!irq) |
779 | return -EINVAL; | |
8b60d6c2 | 780 | |
7454346b | 781 | return fsl_espi_probe(dev, &mem, irq, num_cs); |
8b60d6c2 MH |
782 | } |
783 | ||
e9abb4db HK |
784 | static int of_fsl_espi_remove(struct platform_device *dev) |
785 | { | |
786 | pm_runtime_disable(&dev->dev); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
714bb654 HZ |
791 | #ifdef CONFIG_PM_SLEEP |
792 | static int of_fsl_espi_suspend(struct device *dev) | |
793 | { | |
794 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
795 | int ret; |
796 | ||
714bb654 HZ |
797 | ret = spi_master_suspend(master); |
798 | if (ret) { | |
799 | dev_warn(dev, "cannot suspend master\n"); | |
800 | return ret; | |
801 | } | |
802 | ||
a9a813dd | 803 | return pm_runtime_force_suspend(dev); |
714bb654 HZ |
804 | } |
805 | ||
806 | static int of_fsl_espi_resume(struct device *dev) | |
807 | { | |
714bb654 | 808 | struct spi_master *master = dev_get_drvdata(dev); |
456c742b | 809 | int ret; |
714bb654 | 810 | |
456c742b | 811 | fsl_espi_init_regs(dev, false); |
714bb654 | 812 | |
e9abb4db HK |
813 | ret = pm_runtime_force_resume(dev); |
814 | if (ret < 0) | |
815 | return ret; | |
816 | ||
714bb654 HZ |
817 | return spi_master_resume(master); |
818 | } | |
819 | #endif /* CONFIG_PM_SLEEP */ | |
820 | ||
821 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
822 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
823 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
824 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
825 | }; | |
826 | ||
8b60d6c2 MH |
827 | static const struct of_device_id of_fsl_espi_match[] = { |
828 | { .compatible = "fsl,mpc8536-espi" }, | |
829 | {} | |
830 | }; | |
831 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
832 | ||
18d306d1 | 833 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
834 | .driver = { |
835 | .name = "fsl_espi", | |
8b60d6c2 | 836 | .of_match_table = of_fsl_espi_match, |
714bb654 | 837 | .pm = &espi_pm, |
8b60d6c2 MH |
838 | }, |
839 | .probe = of_fsl_espi_probe, | |
e9abb4db | 840 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 841 | }; |
940ab889 | 842 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
843 | |
844 | MODULE_AUTHOR("Mingkai Hu"); | |
845 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
846 | MODULE_LICENSE("GPL"); |