Commit | Line | Data |
---|---|---|
8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
46afd38b HK |
29 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
30 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
31 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
32 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
33 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
34 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
35 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
36 | ||
37 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 38 | |
8b60d6c2 | 39 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
40 | #define SPMODE_ENABLE BIT(31) |
41 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
42 | #define SPMODE_TXTHR(x) ((x) << 8) |
43 | #define SPMODE_RXTHR(x) ((x) << 0) | |
44 | ||
45 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
46 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
47 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
48 | #define CSMODE_REV BIT(29) | |
49 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 50 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 51 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
52 | #define CSMODE_LEN(x) ((x) << 16) |
53 | #define CSMODE_BEF(x) ((x) << 12) | |
54 | #define CSMODE_AFT(x) ((x) << 8) | |
55 | #define CSMODE_CG(x) ((x) << 3) | |
56 | ||
57 | /* Default mode/csmode for eSPI controller */ | |
58 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) | |
59 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ | |
60 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
61 | ||
62 | /* SPIE register values */ | |
8b60d6c2 MH |
63 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
64 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
65 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
66 | #define SPIE_DON BIT(14) /* TX done */ | |
67 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
68 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
69 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
70 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
71 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
72 | ||
73 | /* SPIM register values */ | |
74 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
75 | #define SPIM_DON BIT(14) /* TX done */ | |
76 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
77 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
78 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
79 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
80 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
81 | |
82 | /* SPCOM register values */ | |
83 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
84 | #define SPCOM_DO BIT(28) /* Dual output */ |
85 | #define SPCOM_TO BIT(27) /* TX only */ | |
86 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 87 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 88 | |
5cfa1e4e | 89 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 90 | |
e9abb4db HK |
91 | #define AUTOSUSPEND_TIMEOUT 2000 |
92 | ||
46afd38b HK |
93 | static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset) |
94 | { | |
95 | return ioread32be(mspi->reg_base + offset); | |
96 | } | |
97 | ||
98 | static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset) | |
99 | { | |
100 | return ioread8(mspi->reg_base + offset); | |
101 | } | |
102 | ||
103 | static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset, | |
104 | u32 val) | |
105 | { | |
106 | iowrite32be(val, mspi->reg_base + offset); | |
107 | } | |
108 | ||
109 | static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset, | |
110 | u8 val) | |
111 | { | |
112 | iowrite8(val, mspi->reg_base + offset); | |
113 | } | |
114 | ||
cce7e3a2 HK |
115 | static void fsl_espi_copy_to_buf(struct spi_message *m, |
116 | struct mpc8xxx_spi *mspi) | |
7c159aa8 | 117 | { |
7c159aa8 HK |
118 | struct spi_transfer *t; |
119 | u8 *buf = mspi->local_buf; | |
120 | ||
121 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
cce7e3a2 | 122 | if (t->tx_buf) |
7c159aa8 | 123 | memcpy(buf, t->tx_buf, t->len); |
cce7e3a2 | 124 | else |
7c159aa8 | 125 | memset(buf, 0, t->len); |
7c159aa8 HK |
126 | buf += t->len; |
127 | } | |
cce7e3a2 HK |
128 | } |
129 | ||
130 | static void fsl_espi_copy_from_buf(struct spi_message *m, | |
131 | struct mpc8xxx_spi *mspi) | |
132 | { | |
133 | struct spi_transfer *t; | |
134 | u8 *buf = mspi->local_buf; | |
7c159aa8 | 135 | |
cce7e3a2 HK |
136 | list_for_each_entry(t, &m->transfers, transfer_list) { |
137 | if (t->rx_buf) | |
138 | memcpy(t->rx_buf, buf, t->len); | |
139 | buf += t->len; | |
140 | } | |
7c159aa8 HK |
141 | } |
142 | ||
d3152cf1 HK |
143 | static int fsl_espi_check_message(struct spi_message *m) |
144 | { | |
145 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); | |
146 | struct spi_transfer *t, *first; | |
147 | ||
148 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
149 | dev_err(mspi->dev, "message too long, size is %u bytes\n", | |
150 | m->frame_length); | |
151 | return -EMSGSIZE; | |
152 | } | |
153 | ||
154 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
155 | transfer_list); | |
156 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
157 | if (first->bits_per_word != t->bits_per_word || | |
158 | first->speed_hz != t->speed_hz) { | |
159 | dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); | |
160 | return -EINVAL; | |
161 | } | |
162 | } | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
8b60d6c2 MH |
167 | static void fsl_espi_change_mode(struct spi_device *spi) |
168 | { | |
169 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
170 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
8b60d6c2 MH |
171 | u32 tmp; |
172 | unsigned long flags; | |
173 | ||
174 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
175 | local_irq_save(flags); | |
176 | ||
177 | /* Turn off SPI unit prior changing mode */ | |
46afd38b HK |
178 | tmp = fsl_espi_read_reg(mspi, ESPI_SPMODE); |
179 | fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp & ~SPMODE_ENABLE); | |
180 | fsl_espi_write_reg(mspi, ESPI_SPMODEx(spi->chip_select), | |
181 | cs->hw_mode); | |
182 | fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp); | |
8b60d6c2 MH |
183 | |
184 | local_irq_restore(flags); | |
185 | } | |
186 | ||
187 | static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi) | |
188 | { | |
189 | u32 data; | |
190 | u16 data_h; | |
191 | u16 data_l; | |
192 | const u32 *tx = mpc8xxx_spi->tx; | |
193 | ||
194 | if (!tx) | |
195 | return 0; | |
196 | ||
197 | data = *tx++ << mpc8xxx_spi->tx_shift; | |
198 | data_l = data & 0xffff; | |
199 | data_h = (data >> 16) & 0xffff; | |
200 | swab16s(&data_l); | |
201 | swab16s(&data_h); | |
202 | data = data_h | data_l; | |
203 | ||
204 | mpc8xxx_spi->tx = tx; | |
205 | return data; | |
206 | } | |
207 | ||
ea616ee2 | 208 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
209 | struct spi_transfer *t) |
210 | { | |
211 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
d198ebfb HK |
212 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
213 | u32 hz = t ? t->speed_hz : spi->max_speed_hz; | |
8b60d6c2 | 214 | u8 pm; |
8b60d6c2 MH |
215 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
216 | ||
8b60d6c2 MH |
217 | cs->rx_shift = 0; |
218 | cs->tx_shift = 0; | |
219 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; | |
220 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
221 | if (bits_per_word <= 8) { | |
222 | cs->rx_shift = 8 - bits_per_word; | |
51faed69 | 223 | } else { |
8b60d6c2 MH |
224 | cs->rx_shift = 16 - bits_per_word; |
225 | if (spi->mode & SPI_LSB_FIRST) | |
226 | cs->get_tx = fsl_espi_tx_buf_lsb; | |
8b60d6c2 MH |
227 | } |
228 | ||
229 | mpc8xxx_spi->rx_shift = cs->rx_shift; | |
230 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
231 | mpc8xxx_spi->get_rx = cs->get_rx; | |
232 | mpc8xxx_spi->get_tx = cs->get_tx; | |
233 | ||
8b60d6c2 MH |
234 | /* mask out bits we are going to set */ |
235 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
236 | ||
a755af52 | 237 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 MH |
238 | |
239 | if ((mpc8xxx_spi->spibrg / hz) > 64) { | |
240 | cs->hw_mode |= CSMODE_DIV16; | |
35faa55c | 241 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); |
8b60d6c2 | 242 | |
87bf5ab8 | 243 | WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " |
8b60d6c2 | 244 | "Will use %d Hz instead.\n", dev_name(&spi->dev), |
87bf5ab8 SAS |
245 | hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); |
246 | if (pm > 33) | |
247 | pm = 33; | |
8b60d6c2 | 248 | } else { |
35faa55c | 249 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); |
8b60d6c2 MH |
250 | } |
251 | if (pm) | |
252 | pm--; | |
87bf5ab8 SAS |
253 | if (pm < 2) |
254 | pm = 2; | |
8b60d6c2 MH |
255 | |
256 | cs->hw_mode |= CSMODE_PM(pm); | |
257 | ||
258 | fsl_espi_change_mode(spi); | |
8b60d6c2 MH |
259 | } |
260 | ||
8b60d6c2 MH |
261 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
262 | { | |
263 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
5bcc6a2f | 264 | u32 word; |
8b60d6c2 MH |
265 | int ret; |
266 | ||
8b60d6c2 | 267 | mpc8xxx_spi->len = t->len; |
5bcc6a2f | 268 | mpc8xxx_spi->count = roundup(t->len, 4) / 4; |
8b60d6c2 MH |
269 | |
270 | mpc8xxx_spi->tx = t->tx_buf; | |
271 | mpc8xxx_spi->rx = t->rx_buf; | |
272 | ||
16735d02 | 273 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
274 | |
275 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
46afd38b | 276 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, |
8b60d6c2 MH |
277 | (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); |
278 | ||
5bcc6a2f | 279 | /* enable rx ints */ |
81abc2ec | 280 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, SPIM_RNE); |
5bcc6a2f HK |
281 | |
282 | /* transmit word */ | |
283 | word = mpc8xxx_spi->get_tx(mpc8xxx_spi); | |
46afd38b | 284 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPITF, word); |
8b60d6c2 | 285 | |
aa70e567 NH |
286 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
287 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
288 | if (ret == 0) | |
289 | dev_err(mpc8xxx_spi->dev, | |
290 | "Transaction hanging up (left %d bytes)\n", | |
291 | mpc8xxx_spi->count); | |
8b60d6c2 MH |
292 | |
293 | /* disable rx ints */ | |
46afd38b | 294 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); |
8b60d6c2 | 295 | |
84ccfc37 | 296 | return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0; |
8b60d6c2 MH |
297 | } |
298 | ||
38d003f1 | 299 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 300 | { |
38d003f1 | 301 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 302 | struct spi_device *spi = m->spi; |
38d003f1 | 303 | int ret; |
8b60d6c2 | 304 | |
38d003f1 | 305 | fsl_espi_copy_to_buf(m, mspi); |
faceef39 | 306 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 307 | |
06af115d | 308 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 309 | |
faceef39 HK |
310 | if (trans->delay_usecs) |
311 | udelay(trans->delay_usecs); | |
8b60d6c2 | 312 | |
8b60d6c2 | 313 | fsl_espi_setup_transfer(spi, NULL); |
e33a3ade | 314 | |
cce7e3a2 HK |
315 | if (!ret) |
316 | fsl_espi_copy_from_buf(m, mspi); | |
e33a3ade HK |
317 | |
318 | return ret; | |
8b60d6c2 MH |
319 | } |
320 | ||
c592becb HK |
321 | static int fsl_espi_do_one_msg(struct spi_master *master, |
322 | struct spi_message *m) | |
8b60d6c2 | 323 | { |
96361faf | 324 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
06af115d | 325 | unsigned int delay_usecs = 0; |
faceef39 | 326 | struct spi_transfer *t, trans = {}; |
e33a3ade | 327 | int ret; |
8b60d6c2 | 328 | |
d3152cf1 HK |
329 | ret = fsl_espi_check_message(m); |
330 | if (ret) | |
331 | goto out; | |
332 | ||
8b60d6c2 | 333 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
334 | if (t->delay_usecs > delay_usecs) |
335 | delay_usecs = t->delay_usecs; | |
8b60d6c2 MH |
336 | } |
337 | ||
96361faf HK |
338 | t = list_first_entry(&m->transfers, struct spi_transfer, |
339 | transfer_list); | |
340 | ||
06af115d | 341 | trans.len = m->frame_length; |
96361faf HK |
342 | trans.speed_hz = t->speed_hz; |
343 | trans.bits_per_word = t->bits_per_word; | |
344 | trans.delay_usecs = delay_usecs; | |
345 | trans.tx_buf = mspi->local_buf; | |
346 | trans.rx_buf = mspi->local_buf; | |
8b60d6c2 | 347 | |
06af115d HK |
348 | if (trans.len) |
349 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 350 | |
faceef39 | 351 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 352 | out: |
0319d499 HK |
353 | if (m->status == -EINPROGRESS) |
354 | m->status = ret; | |
355 | ||
c592becb | 356 | spi_finalize_current_message(master); |
0319d499 HK |
357 | |
358 | return ret; | |
8b60d6c2 MH |
359 | } |
360 | ||
361 | static int fsl_espi_setup(struct spi_device *spi) | |
362 | { | |
363 | struct mpc8xxx_spi *mpc8xxx_spi; | |
8b60d6c2 | 364 | u32 loop_mode; |
d9f26748 | 365 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
366 | |
367 | if (!spi->max_speed_hz) | |
368 | return -EINVAL; | |
369 | ||
370 | if (!cs) { | |
d9f26748 | 371 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
372 | if (!cs) |
373 | return -ENOMEM; | |
d9f26748 | 374 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
375 | } |
376 | ||
377 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
8b60d6c2 | 378 | |
e9abb4db HK |
379 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
380 | ||
46afd38b HK |
381 | cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi, |
382 | ESPI_SPMODEx(spi->chip_select)); | |
8b60d6c2 MH |
383 | /* mask out bits we are going to set */ |
384 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
385 | | CSMODE_REV); | |
386 | ||
387 | if (spi->mode & SPI_CPHA) | |
388 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
389 | if (spi->mode & SPI_CPOL) | |
390 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
391 | if (!(spi->mode & SPI_LSB_FIRST)) | |
392 | cs->hw_mode |= CSMODE_REV; | |
393 | ||
394 | /* Handle the loop mode */ | |
46afd38b | 395 | loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
8b60d6c2 MH |
396 | loop_mode &= ~SPMODE_LOOP; |
397 | if (spi->mode & SPI_LOOP) | |
398 | loop_mode |= SPMODE_LOOP; | |
46afd38b | 399 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 400 | |
ea616ee2 | 401 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
402 | |
403 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
404 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
405 | ||
8b60d6c2 MH |
406 | return 0; |
407 | } | |
408 | ||
d9f26748 AL |
409 | static void fsl_espi_cleanup(struct spi_device *spi) |
410 | { | |
411 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); | |
412 | ||
413 | kfree(cs); | |
414 | spi_set_ctldata(spi, NULL); | |
415 | } | |
416 | ||
10ed1e6d | 417 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 | 418 | { |
8b60d6c2 | 419 | /* We need handle RX first */ |
81abc2ec | 420 | if (events & SPIE_RNE) { |
e6289d63 MH |
421 | u32 rx_data, tmp; |
422 | u8 rx_data_8; | |
6319a680 | 423 | int rx_nr_bytes = 4; |
a12ddd60 | 424 | int ret; |
8b60d6c2 MH |
425 | |
426 | /* Spin until RX is done */ | |
a12ddd60 NH |
427 | if (SPIE_RXCNT(events) < min(4, mspi->len)) { |
428 | ret = spin_event_timeout( | |
429 | !(SPIE_RXCNT(events = | |
46afd38b | 430 | fsl_espi_read_reg(mspi, ESPI_SPIE)) < |
a12ddd60 NH |
431 | min(4, mspi->len)), |
432 | 10000, 0); /* 10 msec */ | |
433 | if (!ret) | |
434 | dev_err(mspi->dev, | |
435 | "tired waiting for SPIE_RXCNT\n"); | |
8b60d6c2 | 436 | } |
8b60d6c2 | 437 | |
e6289d63 | 438 | if (mspi->len >= 4) { |
46afd38b | 439 | rx_data = fsl_espi_read_reg(mspi, ESPI_SPIRF); |
6319a680 NH |
440 | } else if (mspi->len <= 0) { |
441 | dev_err(mspi->dev, | |
81abc2ec | 442 | "unexpected RX(SPIE_RNE) interrupt occurred,\n" |
6319a680 NH |
443 | "(local rxlen %d bytes, reg rxlen %d bytes)\n", |
444 | min(4, mspi->len), SPIE_RXCNT(events)); | |
445 | rx_nr_bytes = 0; | |
e6289d63 | 446 | } else { |
6319a680 | 447 | rx_nr_bytes = mspi->len; |
e6289d63 MH |
448 | tmp = mspi->len; |
449 | rx_data = 0; | |
450 | while (tmp--) { | |
46afd38b HK |
451 | rx_data_8 = fsl_espi_read_reg8(mspi, |
452 | ESPI_SPIRF); | |
e6289d63 MH |
453 | rx_data |= (rx_data_8 << (tmp * 8)); |
454 | } | |
455 | ||
456 | rx_data <<= (4 - mspi->len) * 8; | |
457 | } | |
458 | ||
6319a680 | 459 | mspi->len -= rx_nr_bytes; |
8b60d6c2 MH |
460 | |
461 | if (mspi->rx) | |
462 | mspi->get_rx(rx_data, mspi); | |
463 | } | |
464 | ||
81abc2ec | 465 | if (!(events & SPIE_TNF)) { |
8b60d6c2 MH |
466 | int ret; |
467 | ||
468 | /* spin until TX is done */ | |
46afd38b | 469 | ret = spin_event_timeout(((events = fsl_espi_read_reg( |
81abc2ec | 470 | mspi, ESPI_SPIE)) & SPIE_TNF), 1000, 0); |
8b60d6c2 | 471 | if (!ret) { |
81abc2ec | 472 | dev_err(mspi->dev, "tired waiting for SPIE_TNF\n"); |
7a0a1759 | 473 | complete(&mspi->done); |
8b60d6c2 MH |
474 | return; |
475 | } | |
476 | } | |
477 | ||
8b60d6c2 MH |
478 | mspi->count -= 1; |
479 | if (mspi->count) { | |
480 | u32 word = mspi->get_tx(mspi); | |
481 | ||
46afd38b | 482 | fsl_espi_write_reg(mspi, ESPI_SPITF, word); |
8b60d6c2 MH |
483 | } else { |
484 | complete(&mspi->done); | |
485 | } | |
486 | } | |
487 | ||
488 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
489 | { | |
490 | struct mpc8xxx_spi *mspi = context_data; | |
8b60d6c2 MH |
491 | u32 events; |
492 | ||
493 | /* Get interrupt events(tx/rx) */ | |
46afd38b | 494 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); |
35f5d71e HK |
495 | if (!events) |
496 | return IRQ_NONE; | |
8b60d6c2 MH |
497 | |
498 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
499 | ||
500 | fsl_espi_cpu_irq(mspi, events); | |
501 | ||
35f5d71e | 502 | /* Clear the events */ |
46afd38b | 503 | fsl_espi_write_reg(mspi, ESPI_SPIE, events); |
35f5d71e HK |
504 | |
505 | return IRQ_HANDLED; | |
8b60d6c2 MH |
506 | } |
507 | ||
e9abb4db HK |
508 | #ifdef CONFIG_PM |
509 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 510 | { |
e9abb4db HK |
511 | struct spi_master *master = dev_get_drvdata(dev); |
512 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
513 | u32 regval; |
514 | ||
46afd38b | 515 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 516 | regval &= ~SPMODE_ENABLE; |
46afd38b | 517 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
518 | |
519 | return 0; | |
520 | } | |
521 | ||
e9abb4db | 522 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 523 | { |
e9abb4db HK |
524 | struct spi_master *master = dev_get_drvdata(dev); |
525 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
526 | u32 regval; |
527 | ||
46afd38b | 528 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 529 | regval |= SPMODE_ENABLE; |
46afd38b | 530 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
531 | |
532 | return 0; | |
533 | } | |
e9abb4db | 534 | #endif |
75506d0e | 535 | |
02a595d5 | 536 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
537 | { |
538 | return SPCOM_TRANLEN_MAX; | |
539 | } | |
540 | ||
604042af HK |
541 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
542 | unsigned int irq) | |
8b60d6c2 | 543 | { |
8074cf06 | 544 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
545 | struct spi_master *master; |
546 | struct mpc8xxx_spi *mpc8xxx_spi; | |
d0fb47a5 JW |
547 | struct device_node *nc; |
548 | const __be32 *prop; | |
549 | u32 regval, csmode; | |
604042af | 550 | int i, len, ret; |
8b60d6c2 MH |
551 | |
552 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
604042af HK |
553 | if (!master) |
554 | return -ENOMEM; | |
8b60d6c2 MH |
555 | |
556 | dev_set_drvdata(dev, master); | |
557 | ||
c592becb | 558 | mpc8xxx_spi_probe(dev, mem, irq); |
8b60d6c2 | 559 | |
24778be2 | 560 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 561 | master->setup = fsl_espi_setup; |
d9f26748 | 562 | master->cleanup = fsl_espi_cleanup; |
c592becb | 563 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 564 | master->auto_runtime_pm = true; |
02a595d5 | 565 | master->max_message_size = fsl_espi_max_message_size; |
8b60d6c2 MH |
566 | |
567 | mpc8xxx_spi = spi_master_get_devdata(master); | |
8b60d6c2 | 568 | |
1423877b HK |
569 | mpc8xxx_spi->local_buf = |
570 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
571 | if (!mpc8xxx_spi->local_buf) { | |
572 | ret = -ENOMEM; | |
573 | goto err_probe; | |
574 | } | |
575 | ||
4178b6b1 | 576 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
577 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
578 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
579 | goto err_probe; |
580 | } | |
581 | ||
8b60d6c2 | 582 | /* Register for SPI Interrupt */ |
4178b6b1 | 583 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq, |
8b60d6c2 MH |
584 | 0, "fsl_espi", mpc8xxx_spi); |
585 | if (ret) | |
4178b6b1 | 586 | goto err_probe; |
8b60d6c2 MH |
587 | |
588 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { | |
589 | mpc8xxx_spi->rx_shift = 16; | |
590 | mpc8xxx_spi->tx_shift = 24; | |
591 | } | |
592 | ||
593 | /* SPI controller initializations */ | |
46afd38b HK |
594 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
595 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
596 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
597 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
8b60d6c2 MH |
598 | |
599 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
600 | for_each_available_child_of_node(master->dev.of_node, nc) { |
601 | /* get chip select */ | |
602 | prop = of_get_property(nc, "reg", &len); | |
603 | if (!prop || len < sizeof(*prop)) | |
604 | continue; | |
605 | i = be32_to_cpup(prop); | |
606 | if (i < 0 || i >= pdata->max_chipselect) | |
607 | continue; | |
608 | ||
609 | csmode = CSMODE_INIT_VAL; | |
610 | /* check if CSBEF is set in device tree */ | |
611 | prop = of_get_property(nc, "fsl,csbef", &len); | |
612 | if (prop && len >= sizeof(*prop)) { | |
613 | csmode &= ~(CSMODE_BEF(0xf)); | |
614 | csmode |= CSMODE_BEF(be32_to_cpup(prop)); | |
615 | } | |
616 | /* check if CSAFT is set in device tree */ | |
617 | prop = of_get_property(nc, "fsl,csaft", &len); | |
618 | if (prop && len >= sizeof(*prop)) { | |
619 | csmode &= ~(CSMODE_AFT(0xf)); | |
620 | csmode |= CSMODE_AFT(be32_to_cpup(prop)); | |
621 | } | |
46afd38b | 622 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), csmode); |
d0fb47a5 JW |
623 | |
624 | dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode); | |
625 | } | |
8b60d6c2 MH |
626 | |
627 | /* Enable SPI interface */ | |
628 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
629 | ||
46afd38b | 630 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
8b60d6c2 | 631 | |
e9abb4db HK |
632 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
633 | pm_runtime_use_autosuspend(dev); | |
634 | pm_runtime_set_active(dev); | |
635 | pm_runtime_enable(dev); | |
636 | pm_runtime_get_sync(dev); | |
637 | ||
4178b6b1 | 638 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 639 | if (ret < 0) |
e9abb4db | 640 | goto err_pm; |
8b60d6c2 | 641 | |
46afd38b HK |
642 | dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base, |
643 | mpc8xxx_spi->irq); | |
8b60d6c2 | 644 | |
e9abb4db HK |
645 | pm_runtime_mark_last_busy(dev); |
646 | pm_runtime_put_autosuspend(dev); | |
647 | ||
604042af | 648 | return 0; |
8b60d6c2 | 649 | |
e9abb4db HK |
650 | err_pm: |
651 | pm_runtime_put_noidle(dev); | |
652 | pm_runtime_disable(dev); | |
653 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
654 | err_probe: |
655 | spi_master_put(master); | |
604042af | 656 | return ret; |
8b60d6c2 MH |
657 | } |
658 | ||
659 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
660 | { | |
661 | struct device_node *np = dev->of_node; | |
8074cf06 | 662 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
663 | const u32 *prop; |
664 | int len; | |
665 | ||
666 | prop = of_get_property(np, "fsl,espi-num-chipselects", &len); | |
667 | if (!prop || len < sizeof(*prop)) { | |
668 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); | |
669 | return -EINVAL; | |
670 | } | |
671 | ||
672 | pdata->max_chipselect = *prop; | |
673 | pdata->cs_control = NULL; | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
fd4a319b | 678 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
679 | { |
680 | struct device *dev = &ofdev->dev; | |
681 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 682 | struct resource mem; |
f7578496 | 683 | unsigned int irq; |
acf69219 | 684 | int ret; |
8b60d6c2 | 685 | |
18d306d1 | 686 | ret = of_mpc8xxx_spi_probe(ofdev); |
8b60d6c2 MH |
687 | if (ret) |
688 | return ret; | |
689 | ||
690 | ret = of_fsl_espi_get_chipselects(dev); | |
691 | if (ret) | |
acf69219 | 692 | return ret; |
8b60d6c2 MH |
693 | |
694 | ret = of_address_to_resource(np, 0, &mem); | |
695 | if (ret) | |
acf69219 | 696 | return ret; |
8b60d6c2 | 697 | |
f7578496 | 698 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
699 | if (!irq) |
700 | return -EINVAL; | |
8b60d6c2 | 701 | |
604042af | 702 | return fsl_espi_probe(dev, &mem, irq); |
8b60d6c2 MH |
703 | } |
704 | ||
e9abb4db HK |
705 | static int of_fsl_espi_remove(struct platform_device *dev) |
706 | { | |
707 | pm_runtime_disable(&dev->dev); | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
714bb654 HZ |
712 | #ifdef CONFIG_PM_SLEEP |
713 | static int of_fsl_espi_suspend(struct device *dev) | |
714 | { | |
715 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
716 | int ret; |
717 | ||
714bb654 HZ |
718 | ret = spi_master_suspend(master); |
719 | if (ret) { | |
720 | dev_warn(dev, "cannot suspend master\n"); | |
721 | return ret; | |
722 | } | |
723 | ||
e9abb4db HK |
724 | ret = pm_runtime_force_suspend(dev); |
725 | if (ret < 0) | |
726 | return ret; | |
727 | ||
728 | return 0; | |
714bb654 HZ |
729 | } |
730 | ||
731 | static int of_fsl_espi_resume(struct device *dev) | |
732 | { | |
733 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
734 | struct spi_master *master = dev_get_drvdata(dev); | |
735 | struct mpc8xxx_spi *mpc8xxx_spi; | |
714bb654 | 736 | u32 regval; |
e9abb4db | 737 | int i, ret; |
714bb654 HZ |
738 | |
739 | mpc8xxx_spi = spi_master_get_devdata(master); | |
714bb654 HZ |
740 | |
741 | /* SPI controller initializations */ | |
46afd38b HK |
742 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
743 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
744 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
745 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
714bb654 HZ |
746 | |
747 | /* Init eSPI CS mode register */ | |
748 | for (i = 0; i < pdata->max_chipselect; i++) | |
46afd38b HK |
749 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), |
750 | CSMODE_INIT_VAL); | |
714bb654 HZ |
751 | |
752 | /* Enable SPI interface */ | |
753 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
754 | ||
46afd38b | 755 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
714bb654 | 756 | |
e9abb4db HK |
757 | ret = pm_runtime_force_resume(dev); |
758 | if (ret < 0) | |
759 | return ret; | |
760 | ||
714bb654 HZ |
761 | return spi_master_resume(master); |
762 | } | |
763 | #endif /* CONFIG_PM_SLEEP */ | |
764 | ||
765 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
766 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
767 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
768 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
769 | }; | |
770 | ||
8b60d6c2 MH |
771 | static const struct of_device_id of_fsl_espi_match[] = { |
772 | { .compatible = "fsl,mpc8536-espi" }, | |
773 | {} | |
774 | }; | |
775 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
776 | ||
18d306d1 | 777 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
778 | .driver = { |
779 | .name = "fsl_espi", | |
8b60d6c2 | 780 | .of_match_table = of_fsl_espi_match, |
714bb654 | 781 | .pm = &espi_pm, |
8b60d6c2 MH |
782 | }, |
783 | .probe = of_fsl_espi_probe, | |
e9abb4db | 784 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 785 | }; |
940ab889 | 786 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
787 | |
788 | MODULE_AUTHOR("Mingkai Hu"); | |
789 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
790 | MODULE_LICENSE("GPL"); |