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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
011f23a3 MW |
2 | /* |
3 | * Driver for Cirrus Logic EP93xx SPI controller. | |
4 | * | |
626a96db | 5 | * Copyright (C) 2010-2011 Mika Westerberg |
011f23a3 MW |
6 | * |
7 | * Explicit FIFO handling code was inspired by amba-pl022 driver. | |
8 | * | |
9 | * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. | |
10 | * | |
11 | * For more information about the SPI controller see documentation on Cirrus | |
12 | * Logic web site: | |
13 | * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf | |
011f23a3 MW |
14 | */ |
15 | ||
16 | #include <linux/io.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/device.h> | |
626a96db | 21 | #include <linux/dmaengine.h> |
011f23a3 MW |
22 | #include <linux/bitops.h> |
23 | #include <linux/interrupt.h> | |
5bdb7613 | 24 | #include <linux/module.h> |
011f23a3 | 25 | #include <linux/platform_device.h> |
011f23a3 | 26 | #include <linux/sched.h> |
626a96db | 27 | #include <linux/scatterlist.h> |
011f23a3 MW |
28 | #include <linux/spi/spi.h> |
29 | ||
a3b29245 AB |
30 | #include <linux/platform_data/dma-ep93xx.h> |
31 | #include <linux/platform_data/spi-ep93xx.h> | |
011f23a3 MW |
32 | |
33 | #define SSPCR0 0x0000 | |
34 | #define SSPCR0_MODE_SHIFT 6 | |
35 | #define SSPCR0_SCR_SHIFT 8 | |
36 | ||
37 | #define SSPCR1 0x0004 | |
38 | #define SSPCR1_RIE BIT(0) | |
39 | #define SSPCR1_TIE BIT(1) | |
40 | #define SSPCR1_RORIE BIT(2) | |
41 | #define SSPCR1_LBM BIT(3) | |
42 | #define SSPCR1_SSE BIT(4) | |
43 | #define SSPCR1_MS BIT(5) | |
44 | #define SSPCR1_SOD BIT(6) | |
45 | ||
46 | #define SSPDR 0x0008 | |
47 | ||
48 | #define SSPSR 0x000c | |
49 | #define SSPSR_TFE BIT(0) | |
50 | #define SSPSR_TNF BIT(1) | |
51 | #define SSPSR_RNE BIT(2) | |
52 | #define SSPSR_RFF BIT(3) | |
53 | #define SSPSR_BSY BIT(4) | |
54 | #define SSPCPSR 0x0010 | |
55 | ||
56 | #define SSPIIR 0x0014 | |
57 | #define SSPIIR_RIS BIT(0) | |
58 | #define SSPIIR_TIS BIT(1) | |
59 | #define SSPIIR_RORIS BIT(2) | |
60 | #define SSPICR SSPIIR | |
61 | ||
62 | /* timeout in milliseconds */ | |
63 | #define SPI_TIMEOUT 5 | |
64 | /* maximum depth of RX/TX FIFO */ | |
65 | #define SPI_FIFO_SIZE 8 | |
66 | ||
67 | /** | |
68 | * struct ep93xx_spi - EP93xx SPI controller structure | |
011f23a3 | 69 | * @clk: clock for the controller |
1232978a | 70 | * @mmio: pointer to ioremap()'d registers |
626a96db | 71 | * @sspdr_phys: physical address of the SSPDR register |
011f23a3 MW |
72 | * @tx: current byte in transfer to transmit |
73 | * @rx: current byte in transfer to receive | |
74 | * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one | |
75 | * frame decreases this level and sending one frame increases it. | |
626a96db MW |
76 | * @dma_rx: RX DMA channel |
77 | * @dma_tx: TX DMA channel | |
78 | * @dma_rx_data: RX parameters passed to the DMA engine | |
79 | * @dma_tx_data: TX parameters passed to the DMA engine | |
80 | * @rx_sgt: sg table for RX transfers | |
81 | * @tx_sgt: sg table for TX transfers | |
82 | * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by | |
83 | * the client | |
011f23a3 MW |
84 | */ |
85 | struct ep93xx_spi { | |
011f23a3 | 86 | struct clk *clk; |
1232978a | 87 | void __iomem *mmio; |
626a96db | 88 | unsigned long sspdr_phys; |
011f23a3 MW |
89 | size_t tx; |
90 | size_t rx; | |
91 | size_t fifo_level; | |
626a96db MW |
92 | struct dma_chan *dma_rx; |
93 | struct dma_chan *dma_tx; | |
94 | struct ep93xx_dma_data dma_rx_data; | |
95 | struct ep93xx_dma_data dma_tx_data; | |
96 | struct sg_table rx_sgt; | |
97 | struct sg_table tx_sgt; | |
98 | void *zeropage; | |
011f23a3 MW |
99 | }; |
100 | ||
011f23a3 MW |
101 | /* converts bits per word to CR0.DSS value */ |
102 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) | |
103 | ||
011f23a3 MW |
104 | /** |
105 | * ep93xx_spi_calc_divisors() - calculates SPI clock divisors | |
48738831 | 106 | * @master: SPI master |
011f23a3 | 107 | * @rate: desired SPI output clock rate |
f7ef1da9 HS |
108 | * @div_cpsr: pointer to return the cpsr (pre-scaler) divider |
109 | * @div_scr: pointer to return the scr divider | |
011f23a3 | 110 | */ |
48738831 | 111 | static int ep93xx_spi_calc_divisors(struct spi_master *master, |
56fc0b42 | 112 | u32 rate, u8 *div_cpsr, u8 *div_scr) |
011f23a3 | 113 | { |
48738831 | 114 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
011f23a3 MW |
115 | unsigned long spi_clk_rate = clk_get_rate(espi->clk); |
116 | int cpsr, scr; | |
117 | ||
118 | /* | |
119 | * Make sure that max value is between values supported by the | |
d9a01771 | 120 | * controller. |
011f23a3 | 121 | */ |
56fc0b42 | 122 | rate = clamp(rate, master->min_speed_hz, master->max_speed_hz); |
011f23a3 MW |
123 | |
124 | /* | |
125 | * Calculate divisors so that we can get speed according the | |
126 | * following formula: | |
127 | * rate = spi_clock_rate / (cpsr * (1 + scr)) | |
128 | * | |
129 | * cpsr must be even number and starts from 2, scr can be any number | |
130 | * between 0 and 255. | |
131 | */ | |
132 | for (cpsr = 2; cpsr <= 254; cpsr += 2) { | |
133 | for (scr = 0; scr <= 255; scr++) { | |
134 | if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { | |
f7ef1da9 HS |
135 | *div_scr = (u8)scr; |
136 | *div_cpsr = (u8)cpsr; | |
011f23a3 MW |
137 | return 0; |
138 | } | |
139 | } | |
140 | } | |
141 | ||
142 | return -EINVAL; | |
143 | } | |
144 | ||
48738831 | 145 | static int ep93xx_spi_chip_setup(struct spi_master *master, |
55f0cd3f HS |
146 | struct spi_device *spi, |
147 | struct spi_transfer *xfer) | |
011f23a3 | 148 | { |
48738831 | 149 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
55f0cd3f | 150 | u8 dss = bits_per_word_to_dss(xfer->bits_per_word); |
f7ef1da9 HS |
151 | u8 div_cpsr = 0; |
152 | u8 div_scr = 0; | |
011f23a3 | 153 | u16 cr0; |
f7ef1da9 HS |
154 | int err; |
155 | ||
48738831 | 156 | err = ep93xx_spi_calc_divisors(master, xfer->speed_hz, |
55f0cd3f | 157 | &div_cpsr, &div_scr); |
f7ef1da9 HS |
158 | if (err) |
159 | return err; | |
011f23a3 | 160 | |
f7ef1da9 | 161 | cr0 = div_scr << SSPCR0_SCR_SHIFT; |
55f0cd3f | 162 | cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT; |
d9b65dfd | 163 | cr0 |= dss; |
011f23a3 | 164 | |
48738831 | 165 | dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", |
55f0cd3f | 166 | spi->mode, div_cpsr, div_scr, dss); |
48738831 | 167 | dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0); |
011f23a3 | 168 | |
8447e478 HS |
169 | writel(div_cpsr, espi->mmio + SSPCPSR); |
170 | writel(cr0, espi->mmio + SSPCR0); | |
f7ef1da9 HS |
171 | |
172 | return 0; | |
011f23a3 MW |
173 | } |
174 | ||
d9a01771 | 175 | static void ep93xx_do_write(struct spi_master *master) |
011f23a3 | 176 | { |
d9a01771 HS |
177 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
178 | struct spi_transfer *xfer = master->cur_msg->state; | |
8447e478 | 179 | u32 val = 0; |
011f23a3 | 180 | |
d9a01771 HS |
181 | if (xfer->bits_per_word > 8) { |
182 | if (xfer->tx_buf) | |
183 | val = ((u16 *)xfer->tx_buf)[espi->tx]; | |
8447e478 | 184 | espi->tx += 2; |
011f23a3 | 185 | } else { |
d9a01771 HS |
186 | if (xfer->tx_buf) |
187 | val = ((u8 *)xfer->tx_buf)[espi->tx]; | |
8447e478 | 188 | espi->tx += 1; |
011f23a3 | 189 | } |
8447e478 | 190 | writel(val, espi->mmio + SSPDR); |
011f23a3 MW |
191 | } |
192 | ||
d9a01771 | 193 | static void ep93xx_do_read(struct spi_master *master) |
011f23a3 | 194 | { |
d9a01771 HS |
195 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
196 | struct spi_transfer *xfer = master->cur_msg->state; | |
8447e478 | 197 | u32 val; |
011f23a3 | 198 | |
8447e478 | 199 | val = readl(espi->mmio + SSPDR); |
d9a01771 HS |
200 | if (xfer->bits_per_word > 8) { |
201 | if (xfer->rx_buf) | |
202 | ((u16 *)xfer->rx_buf)[espi->rx] = val; | |
8447e478 | 203 | espi->rx += 2; |
011f23a3 | 204 | } else { |
d9a01771 HS |
205 | if (xfer->rx_buf) |
206 | ((u8 *)xfer->rx_buf)[espi->rx] = val; | |
8447e478 | 207 | espi->rx += 1; |
011f23a3 MW |
208 | } |
209 | } | |
210 | ||
211 | /** | |
212 | * ep93xx_spi_read_write() - perform next RX/TX transfer | |
213 | * @espi: ep93xx SPI controller struct | |
214 | * | |
215 | * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If | |
216 | * called several times, the whole transfer will be completed. Returns | |
217 | * %-EINPROGRESS when current transfer was not yet completed otherwise %0. | |
218 | * | |
219 | * When this function is finished, RX FIFO should be empty and TX FIFO should be | |
220 | * full. | |
221 | */ | |
48738831 | 222 | static int ep93xx_spi_read_write(struct spi_master *master) |
011f23a3 | 223 | { |
48738831 | 224 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
d9a01771 | 225 | struct spi_transfer *xfer = master->cur_msg->state; |
011f23a3 MW |
226 | |
227 | /* read as long as RX FIFO has frames in it */ | |
8447e478 | 228 | while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) { |
d9a01771 | 229 | ep93xx_do_read(master); |
011f23a3 MW |
230 | espi->fifo_level--; |
231 | } | |
232 | ||
233 | /* write as long as TX FIFO has room */ | |
d9a01771 HS |
234 | while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) { |
235 | ep93xx_do_write(master); | |
011f23a3 MW |
236 | espi->fifo_level++; |
237 | } | |
238 | ||
d9a01771 | 239 | if (espi->rx == xfer->len) |
011f23a3 | 240 | return 0; |
011f23a3 MW |
241 | |
242 | return -EINPROGRESS; | |
243 | } | |
244 | ||
a1108c7b NC |
245 | static enum dma_transfer_direction |
246 | ep93xx_dma_data_to_trans_dir(enum dma_data_direction dir) | |
247 | { | |
248 | switch (dir) { | |
249 | case DMA_TO_DEVICE: | |
250 | return DMA_MEM_TO_DEV; | |
251 | case DMA_FROM_DEVICE: | |
252 | return DMA_DEV_TO_MEM; | |
253 | default: | |
254 | return DMA_TRANS_NONE; | |
255 | } | |
256 | } | |
257 | ||
626a96db MW |
258 | /** |
259 | * ep93xx_spi_dma_prepare() - prepares a DMA transfer | |
48738831 | 260 | * @master: SPI master |
626a96db MW |
261 | * @dir: DMA transfer direction |
262 | * | |
263 | * Function configures the DMA, maps the buffer and prepares the DMA | |
264 | * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR | |
265 | * in case of failure. | |
266 | */ | |
267 | static struct dma_async_tx_descriptor * | |
48738831 | 268 | ep93xx_spi_dma_prepare(struct spi_master *master, |
a1108c7b | 269 | enum dma_data_direction dir) |
626a96db | 270 | { |
48738831 | 271 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
d9a01771 | 272 | struct spi_transfer *xfer = master->cur_msg->state; |
626a96db MW |
273 | struct dma_async_tx_descriptor *txd; |
274 | enum dma_slave_buswidth buswidth; | |
275 | struct dma_slave_config conf; | |
276 | struct scatterlist *sg; | |
277 | struct sg_table *sgt; | |
278 | struct dma_chan *chan; | |
279 | const void *buf, *pbuf; | |
d9a01771 | 280 | size_t len = xfer->len; |
626a96db MW |
281 | int i, ret, nents; |
282 | ||
d9a01771 | 283 | if (xfer->bits_per_word > 8) |
626a96db MW |
284 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; |
285 | else | |
286 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
287 | ||
288 | memset(&conf, 0, sizeof(conf)); | |
a1108c7b | 289 | conf.direction = ep93xx_dma_data_to_trans_dir(dir); |
626a96db | 290 | |
a1108c7b | 291 | if (dir == DMA_FROM_DEVICE) { |
626a96db | 292 | chan = espi->dma_rx; |
d9a01771 | 293 | buf = xfer->rx_buf; |
626a96db MW |
294 | sgt = &espi->rx_sgt; |
295 | ||
296 | conf.src_addr = espi->sspdr_phys; | |
297 | conf.src_addr_width = buswidth; | |
298 | } else { | |
299 | chan = espi->dma_tx; | |
d9a01771 | 300 | buf = xfer->tx_buf; |
626a96db MW |
301 | sgt = &espi->tx_sgt; |
302 | ||
303 | conf.dst_addr = espi->sspdr_phys; | |
304 | conf.dst_addr_width = buswidth; | |
305 | } | |
306 | ||
307 | ret = dmaengine_slave_config(chan, &conf); | |
308 | if (ret) | |
309 | return ERR_PTR(ret); | |
310 | ||
311 | /* | |
312 | * We need to split the transfer into PAGE_SIZE'd chunks. This is | |
313 | * because we are using @espi->zeropage to provide a zero RX buffer | |
314 | * for the TX transfers and we have only allocated one page for that. | |
315 | * | |
316 | * For performance reasons we allocate a new sg_table only when | |
317 | * needed. Otherwise we will re-use the current one. Eventually the | |
318 | * last sg_table is released in ep93xx_spi_release_dma(). | |
319 | */ | |
320 | ||
321 | nents = DIV_ROUND_UP(len, PAGE_SIZE); | |
322 | if (nents != sgt->nents) { | |
323 | sg_free_table(sgt); | |
324 | ||
325 | ret = sg_alloc_table(sgt, nents, GFP_KERNEL); | |
326 | if (ret) | |
327 | return ERR_PTR(ret); | |
328 | } | |
329 | ||
330 | pbuf = buf; | |
331 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | |
332 | size_t bytes = min_t(size_t, len, PAGE_SIZE); | |
333 | ||
334 | if (buf) { | |
335 | sg_set_page(sg, virt_to_page(pbuf), bytes, | |
336 | offset_in_page(pbuf)); | |
337 | } else { | |
338 | sg_set_page(sg, virt_to_page(espi->zeropage), | |
339 | bytes, 0); | |
340 | } | |
341 | ||
342 | pbuf += bytes; | |
343 | len -= bytes; | |
344 | } | |
345 | ||
346 | if (WARN_ON(len)) { | |
48738831 | 347 | dev_warn(&master->dev, "len = %zu expected 0!\n", len); |
626a96db MW |
348 | return ERR_PTR(-EINVAL); |
349 | } | |
350 | ||
351 | nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
352 | if (!nents) | |
353 | return ERR_PTR(-ENOMEM); | |
354 | ||
a1108c7b NC |
355 | txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction, |
356 | DMA_CTRL_ACK); | |
626a96db MW |
357 | if (!txd) { |
358 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
359 | return ERR_PTR(-ENOMEM); | |
360 | } | |
361 | return txd; | |
362 | } | |
363 | ||
364 | /** | |
365 | * ep93xx_spi_dma_finish() - finishes with a DMA transfer | |
48738831 | 366 | * @master: SPI master |
626a96db MW |
367 | * @dir: DMA transfer direction |
368 | * | |
369 | * Function finishes with the DMA transfer. After this, the DMA buffer is | |
370 | * unmapped. | |
371 | */ | |
48738831 | 372 | static void ep93xx_spi_dma_finish(struct spi_master *master, |
a1108c7b | 373 | enum dma_data_direction dir) |
626a96db | 374 | { |
48738831 | 375 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
626a96db MW |
376 | struct dma_chan *chan; |
377 | struct sg_table *sgt; | |
378 | ||
a1108c7b | 379 | if (dir == DMA_FROM_DEVICE) { |
626a96db MW |
380 | chan = espi->dma_rx; |
381 | sgt = &espi->rx_sgt; | |
382 | } else { | |
383 | chan = espi->dma_tx; | |
384 | sgt = &espi->tx_sgt; | |
385 | } | |
386 | ||
387 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
388 | } | |
389 | ||
390 | static void ep93xx_spi_dma_callback(void *callback_param) | |
391 | { | |
d9a01771 HS |
392 | struct spi_master *master = callback_param; |
393 | ||
a1108c7b NC |
394 | ep93xx_spi_dma_finish(master, DMA_TO_DEVICE); |
395 | ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE); | |
d9a01771 HS |
396 | |
397 | spi_finalize_current_transfer(master); | |
626a96db MW |
398 | } |
399 | ||
d9a01771 | 400 | static int ep93xx_spi_dma_transfer(struct spi_master *master) |
626a96db | 401 | { |
48738831 | 402 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
626a96db MW |
403 | struct dma_async_tx_descriptor *rxd, *txd; |
404 | ||
a1108c7b | 405 | rxd = ep93xx_spi_dma_prepare(master, DMA_FROM_DEVICE); |
626a96db | 406 | if (IS_ERR(rxd)) { |
48738831 | 407 | dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); |
d9a01771 | 408 | return PTR_ERR(rxd); |
626a96db MW |
409 | } |
410 | ||
a1108c7b | 411 | txd = ep93xx_spi_dma_prepare(master, DMA_TO_DEVICE); |
626a96db | 412 | if (IS_ERR(txd)) { |
a1108c7b | 413 | ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE); |
48738831 | 414 | dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd)); |
d9a01771 | 415 | return PTR_ERR(txd); |
626a96db MW |
416 | } |
417 | ||
418 | /* We are ready when RX is done */ | |
419 | rxd->callback = ep93xx_spi_dma_callback; | |
d9a01771 | 420 | rxd->callback_param = master; |
626a96db | 421 | |
d9a01771 | 422 | /* Now submit both descriptors and start DMA */ |
626a96db MW |
423 | dmaengine_submit(rxd); |
424 | dmaengine_submit(txd); | |
425 | ||
426 | dma_async_issue_pending(espi->dma_rx); | |
427 | dma_async_issue_pending(espi->dma_tx); | |
428 | ||
d9a01771 HS |
429 | /* signal that we need to wait for completion */ |
430 | return 1; | |
011f23a3 MW |
431 | } |
432 | ||
433 | static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) | |
434 | { | |
48738831 HS |
435 | struct spi_master *master = dev_id; |
436 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
ac8d06df | 437 | u32 val; |
011f23a3 MW |
438 | |
439 | /* | |
440 | * If we got ROR (receive overrun) interrupt we know that something is | |
441 | * wrong. Just abort the message. | |
442 | */ | |
8447e478 | 443 | if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) { |
011f23a3 | 444 | /* clear the overrun interrupt */ |
8447e478 | 445 | writel(0, espi->mmio + SSPICR); |
48738831 | 446 | dev_warn(&master->dev, |
011f23a3 | 447 | "receive overrun, aborting the message\n"); |
c7a909cf | 448 | master->cur_msg->status = -EIO; |
011f23a3 MW |
449 | } else { |
450 | /* | |
451 | * Interrupt is either RX (RIS) or TX (TIS). For both cases we | |
452 | * simply execute next data transfer. | |
453 | */ | |
48738831 | 454 | if (ep93xx_spi_read_write(master)) { |
011f23a3 MW |
455 | /* |
456 | * In normal case, there still is some processing left | |
457 | * for current transfer. Let's wait for the next | |
458 | * interrupt then. | |
459 | */ | |
460 | return IRQ_HANDLED; | |
461 | } | |
462 | } | |
463 | ||
464 | /* | |
465 | * Current transfer is finished, either with error or with success. In | |
466 | * any case we disable interrupts and notify the worker to handle | |
467 | * any post-processing of the message. | |
468 | */ | |
ac8d06df HS |
469 | val = readl(espi->mmio + SSPCR1); |
470 | val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
471 | writel(val, espi->mmio + SSPCR1); | |
472 | ||
d9a01771 | 473 | spi_finalize_current_transfer(master); |
ac8d06df | 474 | |
011f23a3 MW |
475 | return IRQ_HANDLED; |
476 | } | |
477 | ||
d9a01771 HS |
478 | static int ep93xx_spi_transfer_one(struct spi_master *master, |
479 | struct spi_device *spi, | |
480 | struct spi_transfer *xfer) | |
481 | { | |
482 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
483 | u32 val; | |
484 | int ret; | |
485 | ||
486 | ret = ep93xx_spi_chip_setup(master, spi, xfer); | |
487 | if (ret) { | |
488 | dev_err(&master->dev, "failed to setup chip for transfer\n"); | |
489 | return ret; | |
490 | } | |
491 | ||
492 | master->cur_msg->state = xfer; | |
493 | espi->rx = 0; | |
494 | espi->tx = 0; | |
495 | ||
496 | /* | |
497 | * There is no point of setting up DMA for the transfers which will | |
498 | * fit into the FIFO and can be transferred with a single interrupt. | |
499 | * So in these cases we will be using PIO and don't bother for DMA. | |
500 | */ | |
501 | if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE) | |
502 | return ep93xx_spi_dma_transfer(master); | |
503 | ||
504 | /* Using PIO so prime the TX FIFO and enable interrupts */ | |
505 | ep93xx_spi_read_write(master); | |
506 | ||
507 | val = readl(espi->mmio + SSPCR1); | |
508 | val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
509 | writel(val, espi->mmio + SSPCR1); | |
510 | ||
511 | /* signal that we need to wait for completion */ | |
512 | return 1; | |
513 | } | |
514 | ||
515 | static int ep93xx_spi_prepare_message(struct spi_master *master, | |
516 | struct spi_message *msg) | |
517 | { | |
518 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
519 | unsigned long timeout; | |
520 | ||
521 | /* | |
522 | * Just to be sure: flush any data from RX FIFO. | |
523 | */ | |
524 | timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); | |
525 | while (readl(espi->mmio + SSPSR) & SSPSR_RNE) { | |
526 | if (time_after(jiffies, timeout)) { | |
527 | dev_warn(&master->dev, | |
528 | "timeout while flushing RX FIFO\n"); | |
529 | return -ETIMEDOUT; | |
530 | } | |
531 | readl(espi->mmio + SSPDR); | |
532 | } | |
533 | ||
534 | /* | |
535 | * We explicitly handle FIFO level. This way we don't have to check TX | |
536 | * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. | |
537 | */ | |
538 | espi->fifo_level = 0; | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
16779622 HS |
543 | static int ep93xx_spi_prepare_hardware(struct spi_master *master) |
544 | { | |
545 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
546 | u32 val; | |
547 | int ret; | |
548 | ||
549 | ret = clk_enable(espi->clk); | |
550 | if (ret) | |
551 | return ret; | |
552 | ||
553 | val = readl(espi->mmio + SSPCR1); | |
554 | val |= SSPCR1_SSE; | |
555 | writel(val, espi->mmio + SSPCR1); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static int ep93xx_spi_unprepare_hardware(struct spi_master *master) | |
561 | { | |
562 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
563 | u32 val; | |
564 | ||
565 | val = readl(espi->mmio + SSPCR1); | |
566 | val &= ~SSPCR1_SSE; | |
567 | writel(val, espi->mmio + SSPCR1); | |
568 | ||
569 | clk_disable(espi->clk); | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
626a96db MW |
574 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) |
575 | { | |
576 | if (ep93xx_dma_chan_is_m2p(chan)) | |
577 | return false; | |
578 | ||
579 | chan->private = filter_param; | |
580 | return true; | |
581 | } | |
582 | ||
583 | static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |
584 | { | |
585 | dma_cap_mask_t mask; | |
586 | int ret; | |
587 | ||
588 | espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); | |
589 | if (!espi->zeropage) | |
590 | return -ENOMEM; | |
591 | ||
592 | dma_cap_zero(mask); | |
593 | dma_cap_set(DMA_SLAVE, mask); | |
594 | ||
595 | espi->dma_rx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 596 | espi->dma_rx_data.direction = DMA_DEV_TO_MEM; |
626a96db MW |
597 | espi->dma_rx_data.name = "ep93xx-spi-rx"; |
598 | ||
599 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
600 | &espi->dma_rx_data); | |
601 | if (!espi->dma_rx) { | |
602 | ret = -ENODEV; | |
603 | goto fail_free_page; | |
604 | } | |
605 | ||
606 | espi->dma_tx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 607 | espi->dma_tx_data.direction = DMA_MEM_TO_DEV; |
626a96db MW |
608 | espi->dma_tx_data.name = "ep93xx-spi-tx"; |
609 | ||
610 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
611 | &espi->dma_tx_data); | |
612 | if (!espi->dma_tx) { | |
613 | ret = -ENODEV; | |
614 | goto fail_release_rx; | |
615 | } | |
616 | ||
617 | return 0; | |
618 | ||
619 | fail_release_rx: | |
620 | dma_release_channel(espi->dma_rx); | |
621 | espi->dma_rx = NULL; | |
622 | fail_free_page: | |
623 | free_page((unsigned long)espi->zeropage); | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
628 | static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) | |
629 | { | |
630 | if (espi->dma_rx) { | |
631 | dma_release_channel(espi->dma_rx); | |
632 | sg_free_table(&espi->rx_sgt); | |
633 | } | |
634 | if (espi->dma_tx) { | |
635 | dma_release_channel(espi->dma_tx); | |
636 | sg_free_table(&espi->tx_sgt); | |
637 | } | |
638 | ||
639 | if (espi->zeropage) | |
640 | free_page((unsigned long)espi->zeropage); | |
641 | } | |
642 | ||
fd4a319b | 643 | static int ep93xx_spi_probe(struct platform_device *pdev) |
011f23a3 MW |
644 | { |
645 | struct spi_master *master; | |
646 | struct ep93xx_spi_info *info; | |
647 | struct ep93xx_spi *espi; | |
648 | struct resource *res; | |
6d6467ee | 649 | int irq; |
011f23a3 MW |
650 | int error; |
651 | ||
8074cf06 | 652 | info = dev_get_platdata(&pdev->dev); |
55f0cd3f HS |
653 | if (!info) { |
654 | dev_err(&pdev->dev, "missing platform data\n"); | |
655 | return -EINVAL; | |
656 | } | |
011f23a3 | 657 | |
48a7776e | 658 | irq = platform_get_irq(pdev, 0); |
6b8ac10e | 659 | if (irq < 0) |
48a7776e | 660 | return -EBUSY; |
48a7776e HS |
661 | |
662 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
663 | if (!res) { | |
664 | dev_err(&pdev->dev, "unable to get iomem resource\n"); | |
665 | return -ENODEV; | |
666 | } | |
667 | ||
011f23a3 | 668 | master = spi_alloc_master(&pdev->dev, sizeof(*espi)); |
b2d185ed | 669 | if (!master) |
011f23a3 | 670 | return -ENOMEM; |
011f23a3 | 671 | |
1dfbf334 | 672 | master->use_gpio_descriptors = true; |
16779622 HS |
673 | master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware; |
674 | master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware; | |
d9a01771 HS |
675 | master->prepare_message = ep93xx_spi_prepare_message; |
676 | master->transfer_one = ep93xx_spi_transfer_one; | |
011f23a3 | 677 | master->bus_num = pdev->id; |
011f23a3 | 678 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
24778be2 | 679 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
1dfbf334 LW |
680 | /* |
681 | * The SPI core will count the number of GPIO descriptors to figure | |
682 | * out the number of chip selects available on the platform. | |
683 | */ | |
684 | master->num_chipselect = 0; | |
55f0cd3f | 685 | |
011f23a3 MW |
686 | platform_set_drvdata(pdev, master); |
687 | ||
688 | espi = spi_master_get_devdata(master); | |
689 | ||
e6eb8d9b | 690 | espi->clk = devm_clk_get(&pdev->dev, NULL); |
011f23a3 MW |
691 | if (IS_ERR(espi->clk)) { |
692 | dev_err(&pdev->dev, "unable to get spi clock\n"); | |
693 | error = PTR_ERR(espi->clk); | |
694 | goto fail_release_master; | |
695 | } | |
696 | ||
011f23a3 MW |
697 | /* |
698 | * Calculate maximum and minimum supported clock rates | |
699 | * for the controller. | |
700 | */ | |
56fc0b42 AL |
701 | master->max_speed_hz = clk_get_rate(espi->clk) / 2; |
702 | master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256); | |
011f23a3 | 703 | |
626a96db | 704 | espi->sspdr_phys = res->start + SSPDR; |
6d6467ee | 705 | |
1232978a HS |
706 | espi->mmio = devm_ioremap_resource(&pdev->dev, res); |
707 | if (IS_ERR(espi->mmio)) { | |
708 | error = PTR_ERR(espi->mmio); | |
e6eb8d9b | 709 | goto fail_release_master; |
011f23a3 MW |
710 | } |
711 | ||
6d6467ee | 712 | error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, |
48738831 | 713 | 0, "ep93xx-spi", master); |
011f23a3 MW |
714 | if (error) { |
715 | dev_err(&pdev->dev, "failed to request irq\n"); | |
e6eb8d9b | 716 | goto fail_release_master; |
011f23a3 MW |
717 | } |
718 | ||
626a96db MW |
719 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) |
720 | dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); | |
721 | ||
011f23a3 | 722 | /* make sure that the hardware is disabled */ |
8447e478 | 723 | writel(0, espi->mmio + SSPCR1); |
011f23a3 | 724 | |
434eaf3b | 725 | error = devm_spi_register_master(&pdev->dev, master); |
011f23a3 MW |
726 | if (error) { |
727 | dev_err(&pdev->dev, "failed to register SPI master\n"); | |
84ddb3c1 | 728 | goto fail_free_dma; |
011f23a3 MW |
729 | } |
730 | ||
731 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", | |
6d6467ee | 732 | (unsigned long)res->start, irq); |
011f23a3 MW |
733 | |
734 | return 0; | |
735 | ||
626a96db MW |
736 | fail_free_dma: |
737 | ep93xx_spi_release_dma(espi); | |
011f23a3 MW |
738 | fail_release_master: |
739 | spi_master_put(master); | |
011f23a3 MW |
740 | |
741 | return error; | |
742 | } | |
743 | ||
fd4a319b | 744 | static int ep93xx_spi_remove(struct platform_device *pdev) |
011f23a3 MW |
745 | { |
746 | struct spi_master *master = platform_get_drvdata(pdev); | |
747 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
011f23a3 | 748 | |
626a96db | 749 | ep93xx_spi_release_dma(espi); |
011f23a3 | 750 | |
011f23a3 MW |
751 | return 0; |
752 | } | |
753 | ||
754 | static struct platform_driver ep93xx_spi_driver = { | |
755 | .driver = { | |
756 | .name = "ep93xx-spi", | |
011f23a3 | 757 | }, |
940ab889 | 758 | .probe = ep93xx_spi_probe, |
fd4a319b | 759 | .remove = ep93xx_spi_remove, |
011f23a3 | 760 | }; |
940ab889 | 761 | module_platform_driver(ep93xx_spi_driver); |
011f23a3 MW |
762 | |
763 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); | |
764 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | |
765 | MODULE_LICENSE("GPL"); | |
766 | MODULE_ALIAS("platform:ep93xx-spi"); |