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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
86f8973c UKK |
2 | /* |
3 | * Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix | |
86f8973c UKK |
4 | */ |
5 | #include <linux/kernel.h> | |
6 | #include <linux/io.h> | |
7 | #include <linux/spi/spi.h> | |
8 | #include <linux/spi/spi_bitbang.h> | |
86f8973c UKK |
9 | #include <linux/interrupt.h> |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/module.h> | |
86f8973c | 14 | #include <linux/platform_data/efm32-spi.h> |
ebb3b9a9 | 15 | #include <linux/of.h> |
86f8973c UKK |
16 | |
17 | #define DRIVER_NAME "efm32-spi" | |
18 | ||
19 | #define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) | |
20 | ||
21 | #define REG_CTRL 0x00 | |
22 | #define REG_CTRL_SYNC 0x0001 | |
23 | #define REG_CTRL_CLKPOL 0x0100 | |
24 | #define REG_CTRL_CLKPHA 0x0200 | |
25 | #define REG_CTRL_MSBF 0x0400 | |
26 | #define REG_CTRL_TXBIL 0x1000 | |
27 | ||
28 | #define REG_FRAME 0x04 | |
29 | #define REG_FRAME_DATABITS__MASK 0x000f | |
30 | #define REG_FRAME_DATABITS(n) ((n) - 3) | |
31 | ||
32 | #define REG_CMD 0x0c | |
33 | #define REG_CMD_RXEN 0x0001 | |
34 | #define REG_CMD_RXDIS 0x0002 | |
35 | #define REG_CMD_TXEN 0x0004 | |
36 | #define REG_CMD_TXDIS 0x0008 | |
37 | #define REG_CMD_MASTEREN 0x0010 | |
38 | ||
39 | #define REG_STATUS 0x10 | |
40 | #define REG_STATUS_TXENS 0x0002 | |
41 | #define REG_STATUS_TXC 0x0020 | |
42 | #define REG_STATUS_TXBL 0x0040 | |
43 | #define REG_STATUS_RXDATAV 0x0080 | |
44 | ||
45 | #define REG_CLKDIV 0x14 | |
46 | ||
47 | #define REG_RXDATAX 0x18 | |
48 | #define REG_RXDATAX_RXDATA__MASK 0x01ff | |
49 | #define REG_RXDATAX_PERR 0x4000 | |
50 | #define REG_RXDATAX_FERR 0x8000 | |
51 | ||
52 | #define REG_TXDATA 0x34 | |
53 | ||
54 | #define REG_IF 0x40 | |
55 | #define REG_IF_TXBL 0x0002 | |
56 | #define REG_IF_RXDATAV 0x0004 | |
57 | ||
58 | #define REG_IFS 0x44 | |
59 | #define REG_IFC 0x48 | |
60 | #define REG_IEN 0x4c | |
61 | ||
62 | #define REG_ROUTE 0x54 | |
63 | #define REG_ROUTE_RXPEN 0x0001 | |
64 | #define REG_ROUTE_TXPEN 0x0002 | |
65 | #define REG_ROUTE_CLKPEN 0x0008 | |
66 | #define REG_ROUTE_LOCATION__MASK 0x0700 | |
67 | #define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n)) | |
68 | ||
69 | struct efm32_spi_ddata { | |
70 | struct spi_bitbang bitbang; | |
71 | ||
72 | spinlock_t lock; | |
73 | ||
74 | struct clk *clk; | |
75 | void __iomem *base; | |
76 | unsigned int rxirq, txirq; | |
77 | struct efm32_spi_pdata pdata; | |
78 | ||
79 | /* irq data */ | |
80 | struct completion done; | |
81 | const u8 *tx_buf; | |
82 | u8 *rx_buf; | |
83 | unsigned tx_len, rx_len; | |
86f8973c UKK |
84 | }; |
85 | ||
86 | #define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev)) | |
87 | #define efm32_spi_vdbg(ddata, format, arg...) \ | |
88 | dev_vdbg(ddata_to_dev(ddata), format, ##arg) | |
89 | ||
90 | static void efm32_spi_write32(struct efm32_spi_ddata *ddata, | |
91 | u32 value, unsigned offset) | |
92 | { | |
93 | writel_relaxed(value, ddata->base + offset); | |
94 | } | |
95 | ||
96 | static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset) | |
97 | { | |
98 | return readl_relaxed(ddata->base + offset); | |
99 | } | |
100 | ||
86f8973c UKK |
101 | static int efm32_spi_setup_transfer(struct spi_device *spi, |
102 | struct spi_transfer *t) | |
103 | { | |
104 | struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); | |
105 | ||
106 | unsigned bpw = t->bits_per_word ?: spi->bits_per_word; | |
107 | unsigned speed = t->speed_hz ?: spi->max_speed_hz; | |
108 | unsigned long clkfreq = clk_get_rate(ddata->clk); | |
109 | u32 clkdiv; | |
110 | ||
111 | efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF | | |
112 | (spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) | | |
113 | (spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL); | |
114 | ||
115 | efm32_spi_write32(ddata, | |
116 | REG_FRAME_DATABITS(bpw), REG_FRAME); | |
117 | ||
118 | if (2 * speed >= clkfreq) | |
119 | clkdiv = 0; | |
120 | else | |
121 | clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4); | |
122 | ||
123 | if (clkdiv > (1U << 21)) | |
124 | return -EINVAL; | |
125 | ||
126 | efm32_spi_write32(ddata, clkdiv, REG_CLKDIV); | |
127 | efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD); | |
128 | efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata) | |
134 | { | |
135 | u8 val = 0; | |
136 | ||
137 | if (ddata->tx_buf) { | |
138 | val = *ddata->tx_buf; | |
139 | ddata->tx_buf++; | |
140 | } | |
141 | ||
142 | ddata->tx_len--; | |
143 | efm32_spi_write32(ddata, val, REG_TXDATA); | |
144 | efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val); | |
145 | } | |
146 | ||
147 | static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata) | |
148 | { | |
149 | u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX); | |
150 | efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata); | |
151 | ||
152 | if (ddata->rx_buf) { | |
153 | *ddata->rx_buf = rxdata; | |
154 | ddata->rx_buf++; | |
155 | } | |
156 | ||
157 | ddata->rx_len--; | |
158 | } | |
159 | ||
160 | static void efm32_spi_filltx(struct efm32_spi_ddata *ddata) | |
161 | { | |
162 | while (ddata->tx_len && | |
163 | ddata->tx_len + 2 > ddata->rx_len && | |
164 | efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) { | |
165 | efm32_spi_tx_u8(ddata); | |
166 | } | |
167 | } | |
168 | ||
169 | static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |
170 | { | |
171 | struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); | |
172 | int ret = -EBUSY; | |
173 | ||
174 | spin_lock_irq(&ddata->lock); | |
175 | ||
176 | if (ddata->tx_buf || ddata->rx_buf) | |
177 | goto out_unlock; | |
178 | ||
179 | ddata->tx_buf = t->tx_buf; | |
180 | ddata->rx_buf = t->rx_buf; | |
181 | ddata->tx_len = ddata->rx_len = | |
182 | t->len * DIV_ROUND_UP(t->bits_per_word, 8); | |
183 | ||
184 | efm32_spi_filltx(ddata); | |
185 | ||
aa0fe826 | 186 | reinit_completion(&ddata->done); |
86f8973c UKK |
187 | |
188 | efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN); | |
189 | ||
190 | spin_unlock_irq(&ddata->lock); | |
191 | ||
192 | wait_for_completion(&ddata->done); | |
193 | ||
194 | spin_lock_irq(&ddata->lock); | |
195 | ||
196 | ret = t->len - max(ddata->tx_len, ddata->rx_len); | |
197 | ||
198 | efm32_spi_write32(ddata, 0, REG_IEN); | |
199 | ddata->tx_buf = ddata->rx_buf = NULL; | |
200 | ||
201 | out_unlock: | |
202 | spin_unlock_irq(&ddata->lock); | |
203 | ||
204 | return ret; | |
205 | } | |
206 | ||
207 | static irqreturn_t efm32_spi_rxirq(int irq, void *data) | |
208 | { | |
209 | struct efm32_spi_ddata *ddata = data; | |
210 | irqreturn_t ret = IRQ_NONE; | |
211 | ||
212 | spin_lock(&ddata->lock); | |
213 | ||
214 | while (ddata->rx_len > 0 && | |
215 | efm32_spi_read32(ddata, REG_STATUS) & | |
216 | REG_STATUS_RXDATAV) { | |
217 | efm32_spi_rx_u8(ddata); | |
218 | ||
219 | ret = IRQ_HANDLED; | |
220 | } | |
221 | ||
222 | if (!ddata->rx_len) { | |
223 | u32 ien = efm32_spi_read32(ddata, REG_IEN); | |
224 | ||
225 | ien &= ~REG_IF_RXDATAV; | |
226 | ||
227 | efm32_spi_write32(ddata, ien, REG_IEN); | |
228 | ||
229 | complete(&ddata->done); | |
230 | } | |
231 | ||
232 | spin_unlock(&ddata->lock); | |
233 | ||
234 | return ret; | |
235 | } | |
236 | ||
237 | static irqreturn_t efm32_spi_txirq(int irq, void *data) | |
238 | { | |
239 | struct efm32_spi_ddata *ddata = data; | |
240 | ||
241 | efm32_spi_vdbg(ddata, | |
242 | "%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n", | |
243 | __func__, ddata->tx_len, ddata->rx_len, | |
244 | efm32_spi_read32(ddata, REG_IF), | |
245 | efm32_spi_read32(ddata, REG_STATUS)); | |
246 | ||
247 | spin_lock(&ddata->lock); | |
248 | ||
249 | efm32_spi_filltx(ddata); | |
250 | ||
251 | efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n", | |
252 | __func__, ddata->tx_len, ddata->rx_len); | |
253 | ||
254 | if (!ddata->tx_len) { | |
255 | u32 ien = efm32_spi_read32(ddata, REG_IEN); | |
256 | ||
257 | ien &= ~REG_IF_TXBL; | |
258 | ||
259 | efm32_spi_write32(ddata, ien, REG_IEN); | |
260 | efm32_spi_vdbg(ddata, "disable TXBL\n"); | |
261 | } | |
262 | ||
263 | spin_unlock(&ddata->lock); | |
264 | ||
265 | return IRQ_HANDLED; | |
266 | } | |
267 | ||
86f8973c UKK |
268 | static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata) |
269 | { | |
270 | u32 reg = efm32_spi_read32(ddata, REG_ROUTE); | |
271 | ||
272 | return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK); | |
273 | } | |
274 | ||
f9f4cbde | 275 | static void efm32_spi_probe_dt(struct platform_device *pdev, |
86f8973c UKK |
276 | struct spi_master *master, struct efm32_spi_ddata *ddata) |
277 | { | |
278 | struct device_node *np = pdev->dev.of_node; | |
279 | u32 location; | |
280 | int ret; | |
281 | ||
10ed7e98 UKK |
282 | ret = of_property_read_u32(np, "energymicro,location", &location); |
283 | ||
284 | if (ret) | |
285 | /* fall back to wrongly namespaced property */ | |
286 | ret = of_property_read_u32(np, "efm32,location", &location); | |
287 | ||
f2bb3105 UKK |
288 | if (ret) |
289 | /* fall back to old and (wrongly) generic property "location" */ | |
290 | ret = of_property_read_u32(np, "location", &location); | |
10ed7e98 | 291 | |
86f8973c UKK |
292 | if (!ret) { |
293 | dev_dbg(&pdev->dev, "using location %u\n", location); | |
294 | } else { | |
295 | /* default to location configured in hardware */ | |
296 | location = efm32_spi_get_configured_location(ddata); | |
297 | ||
298 | dev_info(&pdev->dev, "fall back to location %u\n", location); | |
299 | } | |
300 | ||
301 | ddata->pdata.location = location; | |
86f8973c UKK |
302 | } |
303 | ||
304 | static int efm32_spi_probe(struct platform_device *pdev) | |
305 | { | |
306 | struct efm32_spi_ddata *ddata; | |
307 | struct resource *res; | |
308 | int ret; | |
309 | struct spi_master *master; | |
310 | struct device_node *np = pdev->dev.of_node; | |
f9f4cbde AL |
311 | |
312 | if (!np) | |
313 | return -EINVAL; | |
86f8973c | 314 | |
ebb3b9a9 | 315 | master = spi_alloc_master(&pdev->dev, sizeof(*ddata)); |
86f8973c UKK |
316 | if (!master) { |
317 | dev_dbg(&pdev->dev, | |
318 | "failed to allocate spi master controller\n"); | |
319 | return -ENOMEM; | |
320 | } | |
321 | platform_set_drvdata(pdev, master); | |
322 | ||
323 | master->dev.of_node = pdev->dev.of_node; | |
324 | ||
86f8973c UKK |
325 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
326 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
ebb3b9a9 | 327 | master->use_gpio_descriptors = true; |
86f8973c UKK |
328 | |
329 | ddata = spi_master_get_devdata(master); | |
330 | ||
702a4879 | 331 | ddata->bitbang.master = master; |
86f8973c UKK |
332 | ddata->bitbang.setup_transfer = efm32_spi_setup_transfer; |
333 | ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs; | |
334 | ||
335 | spin_lock_init(&ddata->lock); | |
aa0fe826 | 336 | init_completion(&ddata->done); |
86f8973c UKK |
337 | |
338 | ddata->clk = devm_clk_get(&pdev->dev, NULL); | |
339 | if (IS_ERR(ddata->clk)) { | |
340 | ret = PTR_ERR(ddata->clk); | |
341 | dev_err(&pdev->dev, "failed to get clock: %d\n", ret); | |
342 | goto err; | |
343 | } | |
344 | ||
86f8973c UKK |
345 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
346 | if (!res) { | |
347 | ret = -ENODEV; | |
348 | dev_err(&pdev->dev, "failed to determine base address\n"); | |
349 | goto err; | |
350 | } | |
351 | ||
6a009e8d | 352 | if (resource_size(res) < 0x60) { |
86f8973c UKK |
353 | ret = -EINVAL; |
354 | dev_err(&pdev->dev, "memory resource too small\n"); | |
355 | goto err; | |
356 | } | |
357 | ||
358 | ddata->base = devm_ioremap_resource(&pdev->dev, res); | |
359 | if (IS_ERR(ddata->base)) { | |
360 | ret = PTR_ERR(ddata->base); | |
86f8973c UKK |
361 | goto err; |
362 | } | |
363 | ||
364 | ret = platform_get_irq(pdev, 0); | |
6b8ac10e | 365 | if (ret <= 0) |
86f8973c | 366 | goto err; |
86f8973c UKK |
367 | |
368 | ddata->rxirq = ret; | |
369 | ||
370 | ret = platform_get_irq(pdev, 1); | |
371 | if (ret <= 0) | |
372 | ret = ddata->rxirq + 1; | |
373 | ||
374 | ddata->txirq = ret; | |
375 | ||
376 | ret = clk_prepare_enable(ddata->clk); | |
377 | if (ret < 0) { | |
378 | dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret); | |
379 | goto err; | |
380 | } | |
381 | ||
f9f4cbde | 382 | efm32_spi_probe_dt(pdev, master, ddata); |
86f8973c UKK |
383 | |
384 | efm32_spi_write32(ddata, 0, REG_IEN); | |
385 | efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN | | |
386 | REG_ROUTE_CLKPEN | | |
387 | REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE); | |
388 | ||
389 | ret = request_irq(ddata->rxirq, efm32_spi_rxirq, | |
390 | 0, DRIVER_NAME " rx", ddata); | |
391 | if (ret) { | |
392 | dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret); | |
393 | goto err_disable_clk; | |
394 | } | |
395 | ||
396 | ret = request_irq(ddata->txirq, efm32_spi_txirq, | |
397 | 0, DRIVER_NAME " tx", ddata); | |
398 | if (ret) { | |
399 | dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret); | |
400 | goto err_free_rx_irq; | |
401 | } | |
402 | ||
403 | ret = spi_bitbang_start(&ddata->bitbang); | |
404 | if (ret) { | |
405 | dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret); | |
406 | ||
407 | free_irq(ddata->txirq, ddata); | |
408 | err_free_rx_irq: | |
409 | free_irq(ddata->rxirq, ddata); | |
410 | err_disable_clk: | |
411 | clk_disable_unprepare(ddata->clk); | |
412 | err: | |
413 | spi_master_put(master); | |
86f8973c UKK |
414 | } |
415 | ||
416 | return ret; | |
417 | } | |
418 | ||
419 | static int efm32_spi_remove(struct platform_device *pdev) | |
420 | { | |
421 | struct spi_master *master = platform_get_drvdata(pdev); | |
422 | struct efm32_spi_ddata *ddata = spi_master_get_devdata(master); | |
423 | ||
e6f7563b UKK |
424 | spi_bitbang_stop(&ddata->bitbang); |
425 | ||
86f8973c UKK |
426 | efm32_spi_write32(ddata, 0, REG_IEN); |
427 | ||
428 | free_irq(ddata->txirq, ddata); | |
429 | free_irq(ddata->rxirq, ddata); | |
430 | clk_disable_unprepare(ddata->clk); | |
431 | spi_master_put(master); | |
86f8973c UKK |
432 | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static const struct of_device_id efm32_spi_dt_ids[] = { | |
437 | { | |
12f6dd86 UKK |
438 | .compatible = "energymicro,efm32-spi", |
439 | }, { | |
440 | /* doesn't follow the "vendor,device" scheme, don't use */ | |
86f8973c UKK |
441 | .compatible = "efm32,spi", |
442 | }, { | |
443 | /* sentinel */ | |
444 | } | |
445 | }; | |
d8851a0d | 446 | MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids); |
86f8973c UKK |
447 | |
448 | static struct platform_driver efm32_spi_driver = { | |
449 | .probe = efm32_spi_probe, | |
450 | .remove = efm32_spi_remove, | |
451 | ||
452 | .driver = { | |
453 | .name = DRIVER_NAME, | |
86f8973c UKK |
454 | .of_match_table = efm32_spi_dt_ids, |
455 | }, | |
456 | }; | |
457 | module_platform_driver(efm32_spi_driver); | |
458 | ||
459 | MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>"); | |
460 | MODULE_DESCRIPTION("EFM32 SPI driver"); | |
461 | MODULE_LICENSE("GPL v2"); | |
462 | MODULE_ALIAS("platform:" DRIVER_NAME); |