Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e24c7452 FT |
2 | #ifndef DW_SPI_HEADER_H |
3 | #define DW_SPI_HEADER_H | |
7063c0d9 | 4 | |
e24c7452 | 5 | #include <linux/io.h> |
46165a3d | 6 | #include <linux/scatterlist.h> |
d9c73bb8 | 7 | #include <linux/gpio.h> |
e24c7452 | 8 | |
7eb187b3 HS |
9 | /* Register offsets */ |
10 | #define DW_SPI_CTRL0 0x00 | |
11 | #define DW_SPI_CTRL1 0x04 | |
12 | #define DW_SPI_SSIENR 0x08 | |
13 | #define DW_SPI_MWCR 0x0c | |
14 | #define DW_SPI_SER 0x10 | |
15 | #define DW_SPI_BAUDR 0x14 | |
16 | #define DW_SPI_TXFLTR 0x18 | |
17 | #define DW_SPI_RXFLTR 0x1c | |
18 | #define DW_SPI_TXFLR 0x20 | |
19 | #define DW_SPI_RXFLR 0x24 | |
20 | #define DW_SPI_SR 0x28 | |
21 | #define DW_SPI_IMR 0x2c | |
22 | #define DW_SPI_ISR 0x30 | |
23 | #define DW_SPI_RISR 0x34 | |
24 | #define DW_SPI_TXOICR 0x38 | |
25 | #define DW_SPI_RXOICR 0x3c | |
26 | #define DW_SPI_RXUICR 0x40 | |
27 | #define DW_SPI_MSTICR 0x44 | |
28 | #define DW_SPI_ICR 0x48 | |
29 | #define DW_SPI_DMACR 0x4c | |
30 | #define DW_SPI_DMATDLR 0x50 | |
31 | #define DW_SPI_DMARDLR 0x54 | |
32 | #define DW_SPI_IDR 0x58 | |
33 | #define DW_SPI_VERSION 0x5c | |
34 | #define DW_SPI_DR 0x60 | |
f2d70479 | 35 | #define DW_SPI_CS_OVERRIDE 0xf4 |
7eb187b3 | 36 | |
e24c7452 FT |
37 | /* Bit fields in CTRLR0 */ |
38 | #define SPI_DFS_OFFSET 0 | |
39 | ||
40 | #define SPI_FRF_OFFSET 4 | |
41 | #define SPI_FRF_SPI 0x0 | |
42 | #define SPI_FRF_SSP 0x1 | |
43 | #define SPI_FRF_MICROWIRE 0x2 | |
44 | #define SPI_FRF_RESV 0x3 | |
45 | ||
46 | #define SPI_MODE_OFFSET 6 | |
47 | #define SPI_SCPH_OFFSET 6 | |
48 | #define SPI_SCOL_OFFSET 7 | |
e3e55ff5 | 49 | |
e24c7452 | 50 | #define SPI_TMOD_OFFSET 8 |
e3e55ff5 | 51 | #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) |
e24c7452 FT |
52 | #define SPI_TMOD_TR 0x0 /* xmit & recv */ |
53 | #define SPI_TMOD_TO 0x1 /* xmit only */ | |
54 | #define SPI_TMOD_RO 0x2 /* recv only */ | |
55 | #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ | |
56 | ||
57 | #define SPI_SLVOE_OFFSET 10 | |
58 | #define SPI_SRL_OFFSET 11 | |
59 | #define SPI_CFS_OFFSET 12 | |
60 | ||
61 | /* Bit fields in SR, 7 bits */ | |
62 | #define SR_MASK 0x7f /* cover 7 bits */ | |
63 | #define SR_BUSY (1 << 0) | |
64 | #define SR_TF_NOT_FULL (1 << 1) | |
65 | #define SR_TF_EMPT (1 << 2) | |
66 | #define SR_RF_NOT_EMPT (1 << 3) | |
67 | #define SR_RF_FULL (1 << 4) | |
68 | #define SR_TX_ERR (1 << 5) | |
69 | #define SR_DCOL (1 << 6) | |
70 | ||
71 | /* Bit fields in ISR, IMR, RISR, 7 bits */ | |
72 | #define SPI_INT_TXEI (1 << 0) | |
73 | #define SPI_INT_TXOI (1 << 1) | |
74 | #define SPI_INT_RXUI (1 << 2) | |
75 | #define SPI_INT_RXOI (1 << 3) | |
76 | #define SPI_INT_RXFI (1 << 4) | |
77 | #define SPI_INT_MSTI (1 << 5) | |
78 | ||
15ee3be7 AS |
79 | /* Bit fields in DMACR */ |
80 | #define SPI_DMA_RDMAE (1 << 0) | |
81 | #define SPI_DMA_TDMAE (1 << 1) | |
82 | ||
25985edc | 83 | /* TX RX interrupt level threshold, max can be 256 */ |
e24c7452 FT |
84 | #define SPI_INT_THRESHOLD 32 |
85 | ||
86 | enum dw_ssi_type { | |
87 | SSI_MOTO_SPI = 0, | |
88 | SSI_TI_SSP, | |
89 | SSI_NS_MICROWIRE, | |
90 | }; | |
91 | ||
7063c0d9 FT |
92 | struct dw_spi; |
93 | struct dw_spi_dma_ops { | |
94 | int (*dma_init)(struct dw_spi *dws); | |
95 | void (*dma_exit)(struct dw_spi *dws); | |
f89a6d8f | 96 | int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); |
721483e2 | 97 | bool (*can_dma)(struct spi_controller *master, struct spi_device *spi, |
f89a6d8f AS |
98 | struct spi_transfer *xfer); |
99 | int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); | |
4d5ac1ed | 100 | void (*dma_stop)(struct dw_spi *dws); |
7063c0d9 FT |
101 | }; |
102 | ||
e24c7452 | 103 | struct dw_spi { |
721483e2 | 104 | struct spi_controller *master; |
e24c7452 FT |
105 | enum dw_ssi_type type; |
106 | ||
107 | void __iomem *regs; | |
108 | unsigned long paddr; | |
e24c7452 | 109 | int irq; |
552e4509 | 110 | u32 fifo_len; /* depth of the FIFO buffer */ |
e24c7452 FT |
111 | u32 max_freq; /* max bus freq supported */ |
112 | ||
f2d70479 | 113 | int cs_override; |
c4fe57f7 | 114 | u32 reg_io_width; /* DR I/O width in bytes */ |
e24c7452 FT |
115 | u16 bus_num; |
116 | u16 num_cs; /* supported slave numbers */ | |
62dbbae4 | 117 | void (*set_cs)(struct spi_device *spi, bool enable); |
e24c7452 | 118 | |
e24c7452 | 119 | /* Current message transfer state info */ |
e24c7452 FT |
120 | size_t len; |
121 | void *tx; | |
122 | void *tx_end; | |
123 | void *rx; | |
124 | void *rx_end; | |
125 | int dma_mapped; | |
e24c7452 | 126 | u8 n_bytes; /* current is a 1/2 bytes op */ |
e24c7452 | 127 | u32 dma_width; |
e24c7452 | 128 | irqreturn_t (*transfer_handler)(struct dw_spi *dws); |
13b10301 | 129 | u32 current_freq; /* frequency in hz */ |
e24c7452 | 130 | |
f89a6d8f | 131 | /* DMA info */ |
e24c7452 FT |
132 | int dma_inited; |
133 | struct dma_chan *txchan; | |
134 | struct dma_chan *rxchan; | |
30c8eb52 | 135 | unsigned long dma_chan_busy; |
7063c0d9 | 136 | dma_addr_t dma_addr; /* phy address of the Data register */ |
4fe338c9 | 137 | const struct dw_spi_dma_ops *dma_ops; |
d744f826 AS |
138 | void *dma_tx; |
139 | void *dma_rx; | |
e24c7452 FT |
140 | |
141 | /* Bus interface info */ | |
142 | void *priv; | |
143 | #ifdef CONFIG_DEBUG_FS | |
144 | struct dentry *debugfs; | |
145 | #endif | |
146 | }; | |
147 | ||
7eb187b3 HS |
148 | static inline u32 dw_readl(struct dw_spi *dws, u32 offset) |
149 | { | |
150 | return __raw_readl(dws->regs + offset); | |
151 | } | |
152 | ||
c4fe57f7 MW |
153 | static inline u16 dw_readw(struct dw_spi *dws, u32 offset) |
154 | { | |
155 | return __raw_readw(dws->regs + offset); | |
156 | } | |
157 | ||
7eb187b3 HS |
158 | static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) |
159 | { | |
160 | __raw_writel(val, dws->regs + offset); | |
161 | } | |
162 | ||
c4fe57f7 MW |
163 | static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) |
164 | { | |
165 | __raw_writew(val, dws->regs + offset); | |
166 | } | |
167 | ||
168 | static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) | |
169 | { | |
170 | switch (dws->reg_io_width) { | |
171 | case 2: | |
172 | return dw_readw(dws, offset); | |
173 | case 4: | |
174 | default: | |
175 | return dw_readl(dws, offset); | |
176 | } | |
177 | } | |
178 | ||
179 | static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) | |
180 | { | |
181 | switch (dws->reg_io_width) { | |
182 | case 2: | |
183 | dw_writew(dws, offset, val); | |
184 | break; | |
185 | case 4: | |
186 | default: | |
187 | dw_writel(dws, offset, val); | |
188 | break; | |
189 | } | |
190 | } | |
191 | ||
e24c7452 FT |
192 | static inline void spi_enable_chip(struct dw_spi *dws, int enable) |
193 | { | |
7eb187b3 | 194 | dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); |
e24c7452 FT |
195 | } |
196 | ||
197 | static inline void spi_set_clk(struct dw_spi *dws, u16 div) | |
198 | { | |
7eb187b3 | 199 | dw_writel(dws, DW_SPI_BAUDR, div); |
e24c7452 FT |
200 | } |
201 | ||
e24c7452 FT |
202 | /* Disable IRQ bits */ |
203 | static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) | |
204 | { | |
205 | u32 new_mask; | |
206 | ||
7eb187b3 HS |
207 | new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; |
208 | dw_writel(dws, DW_SPI_IMR, new_mask); | |
e24c7452 FT |
209 | } |
210 | ||
211 | /* Enable IRQ bits */ | |
212 | static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) | |
213 | { | |
214 | u32 new_mask; | |
215 | ||
7eb187b3 HS |
216 | new_mask = dw_readl(dws, DW_SPI_IMR) | mask; |
217 | dw_writel(dws, DW_SPI_IMR, new_mask); | |
e24c7452 FT |
218 | } |
219 | ||
45746e82 AS |
220 | /* |
221 | * This does disable the SPI controller, interrupts, and re-enable the | |
222 | * controller back. Transmit and receive FIFO buffers are cleared when the | |
223 | * device is disabled. | |
224 | */ | |
225 | static inline void spi_reset_chip(struct dw_spi *dws) | |
226 | { | |
227 | spi_enable_chip(dws, 0); | |
228 | spi_mask_intr(dws, 0xff); | |
229 | spi_enable_chip(dws, 1); | |
230 | } | |
231 | ||
1cc3f141 AS |
232 | static inline void spi_shutdown_chip(struct dw_spi *dws) |
233 | { | |
234 | spi_enable_chip(dws, 0); | |
235 | spi_set_clk(dws, 0); | |
236 | } | |
237 | ||
e24c7452 FT |
238 | /* |
239 | * Each SPI slave device to work with dw_api controller should | |
f89a6d8f | 240 | * has such a structure claiming its working mode (poll or PIO/DMA), |
e24c7452 | 241 | * which can be save in the "controller_data" member of the |
05ed2aee | 242 | * struct spi_device. |
e24c7452 FT |
243 | */ |
244 | struct dw_spi_chip { | |
05ed2aee AS |
245 | u8 poll_mode; /* 1 for controller polling mode */ |
246 | u8 type; /* SPI/SSP/MicroWire */ | |
e24c7452 FT |
247 | void (*cs_control)(u32 command); |
248 | }; | |
249 | ||
c79bdbb4 | 250 | extern void dw_spi_set_cs(struct spi_device *spi, bool enable); |
04f421e7 | 251 | extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); |
e24c7452 FT |
252 | extern void dw_spi_remove_host(struct dw_spi *dws); |
253 | extern int dw_spi_suspend_host(struct dw_spi *dws); | |
254 | extern int dw_spi_resume_host(struct dw_spi *dws); | |
7063c0d9 FT |
255 | |
256 | /* platform related setup */ | |
257 | extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ | |
e24c7452 | 258 | #endif /* DW_SPI_HEADER_H */ |