[linux-2.6-block.git] / drivers / spi / spi-dw.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DW_SPI_HEADER_H
#define DW_SPI_HEADER_H

#include <linux/bits.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/irqreturn.h>
#include <linux/io.h>
#include <linux/scatterlist.h>
#include <linux/spi/spi-mem.h>

/* Register offsets */
#define DW_SPI_CTRLR0			0x00
#define DW_SPI_CTRLR1			0x04
#define DW_SPI_SSIENR			0x08
#define DW_SPI_MWCR			0x0c
#define DW_SPI_SER			0x10
#define DW_SPI_BAUDR			0x14
#define DW_SPI_TXFTLR			0x18
#define DW_SPI_RXFTLR			0x1c
#define DW_SPI_TXFLR			0x20
#define DW_SPI_RXFLR			0x24
#define DW_SPI_SR			0x28
#define DW_SPI_IMR			0x2c
#define DW_SPI_ISR			0x30
#define DW_SPI_RISR			0x34
#define DW_SPI_TXOICR			0x38
#define DW_SPI_RXOICR			0x3c
#define DW_SPI_RXUICR			0x40
#define DW_SPI_MSTICR			0x44
#define DW_SPI_ICR			0x48
#define DW_SPI_DMACR			0x4c
#define DW_SPI_DMATDLR			0x50
#define DW_SPI_DMARDLR			0x54
#define DW_SPI_IDR			0x58
#define DW_SPI_VERSION			0x5c
#define DW_SPI_DR			0x60
#define DW_SPI_RX_SAMPLE_DLY		0xf0
#define DW_SPI_CS_OVERRIDE		0xf4

/* Bit fields in CTRLR0 */
#define SPI_DFS_OFFSET			0

#define SPI_FRF_OFFSET			4
#define SPI_FRF_SPI			0x0
#define SPI_FRF_SSP			0x1
#define SPI_FRF_MICROWIRE		0x2
#define SPI_FRF_RESV			0x3

#define SPI_MODE_OFFSET			6
#define SPI_SCPH_OFFSET			6
#define SPI_SCOL_OFFSET			7

#define SPI_TMOD_OFFSET			8
#define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
#define	SPI_TMOD_TR			0x0		/* xmit & recv */
#define SPI_TMOD_TO			0x1		/* xmit only */
#define SPI_TMOD_RO			0x2		/* recv only */
#define SPI_TMOD_EPROMREAD		0x3		/* eeprom read mode */

#define SPI_SLVOE_OFFSET		10
#define SPI_SRL_OFFSET			11
#define SPI_CFS_OFFSET			12

/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
#define DWC_SSI_CTRLR0_SRL_OFFSET	13
#define DWC_SSI_CTRLR0_TMOD_OFFSET	10
#define DWC_SSI_CTRLR0_TMOD_MASK	GENMASK(11, 10)
#define DWC_SSI_CTRLR0_SCPOL_OFFSET	9
#define DWC_SSI_CTRLR0_SCPH_OFFSET	8
#define DWC_SSI_CTRLR0_FRF_OFFSET	6
#define DWC_SSI_CTRLR0_DFS_OFFSET	0

/*
 * For Keem Bay, CTRLR0[31] is used to select controller mode.
 * 0: SSI is slave
 * 1: SSI is master
 */
#define DWC_SSI_CTRLR0_KEEMBAY_MST	BIT(31)

/* Bit fields in CTRLR1 */
#define SPI_NDF_MASK			GENMASK(15, 0)

/* Bit fields in SR, 7 bits */
#define SR_MASK				0x7f		/* cover 7 bits */
#define SR_BUSY				(1 << 0)
#define SR_TF_NOT_FULL			(1 << 1)
#define SR_TF_EMPT			(1 << 2)
#define SR_RF_NOT_EMPT			(1 << 3)
#define SR_RF_FULL			(1 << 4)
#define SR_TX_ERR			(1 << 5)
#define SR_DCOL				(1 << 6)

/* Bit fields in ISR, IMR, RISR, 7 bits */
#define SPI_INT_TXEI			(1 << 0)
#define SPI_INT_TXOI			(1 << 1)
#define SPI_INT_RXUI			(1 << 2)
#define SPI_INT_RXOI			(1 << 3)
#define SPI_INT_RXFI			(1 << 4)
#define SPI_INT_MSTI			(1 << 5)

/* Bit fields in DMACR */
#define SPI_DMA_RDMAE			(1 << 0)
#define SPI_DMA_TDMAE			(1 << 1)

#define SPI_WAIT_RETRIES		5
#define SPI_BUF_SIZE \
	(sizeof_field(struct spi_mem_op, cmd.opcode) + \
	 sizeof_field(struct spi_mem_op, addr.val) + 256)
#define SPI_GET_BYTE(_val, _idx) \
	((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)

enum dw_ssi_type {
	SSI_MOTO_SPI = 0,
	SSI_TI_SSP,
	SSI_NS_MICROWIRE,
};

/* DW SPI capabilities */
#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
#define DW_SPI_CAP_KEEMBAY_MST		BIT(1)
#define DW_SPI_CAP_DWC_SSI		BIT(2)

/* Slave spi_transfer/spi_mem_op related */
struct dw_spi_cfg {
	u8 tmode;
	u8 dfs;
	u32 ndf;
	u32 freq;
};

struct dw_spi;
struct dw_spi_dma_ops {
	int (*dma_init)(struct device *dev, struct dw_spi *dws);
	void (*dma_exit)(struct dw_spi *dws);
	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
	bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
			struct spi_transfer *xfer);
	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
	void (*dma_stop)(struct dw_spi *dws);
};

struct dw_spi {
	struct spi_controller	*master;

	void __iomem		*regs;
	unsigned long		paddr;
	int			irq;
	u32			fifo_len;	/* depth of the FIFO buffer */
	u32			max_freq;	/* max bus freq supported */

	u32			caps;		/* DW SPI capabilities */

	u32			reg_io_width;	/* DR I/O width in bytes */
	u16			bus_num;
	u16			num_cs;		/* supported slave numbers */
	void (*set_cs)(struct spi_device *spi, bool enable);

	/* Current message transfer state info */
	void			*tx;
	unsigned int		tx_len;
	void			*rx;
	unsigned int		rx_len;
	u8			buf[SPI_BUF_SIZE];
	int			dma_mapped;
	u8			n_bytes;	/* current is a 1/2 bytes op */
	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
	u32			current_freq;	/* frequency in hz */
	u32			cur_rx_sample_dly;
	u32			def_rx_sample_dly_ns;

	/* Custom memory operations */
	struct spi_controller_mem_ops mem_ops;

	/* DMA info */
	struct dma_chan		*txchan;
	u32			txburst;
	struct dma_chan		*rxchan;
	u32			rxburst;
	u32			dma_sg_burst;
	unsigned long		dma_chan_busy;
	dma_addr_t		dma_addr; /* phy address of the Data register */
	const struct dw_spi_dma_ops *dma_ops;
	struct completion	dma_completion;

#ifdef CONFIG_DEBUG_FS
	struct dentry *debugfs;
	struct debugfs_regset32 regset;
#endif
};

static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
{
	return __raw_readl(dws->regs + offset);
}

static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
	__raw_writel(val, dws->regs + offset);
}

static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
{
	switch (dws->reg_io_width) {
	case 2:
		return readw_relaxed(dws->regs + offset);
	case 4:
	default:
		return readl_relaxed(dws->regs + offset);
	}
}

static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
{
	switch (dws->reg_io_width) {
	case 2:
		writew_relaxed(val, dws->regs + offset);
		break;
	case 4:
	default:
		writel_relaxed(val, dws->regs + offset);
		break;
	}
}

static inline void spi_enable_chip(struct dw_spi *dws, int enable)
{
	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
}

static inline void spi_set_clk(struct dw_spi *dws, u16 div)
{
	dw_writel(dws, DW_SPI_BAUDR, div);
}

/* Disable IRQ bits */
static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/* Enable IRQ bits */
static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/*
 * This disables the SPI controller, interrupts, clears the interrupts status
 * and CS, then re-enables the controller back. Transmit and receive FIFO
 * buffers are cleared when the device is disabled.
 */
static inline void spi_reset_chip(struct dw_spi *dws)
{
	spi_enable_chip(dws, 0);
	spi_mask_intr(dws, 0xff);
	dw_readl(dws, DW_SPI_ICR);
	dw_writel(dws, DW_SPI_SER, 0);
	spi_enable_chip(dws, 1);
}

static inline void spi_shutdown_chip(struct dw_spi *dws)
{
	spi_enable_chip(dws, 0);
	spi_set_clk(dws, 0);
}

extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
				 struct dw_spi_cfg *cfg);
extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
extern void dw_spi_remove_host(struct dw_spi *dws);
extern int dw_spi_suspend_host(struct dw_spi *dws);
extern int dw_spi_resume_host(struct dw_spi *dws);

#ifdef CONFIG_SPI_DW_DMA

extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
extern void dw_spi_dma_setup_generic(struct dw_spi *dws);

#else

static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}

#endif /* !CONFIG_SPI_DW_DMA */

#endif /* DW_SPI_HEADER_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
e24c7452 FT	2	#ifndef DW_SPI_HEADER_H
e24c7452 FT	3	#define DW_SPI_HEADER_H
7063c0d9	4
cc760f31	5	#include <linux/bits.h>
bdbdf0f0	6	#include <linux/completion.h>
8378449d	7	#include <linux/debugfs.h>
e62a15d9	8	#include <linux/irqreturn.h>
e24c7452	9	#include <linux/io.h>
46165a3d	10	#include <linux/scatterlist.h>
6423207e	11	#include <linux/spi/spi-mem.h>
e24c7452	12
7eb187b3	13	/* Register offsets */
299cb65c WAZ	14	#define DW_SPI_CTRLR0 0x00
299cb65c WAZ	15	#define DW_SPI_CTRLR1 0x04
7eb187b3 HS	16	#define DW_SPI_SSIENR 0x08
	17	#define DW_SPI_MWCR 0x0c
	18	#define DW_SPI_SER 0x10
	19	#define DW_SPI_BAUDR 0x14
299cb65c WAZ	20	#define DW_SPI_TXFTLR 0x18
299cb65c WAZ	21	#define DW_SPI_RXFTLR 0x1c
7eb187b3 HS	22	#define DW_SPI_TXFLR 0x20
	23	#define DW_SPI_RXFLR 0x24
	24	#define DW_SPI_SR 0x28
	25	#define DW_SPI_IMR 0x2c
	26	#define DW_SPI_ISR 0x30
	27	#define DW_SPI_RISR 0x34
	28	#define DW_SPI_TXOICR 0x38
	29	#define DW_SPI_RXOICR 0x3c
	30	#define DW_SPI_RXUICR 0x40
	31	#define DW_SPI_MSTICR 0x44
	32	#define DW_SPI_ICR 0x48
	33	#define DW_SPI_DMACR 0x4c
	34	#define DW_SPI_DMATDLR 0x50
	35	#define DW_SPI_DMARDLR 0x54
	36	#define DW_SPI_IDR 0x58
	37	#define DW_SPI_VERSION 0x5c
	38	#define DW_SPI_DR 0x60
bac70b54	39	#define DW_SPI_RX_SAMPLE_DLY 0xf0
f2d70479	40	#define DW_SPI_CS_OVERRIDE 0xf4
7eb187b3	41
e24c7452 FT	42	/* Bit fields in CTRLR0 */
	43	#define SPI_DFS_OFFSET 0
	44
	45	#define SPI_FRF_OFFSET 4
	46	#define SPI_FRF_SPI 0x0
	47	#define SPI_FRF_SSP 0x1
	48	#define SPI_FRF_MICROWIRE 0x2
	49	#define SPI_FRF_RESV 0x3
	50
	51	#define SPI_MODE_OFFSET 6
	52	#define SPI_SCPH_OFFSET 6
	53	#define SPI_SCOL_OFFSET 7
e3e55ff5	54
e24c7452	55	#define SPI_TMOD_OFFSET 8
e3e55ff5	56	#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
e24c7452 FT	57	#define SPI_TMOD_TR 0x0 /* xmit & recv */
	58	#define SPI_TMOD_TO 0x1 /* xmit only */
	59	#define SPI_TMOD_RO 0x2 /* recv only */
	60	#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
	61
	62	#define SPI_SLVOE_OFFSET 10
	63	#define SPI_SRL_OFFSET 11
	64	#define SPI_CFS_OFFSET 12
	65
e539f435 WAZ	66	/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
	67	#define DWC_SSI_CTRLR0_SRL_OFFSET 13
	68	#define DWC_SSI_CTRLR0_TMOD_OFFSET 10
	69	#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
	70	#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
	71	#define DWC_SSI_CTRLR0_SCPH_OFFSET 8
	72	#define DWC_SSI_CTRLR0_FRF_OFFSET 6
	73	#define DWC_SSI_CTRLR0_DFS_OFFSET 0
	74
ffb7ca54 SS	75	/*
	76	* For Keem Bay, CTRLR0[31] is used to select controller mode.
	77	* 0: SSI is slave
	78	* 1: SSI is master
	79	*/
	80	#define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31)
	81
6423207e SS	82	/* Bit fields in CTRLR1 */
	83	#define SPI_NDF_MASK GENMASK(15, 0)
	84
e24c7452 FT	85	/* Bit fields in SR, 7 bits */
	86	#define SR_MASK 0x7f /* cover 7 bits */
	87	#define SR_BUSY (1 << 0)
	88	#define SR_TF_NOT_FULL (1 << 1)
	89	#define SR_TF_EMPT (1 << 2)
	90	#define SR_RF_NOT_EMPT (1 << 3)
	91	#define SR_RF_FULL (1 << 4)
	92	#define SR_TX_ERR (1 << 5)
	93	#define SR_DCOL (1 << 6)
	94
	95	/* Bit fields in ISR, IMR, RISR, 7 bits */
	96	#define SPI_INT_TXEI (1 << 0)
	97	#define SPI_INT_TXOI (1 << 1)
	98	#define SPI_INT_RXUI (1 << 2)
	99	#define SPI_INT_RXOI (1 << 3)
	100	#define SPI_INT_RXFI (1 << 4)
	101	#define SPI_INT_MSTI (1 << 5)
	102
15ee3be7 AS	103	/* Bit fields in DMACR */
	104	#define SPI_DMA_RDMAE (1 << 0)
	105	#define SPI_DMA_TDMAE (1 << 1)
	106
cf75baea	107	#define SPI_WAIT_RETRIES 5
6423207e SS	108	#define SPI_BUF_SIZE \
	109	(sizeof_field(struct spi_mem_op, cmd.opcode) + \
	110	sizeof_field(struct spi_mem_op, addr.val) + 256)
	111	#define SPI_GET_BYTE(_val, _idx) \
	112	((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
cf75baea	113
e24c7452 FT	114	enum dw_ssi_type {
	115	SSI_MOTO_SPI = 0,
	116	SSI_TI_SSP,
	117	SSI_NS_MICROWIRE,
	118	};
	119
cc760f31 SS	120	/* DW SPI capabilities */
cc760f31 SS	121	#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
ffb7ca54	122	#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
d6bbd119	123	#define DW_SPI_CAP_DWC_SSI BIT(2)
cc760f31	124
3ff60c6b SS	125	/* Slave spi_transfer/spi_mem_op related */
	126	struct dw_spi_cfg {
	127	u8 tmode;
	128	u8 dfs;
	129	u32 ndf;
	130	u32 freq;
	131	};
	132
7063c0d9 FT	133	struct dw_spi;
7063c0d9 FT	134	struct dw_spi_dma_ops {
6370abab	135	int (dma_init)(struct device dev, struct dw_spi *dws);
7063c0d9	136	void (dma_exit)(struct dw_spi dws);
f89a6d8f	137	int (dma_setup)(struct dw_spi dws, struct spi_transfer *xfer);
721483e2	138	bool (can_dma)(struct spi_controller master, struct spi_device *spi,
f89a6d8f AS	139	struct spi_transfer *xfer);
f89a6d8f AS	140	int (dma_transfer)(struct dw_spi dws, struct spi_transfer *xfer);
4d5ac1ed	141	void (dma_stop)(struct dw_spi dws);
7063c0d9 FT	142	};
7063c0d9 FT	143
e24c7452	144	struct dw_spi {
721483e2	145	struct spi_controller *master;
e24c7452 FT	146
	147	void __iomem *regs;
	148	unsigned long paddr;
e24c7452	149	int irq;
552e4509	150	u32 fifo_len; /* depth of the FIFO buffer */
e24c7452 FT	151	u32 max_freq; /* max bus freq supported */
e24c7452 FT	152
cc760f31 SS	153	u32 caps; /* DW SPI capabilities */
cc760f31 SS	154
c4fe57f7	155	u32 reg_io_width; /* DR I/O width in bytes */
e24c7452 FT	156	u16 bus_num;
e24c7452 FT	157	u16 num_cs; /* supported slave numbers */
62dbbae4	158	void (set_cs)(struct spi_device spi, bool enable);
e24c7452	159
e24c7452	160	/* Current message transfer state info */
e24c7452	161	void *tx;
8dedbeac	162	unsigned int tx_len;
e24c7452	163	void *rx;
8dedbeac	164	unsigned int rx_len;
6423207e	165	u8 buf[SPI_BUF_SIZE];
e24c7452	166	int dma_mapped;
e24c7452	167	u8 n_bytes; /* current is a 1/2 bytes op */
e24c7452	168	irqreturn_t (transfer_handler)(struct dw_spi dws);
13b10301	169	u32 current_freq; /* frequency in hz */
bac70b54 LP	170	u32 cur_rx_sample_dly;
bac70b54 LP	171	u32 def_rx_sample_dly_ns;
e24c7452	172
6423207e SS	173	/* Custom memory operations */
	174	struct spi_controller_mem_ops mem_ops;
	175
f89a6d8f	176	/* DMA info */
e24c7452	177	struct dma_chan *txchan;
0b2b6651	178	u32 txburst;
e24c7452	179	struct dma_chan *rxchan;
0b2b6651	180	u32 rxburst;
ad4fe126	181	u32 dma_sg_burst;
30c8eb52	182	unsigned long dma_chan_busy;
7063c0d9	183	dma_addr_t dma_addr; /* phy address of the Data register */
4fe338c9	184	const struct dw_spi_dma_ops *dma_ops;
bdbdf0f0	185	struct completion dma_completion;
e24c7452	186
e24c7452 FT	187	#ifdef CONFIG_DEBUG_FS
e24c7452 FT	188	struct dentry *debugfs;
8378449d	189	struct debugfs_regset32 regset;
e24c7452 FT	190	#endif
	191	};
	192
7eb187b3 HS	193	static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
	194	{
	195	return __raw_readl(dws->regs + offset);
	196	}
	197
	198	static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
	199	{
	200	__raw_writel(val, dws->regs + offset);
	201	}
	202
c4fe57f7 MW	203	static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
	204	{
	205	switch (dws->reg_io_width) {
	206	case 2:
7e31cea7	207	return readw_relaxed(dws->regs + offset);
c4fe57f7 MW	208	case 4:
c4fe57f7 MW	209	default:
7e31cea7	210	return readl_relaxed(dws->regs + offset);
c4fe57f7 MW	211	}
	212	}
	213
	214	static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
	215	{
	216	switch (dws->reg_io_width) {
	217	case 2:
7e31cea7	218	writew_relaxed(val, dws->regs + offset);
c4fe57f7 MW	219	break;
	220	case 4:
	221	default:
7e31cea7	222	writel_relaxed(val, dws->regs + offset);
c4fe57f7 MW	223	break;
	224	}
	225	}
	226
e24c7452 FT	227	static inline void spi_enable_chip(struct dw_spi *dws, int enable)
e24c7452 FT	228	{
7eb187b3	229	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
e24c7452 FT	230	}
	231
	232	static inline void spi_set_clk(struct dw_spi *dws, u16 div)
	233	{
7eb187b3	234	dw_writel(dws, DW_SPI_BAUDR, div);
e24c7452 FT	235	}
e24c7452 FT	236
e24c7452 FT	237	/* Disable IRQ bits */
	238	static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
	239	{
	240	u32 new_mask;
	241
7eb187b3 HS	242	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
7eb187b3 HS	243	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	244	}
	245
	246	/* Enable IRQ bits */
	247	static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
	248	{
	249	u32 new_mask;
	250
7eb187b3 HS	251	new_mask = dw_readl(dws, DW_SPI_IMR) \| mask;
7eb187b3 HS	252	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	253	}
e24c7452 FT	254
45746e82	255	/*
fbddc989 SS	256	* This disables the SPI controller, interrupts, clears the interrupts status
	257	* and CS, then re-enables the controller back. Transmit and receive FIFO
	258	* buffers are cleared when the device is disabled.
45746e82 AS	259	*/
	260	static inline void spi_reset_chip(struct dw_spi *dws)
	261	{
	262	spi_enable_chip(dws, 0);
	263	spi_mask_intr(dws, 0xff);
a128f6ec	264	dw_readl(dws, DW_SPI_ICR);
fbddc989	265	dw_writel(dws, DW_SPI_SER, 0);
45746e82 AS	266	spi_enable_chip(dws, 1);
	267	}
	268
1cc3f141 AS	269	static inline void spi_shutdown_chip(struct dw_spi *dws)
	270	{
	271	spi_enable_chip(dws, 0);
	272	spi_set_clk(dws, 0);
	273	}
	274
c79bdbb4	275	extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
3ff60c6b SS	276	extern void dw_spi_update_config(struct dw_spi dws, struct spi_device spi,
3ff60c6b SS	277	struct dw_spi_cfg *cfg);
bf64b660	278	extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
04f421e7	279	extern int dw_spi_add_host(struct device dev, struct dw_spi dws);
e24c7452 FT	280	extern void dw_spi_remove_host(struct dw_spi *dws);
	281	extern int dw_spi_suspend_host(struct dw_spi *dws);
	282	extern int dw_spi_resume_host(struct dw_spi *dws);
7063c0d9	283
6c710c0c SS	284	#ifdef CONFIG_SPI_DW_DMA
6c710c0c SS	285
57784411 SS	286	extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
57784411 SS	287	extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
6c710c0c SS	288
	289	#else
	290
57784411 SS	291	static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
57784411 SS	292	static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
6c710c0c SS	293
6c710c0c SS	294	#endif /* !CONFIG_SPI_DW_DMA */
37aa8aa6	295
e24c7452	296	#endif /* DW_SPI_HEADER_H */