[linux-2.6-block.git] / drivers / spi / spi-dw.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DW_SPI_HEADER_H
#define DW_SPI_HEADER_H

#include <linux/bits.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/irqreturn.h>
#include <linux/io.h>
#include <linux/scatterlist.h>

/* Register offsets */
#define DW_SPI_CTRLR0			0x00
#define DW_SPI_CTRLR1			0x04
#define DW_SPI_SSIENR			0x08
#define DW_SPI_MWCR			0x0c
#define DW_SPI_SER			0x10
#define DW_SPI_BAUDR			0x14
#define DW_SPI_TXFTLR			0x18
#define DW_SPI_RXFTLR			0x1c
#define DW_SPI_TXFLR			0x20
#define DW_SPI_RXFLR			0x24
#define DW_SPI_SR			0x28
#define DW_SPI_IMR			0x2c
#define DW_SPI_ISR			0x30
#define DW_SPI_RISR			0x34
#define DW_SPI_TXOICR			0x38
#define DW_SPI_RXOICR			0x3c
#define DW_SPI_RXUICR			0x40
#define DW_SPI_MSTICR			0x44
#define DW_SPI_ICR			0x48
#define DW_SPI_DMACR			0x4c
#define DW_SPI_DMATDLR			0x50
#define DW_SPI_DMARDLR			0x54
#define DW_SPI_IDR			0x58
#define DW_SPI_VERSION			0x5c
#define DW_SPI_DR			0x60
#define DW_SPI_RX_SAMPLE_DLY		0xf0
#define DW_SPI_CS_OVERRIDE		0xf4

/* Bit fields in CTRLR0 */
#define SPI_DFS_OFFSET			0

#define SPI_FRF_OFFSET			4
#define SPI_FRF_SPI			0x0
#define SPI_FRF_SSP			0x1
#define SPI_FRF_MICROWIRE		0x2
#define SPI_FRF_RESV			0x3

#define SPI_MODE_OFFSET			6
#define SPI_SCPH_OFFSET			6
#define SPI_SCOL_OFFSET			7

#define SPI_TMOD_OFFSET			8
#define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
#define	SPI_TMOD_TR			0x0		/* xmit & recv */
#define SPI_TMOD_TO			0x1		/* xmit only */
#define SPI_TMOD_RO			0x2		/* recv only */
#define SPI_TMOD_EPROMREAD		0x3		/* eeprom read mode */

#define SPI_SLVOE_OFFSET		10
#define SPI_SRL_OFFSET			11
#define SPI_CFS_OFFSET			12

/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
#define DWC_SSI_CTRLR0_SRL_OFFSET	13
#define DWC_SSI_CTRLR0_TMOD_OFFSET	10
#define DWC_SSI_CTRLR0_TMOD_MASK	GENMASK(11, 10)
#define DWC_SSI_CTRLR0_SCPOL_OFFSET	9
#define DWC_SSI_CTRLR0_SCPH_OFFSET	8
#define DWC_SSI_CTRLR0_FRF_OFFSET	6
#define DWC_SSI_CTRLR0_DFS_OFFSET	0

/*
 * For Keem Bay, CTRLR0[31] is used to select controller mode.
 * 0: SSI is slave
 * 1: SSI is master
 */
#define DWC_SSI_CTRLR0_KEEMBAY_MST	BIT(31)

/* Bit fields in SR, 7 bits */
#define SR_MASK				0x7f		/* cover 7 bits */
#define SR_BUSY				(1 << 0)
#define SR_TF_NOT_FULL			(1 << 1)
#define SR_TF_EMPT			(1 << 2)
#define SR_RF_NOT_EMPT			(1 << 3)
#define SR_RF_FULL			(1 << 4)
#define SR_TX_ERR			(1 << 5)
#define SR_DCOL				(1 << 6)

/* Bit fields in ISR, IMR, RISR, 7 bits */
#define SPI_INT_TXEI			(1 << 0)
#define SPI_INT_TXOI			(1 << 1)
#define SPI_INT_RXUI			(1 << 2)
#define SPI_INT_RXOI			(1 << 3)
#define SPI_INT_RXFI			(1 << 4)
#define SPI_INT_MSTI			(1 << 5)

/* Bit fields in DMACR */
#define SPI_DMA_RDMAE			(1 << 0)
#define SPI_DMA_TDMAE			(1 << 1)

enum dw_ssi_type {
	SSI_MOTO_SPI = 0,
	SSI_TI_SSP,
	SSI_NS_MICROWIRE,
};

/* DW SPI capabilities */
#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
#define DW_SPI_CAP_KEEMBAY_MST		BIT(1)
#define DW_SPI_CAP_DWC_SSI		BIT(2)

struct dw_spi;
struct dw_spi_dma_ops {
	int (*dma_init)(struct device *dev, struct dw_spi *dws);
	void (*dma_exit)(struct dw_spi *dws);
	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
	bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
			struct spi_transfer *xfer);
	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
	void (*dma_stop)(struct dw_spi *dws);
};

struct dw_spi {
	struct spi_controller	*master;

	void __iomem		*regs;
	unsigned long		paddr;
	int			irq;
	u32			fifo_len;	/* depth of the FIFO buffer */
	u32			max_freq;	/* max bus freq supported */

	u32			caps;		/* DW SPI capabilities */

	u32			reg_io_width;	/* DR I/O width in bytes */
	u16			bus_num;
	u16			num_cs;		/* supported slave numbers */
	void (*set_cs)(struct spi_device *spi, bool enable);

	/* Current message transfer state info */
	size_t			len;
	void			*tx;
	void			*tx_end;
	void			*rx;
	void			*rx_end;
	int			dma_mapped;
	u8			n_bytes;	/* current is a 1/2 bytes op */
	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
	u32			current_freq;	/* frequency in hz */
	u32			cur_rx_sample_dly;
	u32			def_rx_sample_dly_ns;

	/* DMA info */
	struct dma_chan		*txchan;
	u32			txburst;
	struct dma_chan		*rxchan;
	u32			rxburst;
	u32			dma_sg_burst;
	unsigned long		dma_chan_busy;
	dma_addr_t		dma_addr; /* phy address of the Data register */
	const struct dw_spi_dma_ops *dma_ops;
	struct completion	dma_completion;

#ifdef CONFIG_DEBUG_FS
	struct dentry *debugfs;
	struct debugfs_regset32 regset;
#endif
};

static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
{
	return __raw_readl(dws->regs + offset);
}

static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
	__raw_writel(val, dws->regs + offset);
}

static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
{
	switch (dws->reg_io_width) {
	case 2:
		return readw_relaxed(dws->regs + offset);
	case 4:
	default:
		return readl_relaxed(dws->regs + offset);
	}
}

static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
{
	switch (dws->reg_io_width) {
	case 2:
		writew_relaxed(val, dws->regs + offset);
		break;
	case 4:
	default:
		writel_relaxed(val, dws->regs + offset);
		break;
	}
}

static inline void spi_enable_chip(struct dw_spi *dws, int enable)
{
	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
}

static inline void spi_set_clk(struct dw_spi *dws, u16 div)
{
	dw_writel(dws, DW_SPI_BAUDR, div);
}

/* Disable IRQ bits */
static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/* Enable IRQ bits */
static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/*
 * This disables the SPI controller, interrupts, clears the interrupts status,
 * and re-enable the controller back. Transmit and receive FIFO buffers are
 * cleared when the device is disabled.
 */
static inline void spi_reset_chip(struct dw_spi *dws)
{
	spi_enable_chip(dws, 0);
	spi_mask_intr(dws, 0xff);
	dw_readl(dws, DW_SPI_ICR);
	spi_enable_chip(dws, 1);
}

static inline void spi_shutdown_chip(struct dw_spi *dws)
{
	spi_enable_chip(dws, 0);
	spi_set_clk(dws, 0);
}

extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
extern void dw_spi_remove_host(struct dw_spi *dws);
extern int dw_spi_suspend_host(struct dw_spi *dws);
extern int dw_spi_resume_host(struct dw_spi *dws);

#ifdef CONFIG_SPI_DW_DMA

extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
extern void dw_spi_dma_setup_generic(struct dw_spi *dws);

#else

static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}

#endif /* !CONFIG_SPI_DW_DMA */

#endif /* DW_SPI_HEADER_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
e24c7452 FT	2	#ifndef DW_SPI_HEADER_H
e24c7452 FT	3	#define DW_SPI_HEADER_H
7063c0d9	4
cc760f31	5	#include <linux/bits.h>
bdbdf0f0	6	#include <linux/completion.h>
8378449d	7	#include <linux/debugfs.h>
e62a15d9	8	#include <linux/irqreturn.h>
e24c7452	9	#include <linux/io.h>
46165a3d	10	#include <linux/scatterlist.h>
e24c7452	11
7eb187b3	12	/* Register offsets */
299cb65c WAZ	13	#define DW_SPI_CTRLR0 0x00
299cb65c WAZ	14	#define DW_SPI_CTRLR1 0x04
7eb187b3 HS	15	#define DW_SPI_SSIENR 0x08
	16	#define DW_SPI_MWCR 0x0c
	17	#define DW_SPI_SER 0x10
	18	#define DW_SPI_BAUDR 0x14
299cb65c WAZ	19	#define DW_SPI_TXFTLR 0x18
299cb65c WAZ	20	#define DW_SPI_RXFTLR 0x1c
7eb187b3 HS	21	#define DW_SPI_TXFLR 0x20
	22	#define DW_SPI_RXFLR 0x24
	23	#define DW_SPI_SR 0x28
	24	#define DW_SPI_IMR 0x2c
	25	#define DW_SPI_ISR 0x30
	26	#define DW_SPI_RISR 0x34
	27	#define DW_SPI_TXOICR 0x38
	28	#define DW_SPI_RXOICR 0x3c
	29	#define DW_SPI_RXUICR 0x40
	30	#define DW_SPI_MSTICR 0x44
	31	#define DW_SPI_ICR 0x48
	32	#define DW_SPI_DMACR 0x4c
	33	#define DW_SPI_DMATDLR 0x50
	34	#define DW_SPI_DMARDLR 0x54
	35	#define DW_SPI_IDR 0x58
	36	#define DW_SPI_VERSION 0x5c
	37	#define DW_SPI_DR 0x60
bac70b54	38	#define DW_SPI_RX_SAMPLE_DLY 0xf0
f2d70479	39	#define DW_SPI_CS_OVERRIDE 0xf4
7eb187b3	40
e24c7452 FT	41	/* Bit fields in CTRLR0 */
	42	#define SPI_DFS_OFFSET 0
	43
	44	#define SPI_FRF_OFFSET 4
	45	#define SPI_FRF_SPI 0x0
	46	#define SPI_FRF_SSP 0x1
	47	#define SPI_FRF_MICROWIRE 0x2
	48	#define SPI_FRF_RESV 0x3
	49
	50	#define SPI_MODE_OFFSET 6
	51	#define SPI_SCPH_OFFSET 6
	52	#define SPI_SCOL_OFFSET 7
e3e55ff5	53
e24c7452	54	#define SPI_TMOD_OFFSET 8
e3e55ff5	55	#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
e24c7452 FT	56	#define SPI_TMOD_TR 0x0 /* xmit & recv */
	57	#define SPI_TMOD_TO 0x1 /* xmit only */
	58	#define SPI_TMOD_RO 0x2 /* recv only */
	59	#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
	60
	61	#define SPI_SLVOE_OFFSET 10
	62	#define SPI_SRL_OFFSET 11
	63	#define SPI_CFS_OFFSET 12
	64
e539f435 WAZ	65	/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
	66	#define DWC_SSI_CTRLR0_SRL_OFFSET 13
	67	#define DWC_SSI_CTRLR0_TMOD_OFFSET 10
	68	#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
	69	#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
	70	#define DWC_SSI_CTRLR0_SCPH_OFFSET 8
	71	#define DWC_SSI_CTRLR0_FRF_OFFSET 6
	72	#define DWC_SSI_CTRLR0_DFS_OFFSET 0
	73
ffb7ca54 SS	74	/*
	75	* For Keem Bay, CTRLR0[31] is used to select controller mode.
	76	* 0: SSI is slave
	77	* 1: SSI is master
	78	*/
	79	#define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31)
	80
e24c7452 FT	81	/* Bit fields in SR, 7 bits */
	82	#define SR_MASK 0x7f /* cover 7 bits */
	83	#define SR_BUSY (1 << 0)
	84	#define SR_TF_NOT_FULL (1 << 1)
	85	#define SR_TF_EMPT (1 << 2)
	86	#define SR_RF_NOT_EMPT (1 << 3)
	87	#define SR_RF_FULL (1 << 4)
	88	#define SR_TX_ERR (1 << 5)
	89	#define SR_DCOL (1 << 6)
	90
	91	/* Bit fields in ISR, IMR, RISR, 7 bits */
	92	#define SPI_INT_TXEI (1 << 0)
	93	#define SPI_INT_TXOI (1 << 1)
	94	#define SPI_INT_RXUI (1 << 2)
	95	#define SPI_INT_RXOI (1 << 3)
	96	#define SPI_INT_RXFI (1 << 4)
	97	#define SPI_INT_MSTI (1 << 5)
	98
15ee3be7 AS	99	/* Bit fields in DMACR */
	100	#define SPI_DMA_RDMAE (1 << 0)
	101	#define SPI_DMA_TDMAE (1 << 1)
	102
e24c7452 FT	103	enum dw_ssi_type {
	104	SSI_MOTO_SPI = 0,
	105	SSI_TI_SSP,
	106	SSI_NS_MICROWIRE,
	107	};
	108
cc760f31 SS	109	/* DW SPI capabilities */
cc760f31 SS	110	#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
ffb7ca54	111	#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
d6bbd119	112	#define DW_SPI_CAP_DWC_SSI BIT(2)
cc760f31	113
7063c0d9 FT	114	struct dw_spi;
7063c0d9 FT	115	struct dw_spi_dma_ops {
6370abab	116	int (dma_init)(struct device dev, struct dw_spi *dws);
7063c0d9	117	void (dma_exit)(struct dw_spi dws);
f89a6d8f	118	int (dma_setup)(struct dw_spi dws, struct spi_transfer *xfer);
721483e2	119	bool (can_dma)(struct spi_controller master, struct spi_device *spi,
f89a6d8f AS	120	struct spi_transfer *xfer);
f89a6d8f AS	121	int (dma_transfer)(struct dw_spi dws, struct spi_transfer *xfer);
4d5ac1ed	122	void (dma_stop)(struct dw_spi dws);
7063c0d9 FT	123	};
7063c0d9 FT	124
e24c7452	125	struct dw_spi {
721483e2	126	struct spi_controller *master;
e24c7452 FT	127
	128	void __iomem *regs;
	129	unsigned long paddr;
e24c7452	130	int irq;
552e4509	131	u32 fifo_len; /* depth of the FIFO buffer */
e24c7452 FT	132	u32 max_freq; /* max bus freq supported */
e24c7452 FT	133
cc760f31 SS	134	u32 caps; /* DW SPI capabilities */
cc760f31 SS	135
c4fe57f7	136	u32 reg_io_width; /* DR I/O width in bytes */
e24c7452 FT	137	u16 bus_num;
e24c7452 FT	138	u16 num_cs; /* supported slave numbers */
62dbbae4	139	void (set_cs)(struct spi_device spi, bool enable);
e24c7452	140
e24c7452	141	/* Current message transfer state info */
e24c7452 FT	142	size_t len;
	143	void *tx;
	144	void *tx_end;
	145	void *rx;
	146	void *rx_end;
	147	int dma_mapped;
e24c7452	148	u8 n_bytes; /* current is a 1/2 bytes op */
e24c7452	149	irqreturn_t (transfer_handler)(struct dw_spi dws);
13b10301	150	u32 current_freq; /* frequency in hz */
bac70b54 LP	151	u32 cur_rx_sample_dly;
bac70b54 LP	152	u32 def_rx_sample_dly_ns;
e24c7452	153
f89a6d8f	154	/* DMA info */
e24c7452	155	struct dma_chan *txchan;
0b2b6651	156	u32 txburst;
e24c7452	157	struct dma_chan *rxchan;
0b2b6651	158	u32 rxburst;
ad4fe126	159	u32 dma_sg_burst;
30c8eb52	160	unsigned long dma_chan_busy;
7063c0d9	161	dma_addr_t dma_addr; /* phy address of the Data register */
4fe338c9	162	const struct dw_spi_dma_ops *dma_ops;
bdbdf0f0	163	struct completion dma_completion;
e24c7452	164
e24c7452 FT	165	#ifdef CONFIG_DEBUG_FS
e24c7452 FT	166	struct dentry *debugfs;
8378449d	167	struct debugfs_regset32 regset;
e24c7452 FT	168	#endif
	169	};
	170
7eb187b3 HS	171	static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
	172	{
	173	return __raw_readl(dws->regs + offset);
	174	}
	175
	176	static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
	177	{
	178	__raw_writel(val, dws->regs + offset);
	179	}
	180
c4fe57f7 MW	181	static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
	182	{
	183	switch (dws->reg_io_width) {
	184	case 2:
7e31cea7	185	return readw_relaxed(dws->regs + offset);
c4fe57f7 MW	186	case 4:
c4fe57f7 MW	187	default:
7e31cea7	188	return readl_relaxed(dws->regs + offset);
c4fe57f7 MW	189	}
	190	}
	191
	192	static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
	193	{
	194	switch (dws->reg_io_width) {
	195	case 2:
7e31cea7	196	writew_relaxed(val, dws->regs + offset);
c4fe57f7 MW	197	break;
	198	case 4:
	199	default:
7e31cea7	200	writel_relaxed(val, dws->regs + offset);
c4fe57f7 MW	201	break;
	202	}
	203	}
	204
e24c7452 FT	205	static inline void spi_enable_chip(struct dw_spi *dws, int enable)
e24c7452 FT	206	{
7eb187b3	207	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
e24c7452 FT	208	}
	209
	210	static inline void spi_set_clk(struct dw_spi *dws, u16 div)
	211	{
7eb187b3	212	dw_writel(dws, DW_SPI_BAUDR, div);
e24c7452 FT	213	}
e24c7452 FT	214
e24c7452 FT	215	/* Disable IRQ bits */
	216	static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
	217	{
	218	u32 new_mask;
	219
7eb187b3 HS	220	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
7eb187b3 HS	221	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	222	}
	223
	224	/* Enable IRQ bits */
	225	static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
	226	{
	227	u32 new_mask;
	228
7eb187b3 HS	229	new_mask = dw_readl(dws, DW_SPI_IMR) \| mask;
7eb187b3 HS	230	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	231	}
e24c7452 FT	232
45746e82	233	/*
a128f6ec SS	234	* This disables the SPI controller, interrupts, clears the interrupts status,
	235	* and re-enable the controller back. Transmit and receive FIFO buffers are
	236	* cleared when the device is disabled.
45746e82 AS	237	*/
	238	static inline void spi_reset_chip(struct dw_spi *dws)
	239	{
	240	spi_enable_chip(dws, 0);
	241	spi_mask_intr(dws, 0xff);
a128f6ec	242	dw_readl(dws, DW_SPI_ICR);
45746e82 AS	243	spi_enable_chip(dws, 1);
	244	}
	245
1cc3f141 AS	246	static inline void spi_shutdown_chip(struct dw_spi *dws)
	247	{
	248	spi_enable_chip(dws, 0);
	249	spi_set_clk(dws, 0);
	250	}
	251
c79bdbb4	252	extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
04f421e7	253	extern int dw_spi_add_host(struct device dev, struct dw_spi dws);
e24c7452 FT	254	extern void dw_spi_remove_host(struct dw_spi *dws);
	255	extern int dw_spi_suspend_host(struct dw_spi *dws);
	256	extern int dw_spi_resume_host(struct dw_spi *dws);
7063c0d9	257
6c710c0c SS	258	#ifdef CONFIG_SPI_DW_DMA
6c710c0c SS	259
57784411 SS	260	extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
57784411 SS	261	extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
6c710c0c SS	262
	263	#else
	264
57784411 SS	265	static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
57784411 SS	266	static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
6c710c0c SS	267
6c710c0c SS	268	#endif /* !CONFIG_SPI_DW_DMA */
37aa8aa6	269
e24c7452	270	#endif /* DW_SPI_HEADER_H */