[linux-2.6-block.git] / drivers / spi / spi-dw.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SPI_DW_H__
#define __SPI_DW_H__

#include <linux/bits.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/irqreturn.h>
#include <linux/io.h>
#include <linux/scatterlist.h>
#include <linux/spi/spi-mem.h>
#include <linux/bitfield.h>

/* Synopsys DW SSI IP-core virtual IDs */
#define DW_PSSI_ID			0
#define DW_HSSI_ID			1

/* Synopsys DW SSI component versions (FourCC sequence) */
#define DW_HSSI_102A			0x3130322a

/* DW SSI IP-core ID and version check helpers */
#define dw_spi_ip_is(_dws, _ip) \
	((_dws)->ip == DW_ ## _ip ## _ID)

#define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
	(dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)

#define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)

#define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=)

/* DW SPI controller capabilities */
#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
#define DW_SPI_CAP_DFS32		BIT(1)

/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
#define DW_SPI_CTRLR0			0x00
#define DW_SPI_CTRLR1			0x04
#define DW_SPI_SSIENR			0x08
#define DW_SPI_MWCR			0x0c
#define DW_SPI_SER			0x10
#define DW_SPI_BAUDR			0x14
#define DW_SPI_TXFTLR			0x18
#define DW_SPI_RXFTLR			0x1c
#define DW_SPI_TXFLR			0x20
#define DW_SPI_RXFLR			0x24
#define DW_SPI_SR			0x28
#define DW_SPI_IMR			0x2c
#define DW_SPI_ISR			0x30
#define DW_SPI_RISR			0x34
#define DW_SPI_TXOICR			0x38
#define DW_SPI_RXOICR			0x3c
#define DW_SPI_RXUICR			0x40
#define DW_SPI_MSTICR			0x44
#define DW_SPI_ICR			0x48
#define DW_SPI_DMACR			0x4c
#define DW_SPI_DMATDLR			0x50
#define DW_SPI_DMARDLR			0x54
#define DW_SPI_IDR			0x58
#define DW_SPI_VERSION			0x5c
#define DW_SPI_DR			0x60
#define DW_SPI_RX_SAMPLE_DLY		0xf0
#define DW_SPI_CS_OVERRIDE		0xf4

/* Bit fields in CTRLR0 (DWC APB SSI) */
#define DW_PSSI_CTRLR0_DFS_MASK			GENMASK(3, 0)
#define DW_PSSI_CTRLR0_DFS32_MASK		GENMASK(20, 16)

#define DW_PSSI_CTRLR0_FRF_MASK			GENMASK(5, 4)
#define DW_SPI_CTRLR0_FRF_MOTO_SPI		0x0
#define DW_SPI_CTRLR0_FRF_TI_SSP		0x1
#define DW_SPI_CTRLR0_FRF_NS_MICROWIRE		0x2
#define DW_SPI_CTRLR0_FRF_RESV			0x3

#define DW_PSSI_CTRLR0_MODE_MASK		GENMASK(7, 6)
#define DW_PSSI_CTRLR0_SCPHA			BIT(6)
#define DW_PSSI_CTRLR0_SCPOL			BIT(7)

#define DW_PSSI_CTRLR0_TMOD_MASK		GENMASK(9, 8)
#define DW_SPI_CTRLR0_TMOD_TR			0x0	/* xmit & recv */
#define DW_SPI_CTRLR0_TMOD_TO			0x1	/* xmit only */
#define DW_SPI_CTRLR0_TMOD_RO			0x2	/* recv only */
#define DW_SPI_CTRLR0_TMOD_EPROMREAD		0x3	/* eeprom read mode */

#define DW_PSSI_CTRLR0_SLV_OE			BIT(10)
#define DW_PSSI_CTRLR0_SRL			BIT(11)
#define DW_PSSI_CTRLR0_CFS			BIT(12)

/* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
#define DW_HSSI_CTRLR0_DFS_MASK			GENMASK(4, 0)
#define DW_HSSI_CTRLR0_FRF_MASK			GENMASK(7, 6)
#define DW_HSSI_CTRLR0_SCPHA			BIT(8)
#define DW_HSSI_CTRLR0_SCPOL			BIT(9)
#define DW_HSSI_CTRLR0_TMOD_MASK		GENMASK(11, 10)
#define DW_HSSI_CTRLR0_SRL			BIT(13)
#define DW_HSSI_CTRLR0_MST			BIT(31)

/* Bit fields in CTRLR1 */
#define DW_SPI_NDF_MASK				GENMASK(15, 0)

/* Bit fields in SR, 7 bits */
#define DW_SPI_SR_MASK				GENMASK(6, 0)
#define DW_SPI_SR_BUSY				BIT(0)
#define DW_SPI_SR_TF_NOT_FULL			BIT(1)
#define DW_SPI_SR_TF_EMPT			BIT(2)
#define DW_SPI_SR_RF_NOT_EMPT			BIT(3)
#define DW_SPI_SR_RF_FULL			BIT(4)
#define DW_SPI_SR_TX_ERR			BIT(5)
#define DW_SPI_SR_DCOL				BIT(6)

/* Bit fields in ISR, IMR, RISR, 7 bits */
#define DW_SPI_INT_MASK				GENMASK(5, 0)
#define DW_SPI_INT_TXEI				BIT(0)
#define DW_SPI_INT_TXOI				BIT(1)
#define DW_SPI_INT_RXUI				BIT(2)
#define DW_SPI_INT_RXOI				BIT(3)
#define DW_SPI_INT_RXFI				BIT(4)
#define DW_SPI_INT_MSTI				BIT(5)

/* Bit fields in DMACR */
#define DW_SPI_DMACR_RDMAE			BIT(0)
#define DW_SPI_DMACR_TDMAE			BIT(1)

/* Mem/DMA operations helpers */
#define DW_SPI_WAIT_RETRIES			5
#define DW_SPI_BUF_SIZE \
	(sizeof_field(struct spi_mem_op, cmd.opcode) + \
	 sizeof_field(struct spi_mem_op, addr.val) + 256)
#define DW_SPI_GET_BYTE(_val, _idx) \
	((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)

/* Slave spi_transfer/spi_mem_op related */
struct dw_spi_cfg {
	u8 tmode;
	u8 dfs;
	u32 ndf;
	u32 freq;
};

struct dw_spi;
struct dw_spi_dma_ops {
	int (*dma_init)(struct device *dev, struct dw_spi *dws);
	void (*dma_exit)(struct dw_spi *dws);
	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
	bool (*can_dma)(struct spi_controller *host, struct spi_device *spi,
			struct spi_transfer *xfer);
	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
	void (*dma_stop)(struct dw_spi *dws);
};

struct dw_spi {
	struct spi_controller	*host;

	u32			ip;		/* Synopsys DW SSI IP-core ID */
	u32			ver;		/* Synopsys component version */
	u32			caps;		/* DW SPI capabilities */

	void __iomem		*regs;
	unsigned long		paddr;
	int			irq;
	u32			fifo_len;	/* depth of the FIFO buffer */
	unsigned int		dfs_offset;     /* CTRLR0 DFS field offset */
	u32			max_mem_freq;	/* max mem-ops bus freq */
	u32			max_freq;	/* max bus freq supported */

	u32			reg_io_width;	/* DR I/O width in bytes */
	u16			bus_num;
	u16			num_cs;		/* supported slave numbers */
	void (*set_cs)(struct spi_device *spi, bool enable);

	/* Current message transfer state info */
	void			*tx;
	unsigned int		tx_len;
	void			*rx;
	unsigned int		rx_len;
	u8			buf[DW_SPI_BUF_SIZE];
	int			dma_mapped;
	u8			n_bytes;	/* current is a 1/2 bytes op */
	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
	u32			current_freq;	/* frequency in hz */
	u32			cur_rx_sample_dly;
	u32			def_rx_sample_dly_ns;

	/* Custom memory operations */
	struct spi_controller_mem_ops mem_ops;

	/* DMA info */
	struct dma_chan		*txchan;
	u32			txburst;
	struct dma_chan		*rxchan;
	u32			rxburst;
	u32			dma_sg_burst;
	u32			dma_addr_widths;
	unsigned long		dma_chan_busy;
	dma_addr_t		dma_addr; /* phy address of the Data register */
	const struct dw_spi_dma_ops *dma_ops;
	struct completion	dma_completion;

#ifdef CONFIG_DEBUG_FS
	struct dentry *debugfs;
	struct debugfs_regset32 regset;
#endif
};

static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
{
	return __raw_readl(dws->regs + offset);
}

static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
	__raw_writel(val, dws->regs + offset);
}

static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
{
	switch (dws->reg_io_width) {
	case 2:
		return readw_relaxed(dws->regs + offset);
	case 4:
	default:
		return readl_relaxed(dws->regs + offset);
	}
}

static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
{
	switch (dws->reg_io_width) {
	case 2:
		writew_relaxed(val, dws->regs + offset);
		break;
	case 4:
	default:
		writel_relaxed(val, dws->regs + offset);
		break;
	}
}

static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
{
	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
}

static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
{
	dw_writel(dws, DW_SPI_BAUDR, div);
}

/* Disable IRQ bits */
static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/* Enable IRQ bits */
static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
{
	u32 new_mask;

	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
	dw_writel(dws, DW_SPI_IMR, new_mask);
}

/*
 * This disables the SPI controller, interrupts, clears the interrupts status
 * and CS, then re-enables the controller back. Transmit and receive FIFO
 * buffers are cleared when the device is disabled.
 */
static inline void dw_spi_reset_chip(struct dw_spi *dws)
{
	dw_spi_enable_chip(dws, 0);
	dw_spi_mask_intr(dws, 0xff);
	dw_readl(dws, DW_SPI_ICR);
	dw_writel(dws, DW_SPI_SER, 0);
	dw_spi_enable_chip(dws, 1);
}

static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
{
	dw_spi_enable_chip(dws, 0);
	dw_spi_set_clk(dws, 0);
}

extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
				 struct dw_spi_cfg *cfg);
extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
extern void dw_spi_remove_host(struct dw_spi *dws);
extern int dw_spi_suspend_host(struct dw_spi *dws);
extern int dw_spi_resume_host(struct dw_spi *dws);

#ifdef CONFIG_SPI_DW_DMA

extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
extern void dw_spi_dma_setup_generic(struct dw_spi *dws);

#else

static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}

#endif /* !CONFIG_SPI_DW_DMA */

#endif /* __SPI_DW_H__ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
725b0e3e SS	2	#ifndef __SPI_DW_H__
725b0e3e SS	3	#define __SPI_DW_H__
7063c0d9	4
cc760f31	5	#include <linux/bits.h>
bdbdf0f0	6	#include <linux/completion.h>
8378449d	7	#include <linux/debugfs.h>
e62a15d9	8	#include <linux/irqreturn.h>
e24c7452	9	#include <linux/io.h>
46165a3d	10	#include <linux/scatterlist.h>
6423207e	11	#include <linux/spi/spi-mem.h>
a51acc24	12	#include <linux/bitfield.h>
e24c7452	13
2cc8d922 SS	14	/* Synopsys DW SSI IP-core virtual IDs */
	15	#define DW_PSSI_ID 0
	16	#define DW_HSSI_ID 1
	17
	18	/* Synopsys DW SSI component versions (FourCC sequence) */
	19	#define DW_HSSI_102A 0x3130322a
	20
	21	/* DW SSI IP-core ID and version check helpers */
	22	#define dw_spi_ip_is(_dws, _ip) \
	23	((_dws)->ip == DW_ ## _ip ## _ID)
	24
	25	#define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
5d76b750	26	(dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
2cc8d922 SS	27
	28	#define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
	29
	30	#define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=)
	31
	32	/* DW SPI controller capabilities */
	33	#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
dc4e6d9f	34	#define DW_SPI_CAP_DFS32 BIT(1)
2cc8d922	35
725b0e3e	36	/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
299cb65c WAZ	37	#define DW_SPI_CTRLR0 0x00
299cb65c WAZ	38	#define DW_SPI_CTRLR1 0x04
7eb187b3 HS	39	#define DW_SPI_SSIENR 0x08
	40	#define DW_SPI_MWCR 0x0c
	41	#define DW_SPI_SER 0x10
	42	#define DW_SPI_BAUDR 0x14
299cb65c WAZ	43	#define DW_SPI_TXFTLR 0x18
299cb65c WAZ	44	#define DW_SPI_RXFTLR 0x1c
7eb187b3 HS	45	#define DW_SPI_TXFLR 0x20
	46	#define DW_SPI_RXFLR 0x24
	47	#define DW_SPI_SR 0x28
	48	#define DW_SPI_IMR 0x2c
	49	#define DW_SPI_ISR 0x30
	50	#define DW_SPI_RISR 0x34
	51	#define DW_SPI_TXOICR 0x38
	52	#define DW_SPI_RXOICR 0x3c
	53	#define DW_SPI_RXUICR 0x40
	54	#define DW_SPI_MSTICR 0x44
	55	#define DW_SPI_ICR 0x48
	56	#define DW_SPI_DMACR 0x4c
	57	#define DW_SPI_DMATDLR 0x50
	58	#define DW_SPI_DMARDLR 0x54
	59	#define DW_SPI_IDR 0x58
	60	#define DW_SPI_VERSION 0x5c
	61	#define DW_SPI_DR 0x60
bac70b54	62	#define DW_SPI_RX_SAMPLE_DLY 0xf0
f2d70479	63	#define DW_SPI_CS_OVERRIDE 0xf4
7eb187b3	64
725b0e3e	65	/* Bit fields in CTRLR0 (DWC APB SSI) */
725b0e3e	66	#define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)
ec77c086	67	#define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)
725b0e3e	68
ec77c086	69	#define DW_PSSI_CTRLR0_FRF_MASK GENMASK(5, 4)
725b0e3e SS	70	#define DW_SPI_CTRLR0_FRF_MOTO_SPI 0x0
	71	#define DW_SPI_CTRLR0_FRF_TI_SSP 0x1
	72	#define DW_SPI_CTRLR0_FRF_NS_MICROWIRE 0x2
	73	#define DW_SPI_CTRLR0_FRF_RESV 0x3
	74
ec77c086 SS	75	#define DW_PSSI_CTRLR0_MODE_MASK GENMASK(7, 6)
	76	#define DW_PSSI_CTRLR0_SCPHA BIT(6)
	77	#define DW_PSSI_CTRLR0_SCPOL BIT(7)
725b0e3e	78
ec77c086	79	#define DW_PSSI_CTRLR0_TMOD_MASK GENMASK(9, 8)
725b0e3e SS	80	#define DW_SPI_CTRLR0_TMOD_TR 0x0 /* xmit & recv */
	81	#define DW_SPI_CTRLR0_TMOD_TO 0x1 /* xmit only */
	82	#define DW_SPI_CTRLR0_TMOD_RO 0x2 /* recv only */
	83	#define DW_SPI_CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
	84
ec77c086 SS	85	#define DW_PSSI_CTRLR0_SLV_OE BIT(10)
	86	#define DW_PSSI_CTRLR0_SRL BIT(11)
	87	#define DW_PSSI_CTRLR0_CFS BIT(12)
725b0e3e SS	88
725b0e3e SS	89	/* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
ec77c086 SS	90	#define DW_HSSI_CTRLR0_DFS_MASK GENMASK(4, 0)
	91	#define DW_HSSI_CTRLR0_FRF_MASK GENMASK(7, 6)
	92	#define DW_HSSI_CTRLR0_SCPHA BIT(8)
	93	#define DW_HSSI_CTRLR0_SCPOL BIT(9)
725b0e3e	94	#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
ec77c086	95	#define DW_HSSI_CTRLR0_SRL BIT(13)
51e41dc2	96	#define DW_HSSI_CTRLR0_MST BIT(31)
ffb7ca54	97
6423207e	98	/* Bit fields in CTRLR1 */
725b0e3e	99	#define DW_SPI_NDF_MASK GENMASK(15, 0)
6423207e	100
e24c7452	101	/* Bit fields in SR, 7 bits */
ec77c086 SS	102	#define DW_SPI_SR_MASK GENMASK(6, 0)
	103	#define DW_SPI_SR_BUSY BIT(0)
	104	#define DW_SPI_SR_TF_NOT_FULL BIT(1)
	105	#define DW_SPI_SR_TF_EMPT BIT(2)
	106	#define DW_SPI_SR_RF_NOT_EMPT BIT(3)
	107	#define DW_SPI_SR_RF_FULL BIT(4)
	108	#define DW_SPI_SR_TX_ERR BIT(5)
	109	#define DW_SPI_SR_DCOL BIT(6)
e24c7452 FT	110
e24c7452 FT	111	/* Bit fields in ISR, IMR, RISR, 7 bits */
ec77c086 SS	112	#define DW_SPI_INT_MASK GENMASK(5, 0)
	113	#define DW_SPI_INT_TXEI BIT(0)
	114	#define DW_SPI_INT_TXOI BIT(1)
	115	#define DW_SPI_INT_RXUI BIT(2)
	116	#define DW_SPI_INT_RXOI BIT(3)
	117	#define DW_SPI_INT_RXFI BIT(4)
	118	#define DW_SPI_INT_MSTI BIT(5)
e24c7452	119
15ee3be7	120	/* Bit fields in DMACR */
ec77c086 SS	121	#define DW_SPI_DMACR_RDMAE BIT(0)
ec77c086 SS	122	#define DW_SPI_DMACR_TDMAE BIT(1)
15ee3be7	123
725b0e3e SS	124	/* Mem/DMA operations helpers */
	125	#define DW_SPI_WAIT_RETRIES 5
	126	#define DW_SPI_BUF_SIZE \
6423207e SS	127	(sizeof_field(struct spi_mem_op, cmd.opcode) + \
6423207e SS	128	sizeof_field(struct spi_mem_op, addr.val) + 256)
725b0e3e	129	#define DW_SPI_GET_BYTE(_val, _idx) \
6423207e	130	((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
cf75baea	131
3ff60c6b SS	132	/* Slave spi_transfer/spi_mem_op related */
	133	struct dw_spi_cfg {
	134	u8 tmode;
	135	u8 dfs;
	136	u32 ndf;
	137	u32 freq;
	138	};
	139
7063c0d9 FT	140	struct dw_spi;
7063c0d9 FT	141	struct dw_spi_dma_ops {
6370abab	142	int (dma_init)(struct device dev, struct dw_spi *dws);
7063c0d9	143	void (dma_exit)(struct dw_spi dws);
f89a6d8f	144	int (dma_setup)(struct dw_spi dws, struct spi_transfer *xfer);
eefc6c5c	145	bool (can_dma)(struct spi_controller host, struct spi_device *spi,
f89a6d8f AS	146	struct spi_transfer *xfer);
f89a6d8f AS	147	int (dma_transfer)(struct dw_spi dws, struct spi_transfer *xfer);
4d5ac1ed	148	void (dma_stop)(struct dw_spi dws);
7063c0d9 FT	149	};
7063c0d9 FT	150
e24c7452	151	struct dw_spi {
eefc6c5c	152	struct spi_controller *host;
e24c7452	153
2cc8d922 SS	154	u32 ip; /* Synopsys DW SSI IP-core ID */
	155	u32 ver; /* Synopsys component version */
	156	u32 caps; /* DW SPI capabilities */
	157
e24c7452 FT	158	void __iomem *regs;
e24c7452 FT	159	unsigned long paddr;
e24c7452	160	int irq;
552e4509	161	u32 fifo_len; /* depth of the FIFO buffer */
a51acc24	162	unsigned int dfs_offset; /* CTRLR0 DFS field offset */
84ecaf4a	163	u32 max_mem_freq; /* max mem-ops bus freq */
e24c7452 FT	164	u32 max_freq; /* max bus freq supported */
e24c7452 FT	165
c4fe57f7	166	u32 reg_io_width; /* DR I/O width in bytes */
e24c7452 FT	167	u16 bus_num;
e24c7452 FT	168	u16 num_cs; /* supported slave numbers */
62dbbae4	169	void (set_cs)(struct spi_device spi, bool enable);
e24c7452	170
e24c7452	171	/* Current message transfer state info */
e24c7452	172	void *tx;
8dedbeac	173	unsigned int tx_len;
e24c7452	174	void *rx;
8dedbeac	175	unsigned int rx_len;
725b0e3e	176	u8 buf[DW_SPI_BUF_SIZE];
e24c7452	177	int dma_mapped;
e24c7452	178	u8 n_bytes; /* current is a 1/2 bytes op */
e24c7452	179	irqreturn_t (transfer_handler)(struct dw_spi dws);
13b10301	180	u32 current_freq; /* frequency in hz */
bac70b54 LP	181	u32 cur_rx_sample_dly;
bac70b54 LP	182	u32 def_rx_sample_dly_ns;
e24c7452	183
6423207e SS	184	/* Custom memory operations */
	185	struct spi_controller_mem_ops mem_ops;
	186
f89a6d8f	187	/* DMA info */
e24c7452	188	struct dma_chan *txchan;
0b2b6651	189	u32 txburst;
e24c7452	190	struct dma_chan *rxchan;
0b2b6651	191	u32 rxburst;
ad4fe126	192	u32 dma_sg_burst;
020a3947	193	u32 dma_addr_widths;
30c8eb52	194	unsigned long dma_chan_busy;
7063c0d9	195	dma_addr_t dma_addr; /* phy address of the Data register */
4fe338c9	196	const struct dw_spi_dma_ops *dma_ops;
bdbdf0f0	197	struct completion dma_completion;
e24c7452	198
e24c7452 FT	199	#ifdef CONFIG_DEBUG_FS
e24c7452 FT	200	struct dentry *debugfs;
8378449d	201	struct debugfs_regset32 regset;
e24c7452 FT	202	#endif
	203	};
	204
7eb187b3 HS	205	static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
	206	{
	207	return __raw_readl(dws->regs + offset);
	208	}
	209
	210	static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
	211	{
	212	__raw_writel(val, dws->regs + offset);
	213	}
	214
c4fe57f7 MW	215	static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
	216	{
	217	switch (dws->reg_io_width) {
	218	case 2:
7e31cea7	219	return readw_relaxed(dws->regs + offset);
c4fe57f7 MW	220	case 4:
c4fe57f7 MW	221	default:
7e31cea7	222	return readl_relaxed(dws->regs + offset);
c4fe57f7 MW	223	}
	224	}
	225
	226	static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
	227	{
	228	switch (dws->reg_io_width) {
	229	case 2:
7e31cea7	230	writew_relaxed(val, dws->regs + offset);
c4fe57f7 MW	231	break;
	232	case 4:
	233	default:
7e31cea7	234	writel_relaxed(val, dws->regs + offset);
c4fe57f7 MW	235	break;
	236	}
	237	}
	238
725b0e3e	239	static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
e24c7452	240	{
7eb187b3	241	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
e24c7452 FT	242	}
e24c7452 FT	243
725b0e3e	244	static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
e24c7452	245	{
7eb187b3	246	dw_writel(dws, DW_SPI_BAUDR, div);
e24c7452 FT	247	}
e24c7452 FT	248
e24c7452	249	/* Disable IRQ bits */
725b0e3e	250	static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
e24c7452 FT	251	{
	252	u32 new_mask;
	253
7eb187b3 HS	254	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
7eb187b3 HS	255	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	256	}
	257
	258	/* Enable IRQ bits */
725b0e3e	259	static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
e24c7452 FT	260	{
	261	u32 new_mask;
	262
7eb187b3 HS	263	new_mask = dw_readl(dws, DW_SPI_IMR) \| mask;
7eb187b3 HS	264	dw_writel(dws, DW_SPI_IMR, new_mask);
e24c7452 FT	265	}
e24c7452 FT	266
45746e82	267	/*
fbddc989 SS	268	* This disables the SPI controller, interrupts, clears the interrupts status
	269	* and CS, then re-enables the controller back. Transmit and receive FIFO
	270	* buffers are cleared when the device is disabled.
45746e82	271	*/
725b0e3e	272	static inline void dw_spi_reset_chip(struct dw_spi *dws)
45746e82	273	{
725b0e3e SS	274	dw_spi_enable_chip(dws, 0);
725b0e3e SS	275	dw_spi_mask_intr(dws, 0xff);
a128f6ec	276	dw_readl(dws, DW_SPI_ICR);
fbddc989	277	dw_writel(dws, DW_SPI_SER, 0);
725b0e3e	278	dw_spi_enable_chip(dws, 1);
45746e82 AS	279	}
45746e82 AS	280
725b0e3e	281	static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
1cc3f141	282	{
725b0e3e SS	283	dw_spi_enable_chip(dws, 0);
725b0e3e SS	284	dw_spi_set_clk(dws, 0);
1cc3f141 AS	285	}
1cc3f141 AS	286
c79bdbb4	287	extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
3ff60c6b SS	288	extern void dw_spi_update_config(struct dw_spi dws, struct spi_device spi,
3ff60c6b SS	289	struct dw_spi_cfg *cfg);
bf64b660	290	extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
04f421e7	291	extern int dw_spi_add_host(struct device dev, struct dw_spi dws);
e24c7452 FT	292	extern void dw_spi_remove_host(struct dw_spi *dws);
	293	extern int dw_spi_suspend_host(struct dw_spi *dws);
	294	extern int dw_spi_resume_host(struct dw_spi *dws);
7063c0d9	295
6c710c0c SS	296	#ifdef CONFIG_SPI_DW_DMA
6c710c0c SS	297
57784411 SS	298	extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
57784411 SS	299	extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
6c710c0c SS	300
	301	#else
	302
57784411 SS	303	static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
57784411 SS	304	static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
6c710c0c SS	305
6c710c0c SS	306	#endif /* !CONFIG_SPI_DW_DMA */
37aa8aa6	307
725b0e3e	308	#endif /* __SPI_DW_H__ */