Commit | Line | Data |
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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e24c7452 | 2 | /* |
ca632f55 | 3 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
4 | * |
5 | * Copyright (c) 2009, Intel Corporation. | |
e24c7452 FT |
6 | */ |
7 | ||
8 | #include <linux/dma-mapping.h> | |
9 | #include <linux/interrupt.h> | |
d7614de4 | 10 | #include <linux/module.h> |
e24c7452 FT |
11 | #include <linux/highmem.h> |
12 | #include <linux/delay.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
e24c7452 FT |
14 | #include <linux/spi/spi.h> |
15 | ||
ca632f55 | 16 | #include "spi-dw.h" |
568a60ed | 17 | |
e24c7452 FT |
18 | #ifdef CONFIG_DEBUG_FS |
19 | #include <linux/debugfs.h> | |
20 | #endif | |
21 | ||
e24c7452 FT |
22 | /* Slave spi_dev related */ |
23 | struct chip_data { | |
e24c7452 FT |
24 | u8 tmode; /* TR/TO/RO/EEPROM */ |
25 | u8 type; /* SPI/SSP/MicroWire */ | |
26 | ||
e24c7452 FT |
27 | u16 clk_div; /* baud rate divider */ |
28 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
29 | }; |
30 | ||
31 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 32 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
33 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
34 | size_t count, loff_t *ppos) | |
e24c7452 | 35 | { |
53288fe9 | 36 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
37 | char *buf; |
38 | u32 len = 0; | |
39 | ssize_t ret; | |
40 | ||
e24c7452 FT |
41 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
42 | if (!buf) | |
43 | return 0; | |
44 | ||
d1d6bd78 | 45 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
53288fe9 | 46 | "%s registers:\n", dev_name(&dws->master->dev)); |
d1d6bd78 | 47 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
e24c7452 | 48 | "=================================\n"); |
d1d6bd78 | 49 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 50 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
d1d6bd78 | 51 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 52 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
d1d6bd78 | 53 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 54 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
d1d6bd78 | 55 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 56 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
d1d6bd78 | 57 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 58 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
d1d6bd78 | 59 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 60 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
d1d6bd78 | 61 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 62 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
d1d6bd78 | 63 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 64 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
d1d6bd78 | 65 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 66 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
d1d6bd78 | 67 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 68 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
d1d6bd78 | 69 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 70 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
d1d6bd78 | 71 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 72 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
d1d6bd78 | 73 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 74 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
d1d6bd78 | 75 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 76 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
d1d6bd78 | 77 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 78 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
d1d6bd78 | 79 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
e24c7452 FT |
80 | "=================================\n"); |
81 | ||
53288fe9 | 82 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
83 | kfree(buf); |
84 | return ret; | |
85 | } | |
86 | ||
53288fe9 | 87 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 88 | .owner = THIS_MODULE, |
234e3405 | 89 | .open = simple_open, |
53288fe9 | 90 | .read = dw_spi_show_regs, |
6038f373 | 91 | .llseek = default_llseek, |
e24c7452 FT |
92 | }; |
93 | ||
53288fe9 | 94 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 95 | { |
e70002c8 | 96 | char name[32]; |
13288bdf | 97 | |
e70002c8 | 98 | snprintf(name, 32, "dw_spi%d", dws->master->bus_num); |
13288bdf | 99 | dws->debugfs = debugfs_create_dir(name, NULL); |
e24c7452 FT |
100 | if (!dws->debugfs) |
101 | return -ENOMEM; | |
102 | ||
103 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 104 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
105 | return 0; |
106 | } | |
107 | ||
53288fe9 | 108 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 109 | { |
fadcace7 | 110 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
111 | } |
112 | ||
113 | #else | |
53288fe9 | 114 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 115 | { |
20a588fc | 116 | return 0; |
e24c7452 FT |
117 | } |
118 | ||
53288fe9 | 119 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
120 | { |
121 | } | |
122 | #endif /* CONFIG_DEBUG_FS */ | |
123 | ||
c79bdbb4 | 124 | void dw_spi_set_cs(struct spi_device *spi, bool enable) |
c22c62db | 125 | { |
721483e2 | 126 | struct dw_spi *dws = spi_controller_get_devdata(spi->controller); |
c22c62db | 127 | |
ada9e3fc | 128 | if (!enable) |
c22c62db | 129 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); |
f2d70479 TS |
130 | else if (dws->cs_override) |
131 | dw_writel(dws, DW_SPI_SER, 0); | |
c22c62db | 132 | } |
c79bdbb4 | 133 | EXPORT_SYMBOL_GPL(dw_spi_set_cs); |
c22c62db | 134 | |
2ff271bf AD |
135 | /* Return the max entries we can fill into tx fifo */ |
136 | static inline u32 tx_max(struct dw_spi *dws) | |
137 | { | |
138 | u32 tx_left, tx_room, rxtx_gap; | |
139 | ||
140 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
dd114443 | 141 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
2ff271bf AD |
142 | |
143 | /* | |
144 | * Another concern is about the tx/rx mismatch, we | |
145 | * though to use (dws->fifo_len - rxflr - txflr) as | |
146 | * one maximum value for tx, but it doesn't cover the | |
147 | * data which is out of tx/rx fifo and inside the | |
148 | * shift registers. So a control from sw point of | |
149 | * view is taken. | |
150 | */ | |
151 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
152 | / dws->n_bytes; | |
153 | ||
154 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
155 | } | |
156 | ||
157 | /* Return the max entries we should read out of rx fifo */ | |
158 | static inline u32 rx_max(struct dw_spi *dws) | |
159 | { | |
160 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
161 | ||
dd114443 | 162 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
163 | } |
164 | ||
3b8a4dd3 | 165 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 166 | { |
19b61392 | 167 | u32 max; |
de6efe0a | 168 | u16 txw = 0; |
e24c7452 | 169 | |
19b61392 | 170 | spin_lock(&dws->buf_lock); |
171 | max = tx_max(dws); | |
2ff271bf AD |
172 | while (max--) { |
173 | /* Set the tx word if the transfer's original "tx" is not null */ | |
174 | if (dws->tx_end - dws->len) { | |
175 | if (dws->n_bytes == 1) | |
176 | txw = *(u8 *)(dws->tx); | |
177 | else | |
178 | txw = *(u16 *)(dws->tx); | |
179 | } | |
c4fe57f7 | 180 | dw_write_io_reg(dws, DW_SPI_DR, txw); |
2ff271bf | 181 | dws->tx += dws->n_bytes; |
e24c7452 | 182 | } |
19b61392 | 183 | spin_unlock(&dws->buf_lock); |
e24c7452 FT |
184 | } |
185 | ||
3b8a4dd3 | 186 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 187 | { |
19b61392 | 188 | u32 max; |
de6efe0a | 189 | u16 rxw; |
e24c7452 | 190 | |
19b61392 | 191 | spin_lock(&dws->buf_lock); |
192 | max = rx_max(dws); | |
2ff271bf | 193 | while (max--) { |
c4fe57f7 | 194 | rxw = dw_read_io_reg(dws, DW_SPI_DR); |
de6efe0a FT |
195 | /* Care rx only if the transfer's original "rx" is not null */ |
196 | if (dws->rx_end - dws->len) { | |
197 | if (dws->n_bytes == 1) | |
198 | *(u8 *)(dws->rx) = rxw; | |
199 | else | |
200 | *(u16 *)(dws->rx) = rxw; | |
201 | } | |
202 | dws->rx += dws->n_bytes; | |
e24c7452 | 203 | } |
19b61392 | 204 | spin_unlock(&dws->buf_lock); |
e24c7452 FT |
205 | } |
206 | ||
e24c7452 FT |
207 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
208 | { | |
45746e82 | 209 | spi_reset_chip(dws); |
e24c7452 FT |
210 | |
211 | dev_err(&dws->master->dev, "%s\n", msg); | |
c22c62db AS |
212 | dws->master->cur_msg->status = -EIO; |
213 | spi_finalize_current_transfer(dws->master); | |
e24c7452 FT |
214 | } |
215 | ||
e24c7452 FT |
216 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
217 | { | |
dd114443 | 218 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
e24c7452 | 219 | |
e24c7452 FT |
220 | /* Error handling */ |
221 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
dd114443 | 222 | dw_readl(dws, DW_SPI_ICR); |
3b8a4dd3 | 223 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
224 | return IRQ_HANDLED; |
225 | } | |
226 | ||
3b8a4dd3 AD |
227 | dw_reader(dws); |
228 | if (dws->rx_end == dws->rx) { | |
229 | spi_mask_intr(dws, SPI_INT_TXEI); | |
c22c62db | 230 | spi_finalize_current_transfer(dws->master); |
3b8a4dd3 AD |
231 | return IRQ_HANDLED; |
232 | } | |
552e4509 FT |
233 | if (irq_status & SPI_INT_TXEI) { |
234 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
235 | dw_writer(dws); |
236 | /* Enable TX irq always, it will be disabled when RX finished */ | |
237 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
238 | } |
239 | ||
e24c7452 FT |
240 | return IRQ_HANDLED; |
241 | } | |
242 | ||
243 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
244 | { | |
721483e2 JN |
245 | struct spi_controller *master = dev_id; |
246 | struct dw_spi *dws = spi_controller_get_devdata(master); | |
dd114443 | 247 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 248 | |
cbcc062a YW |
249 | if (!irq_status) |
250 | return IRQ_NONE; | |
e24c7452 | 251 | |
c22c62db | 252 | if (!master->cur_msg) { |
e24c7452 | 253 | spi_mask_intr(dws, SPI_INT_TXEI); |
e24c7452 FT |
254 | return IRQ_HANDLED; |
255 | } | |
256 | ||
257 | return dws->transfer_handler(dws); | |
258 | } | |
259 | ||
721483e2 | 260 | static int dw_spi_transfer_one(struct spi_controller *master, |
c22c62db | 261 | struct spi_device *spi, struct spi_transfer *transfer) |
e24c7452 | 262 | { |
721483e2 | 263 | struct dw_spi *dws = spi_controller_get_devdata(master); |
c22c62db | 264 | struct chip_data *chip = spi_get_ctldata(spi); |
19b61392 | 265 | unsigned long flags; |
e24c7452 | 266 | u8 imask = 0; |
ea11370f | 267 | u16 txlevel = 0; |
4adb1f8f | 268 | u32 cr0; |
9f14538e | 269 | int ret; |
e24c7452 | 270 | |
f89a6d8f | 271 | dws->dma_mapped = 0; |
19b61392 | 272 | spin_lock_irqsave(&dws->buf_lock, flags); |
e24c7452 FT |
273 | dws->tx = (void *)transfer->tx_buf; |
274 | dws->tx_end = dws->tx + transfer->len; | |
275 | dws->rx = transfer->rx_buf; | |
276 | dws->rx_end = dws->rx + transfer->len; | |
c22c62db | 277 | dws->len = transfer->len; |
19b61392 | 278 | spin_unlock_irqrestore(&dws->buf_lock, flags); |
e24c7452 | 279 | |
bfda0445 XK |
280 | /* Ensure dw->rx and dw->rx_end are visible */ |
281 | smp_mb(); | |
282 | ||
0b2e8915 AS |
283 | spi_enable_chip(dws, 0); |
284 | ||
e24c7452 | 285 | /* Handle per transfer options for bpw and speed */ |
13b10301 MS |
286 | if (transfer->speed_hz != dws->current_freq) { |
287 | if (transfer->speed_hz != chip->speed_hz) { | |
288 | /* clk_div doesn't support odd number */ | |
3aef4632 | 289 | chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe; |
13b10301 MS |
290 | chip->speed_hz = transfer->speed_hz; |
291 | } | |
292 | dws->current_freq = transfer->speed_hz; | |
0ed36990 | 293 | spi_set_clk(dws, chip->clk_div); |
e24c7452 | 294 | } |
af060b3f SG |
295 | |
296 | dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); | |
297 | dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); | |
298 | ||
4adb1f8f | 299 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
0ed36990 JN |
300 | cr0 = (transfer->bits_per_word - 1) |
301 | | (chip->type << SPI_FRF_OFFSET) | |
e1bc2048 | 302 | | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) | |
1403cfa6 TT |
303 | (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) | |
304 | (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET)) | |
0ed36990 | 305 | | (chip->tmode << SPI_TMOD_OFFSET); |
e24c7452 | 306 | |
dd114443 | 307 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
0b2e8915 | 308 | |
e24c7452 | 309 | /* Check if current transfer is a DMA transaction */ |
f89a6d8f AS |
310 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
311 | dws->dma_mapped = master->cur_msg_mapped; | |
e24c7452 | 312 | |
0b2e8915 AS |
313 | /* For poll mode just disable all interrupts */ |
314 | spi_mask_intr(dws, 0xff); | |
315 | ||
552e4509 FT |
316 | /* |
317 | * Interrupt mode | |
318 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
319 | */ | |
9f14538e | 320 | if (dws->dma_mapped) { |
f89a6d8f | 321 | ret = dws->dma_ops->dma_setup(dws, transfer); |
9f14538e AS |
322 | if (ret < 0) { |
323 | spi_enable_chip(dws, 1); | |
324 | return ret; | |
325 | } | |
33e8fd4b | 326 | } else { |
ea11370f | 327 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
dd114443 | 328 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
552e4509 | 329 | |
0b2e8915 | 330 | /* Set the interrupt mask */ |
fadcace7 JH |
331 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
332 | SPI_INT_RXUI | SPI_INT_RXOI; | |
0b2e8915 AS |
333 | spi_umask_intr(dws, imask); |
334 | ||
e24c7452 FT |
335 | dws->transfer_handler = interrupt_transfer; |
336 | } | |
337 | ||
0b2e8915 | 338 | spi_enable_chip(dws, 1); |
e24c7452 | 339 | |
9f14538e | 340 | if (dws->dma_mapped) { |
f89a6d8f | 341 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
9f14538e AS |
342 | if (ret < 0) |
343 | return ret; | |
344 | } | |
e24c7452 | 345 | |
c22c62db | 346 | return 1; |
e24c7452 FT |
347 | } |
348 | ||
721483e2 | 349 | static void dw_spi_handle_err(struct spi_controller *master, |
ec37e8e1 | 350 | struct spi_message *msg) |
e24c7452 | 351 | { |
721483e2 | 352 | struct dw_spi *dws = spi_controller_get_devdata(master); |
e24c7452 | 353 | |
4d5ac1ed AS |
354 | if (dws->dma_mapped) |
355 | dws->dma_ops->dma_stop(dws); | |
356 | ||
c22c62db | 357 | spi_reset_chip(dws); |
e24c7452 FT |
358 | } |
359 | ||
360 | /* This may be called twice for each spi dev */ | |
361 | static int dw_spi_setup(struct spi_device *spi) | |
362 | { | |
e24c7452 FT |
363 | struct chip_data *chip; |
364 | ||
e24c7452 FT |
365 | /* Only alloc on first setup */ |
366 | chip = spi_get_ctldata(spi); | |
367 | if (!chip) { | |
a97c883a | 368 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
e24c7452 FT |
369 | if (!chip) |
370 | return -ENOMEM; | |
43f627ac | 371 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
372 | } |
373 | ||
6096828e | 374 | chip->tmode = SPI_TMOD_TR; |
c3ce15bf | 375 | |
e24c7452 FT |
376 | return 0; |
377 | } | |
378 | ||
a97c883a AL |
379 | static void dw_spi_cleanup(struct spi_device *spi) |
380 | { | |
381 | struct chip_data *chip = spi_get_ctldata(spi); | |
382 | ||
383 | kfree(chip); | |
384 | spi_set_ctldata(spi, NULL); | |
385 | } | |
386 | ||
e24c7452 | 387 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
30b4b703 | 388 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
e24c7452 | 389 | { |
45746e82 | 390 | spi_reset_chip(dws); |
c587b6fa FT |
391 | |
392 | /* | |
393 | * Try to detect the FIFO depth if not set by interface driver, | |
394 | * the depth could be from 2 to 256 from HW spec | |
395 | */ | |
396 | if (!dws->fifo_len) { | |
397 | u32 fifo; | |
fadcace7 | 398 | |
9d239d35 | 399 | for (fifo = 1; fifo < 256; fifo++) { |
dd114443 TT |
400 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
401 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
402 | break; |
403 | } | |
dd114443 | 404 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 405 | |
9d239d35 | 406 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
30b4b703 | 407 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
c587b6fa | 408 | } |
f2d70479 TS |
409 | |
410 | /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */ | |
411 | if (dws->cs_override) | |
412 | dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF); | |
e24c7452 FT |
413 | } |
414 | ||
04f421e7 | 415 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 | 416 | { |
721483e2 | 417 | struct spi_controller *master; |
e24c7452 FT |
418 | int ret; |
419 | ||
169f9aca AP |
420 | if (!dws) |
421 | return -EINVAL; | |
e24c7452 | 422 | |
04f421e7 BS |
423 | master = spi_alloc_master(dev, 0); |
424 | if (!master) | |
425 | return -ENOMEM; | |
e24c7452 FT |
426 | |
427 | dws->master = master; | |
428 | dws->type = SSI_MOTO_SPI; | |
e24c7452 | 429 | dws->dma_inited = 0; |
d7ef54ca | 430 | dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); |
19b61392 | 431 | spin_lock_init(&dws->buf_lock); |
e24c7452 | 432 | |
66b19d76 AB |
433 | spi_controller_set_devdata(master, dws); |
434 | ||
e70002c8 PR |
435 | ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), |
436 | master); | |
e24c7452 | 437 | if (ret < 0) { |
5f0966e6 | 438 | dev_err(dev, "can not get IRQ\n"); |
e24c7452 FT |
439 | goto err_free_master; |
440 | } | |
441 | ||
9400c41e | 442 | master->use_gpio_descriptors = true; |
c3ce15bf | 443 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
af060b3f | 444 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e24c7452 FT |
445 | master->bus_num = dws->bus_num; |
446 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 447 | master->setup = dw_spi_setup; |
a97c883a | 448 | master->cleanup = dw_spi_cleanup; |
c22c62db AS |
449 | master->set_cs = dw_spi_set_cs; |
450 | master->transfer_one = dw_spi_transfer_one; | |
451 | master->handle_err = dw_spi_handle_err; | |
765ee709 | 452 | master->max_speed_hz = dws->max_freq; |
9c6de47d | 453 | master->dev.of_node = dev->of_node; |
32215a6c | 454 | master->dev.fwnode = dev->fwnode; |
80b444e5 | 455 | master->flags = SPI_MASTER_GPIO_SS; |
1e695983 | 456 | master->auto_runtime_pm = true; |
e24c7452 | 457 | |
62dbbae4 AB |
458 | if (dws->set_cs) |
459 | master->set_cs = dws->set_cs; | |
460 | ||
e24c7452 | 461 | /* Basic HW init */ |
30b4b703 | 462 | spi_hw_init(dev, dws); |
e24c7452 | 463 | |
7063c0d9 FT |
464 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
465 | ret = dws->dma_ops->dma_init(dws); | |
466 | if (ret) { | |
3dbb3b98 | 467 | dev_warn(dev, "DMA init failed\n"); |
7063c0d9 | 468 | dws->dma_inited = 0; |
f89a6d8f AS |
469 | } else { |
470 | master->can_dma = dws->dma_ops->can_dma; | |
7063c0d9 FT |
471 | } |
472 | } | |
473 | ||
721483e2 | 474 | ret = devm_spi_register_controller(dev, master); |
e24c7452 FT |
475 | if (ret) { |
476 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 477 | goto err_dma_exit; |
e24c7452 FT |
478 | } |
479 | ||
53288fe9 | 480 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
481 | return 0; |
482 | ||
ec37e8e1 | 483 | err_dma_exit: |
7063c0d9 FT |
484 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
485 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 486 | spi_enable_chip(dws, 0); |
02f20387 | 487 | free_irq(dws->irq, master); |
e24c7452 | 488 | err_free_master: |
721483e2 | 489 | spi_controller_put(master); |
e24c7452 FT |
490 | return ret; |
491 | } | |
79290a2a | 492 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 493 | |
fd4a319b | 494 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 495 | { |
53288fe9 | 496 | dw_spi_debugfs_remove(dws); |
e24c7452 | 497 | |
7063c0d9 FT |
498 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
499 | dws->dma_ops->dma_exit(dws); | |
1cc3f141 AS |
500 | |
501 | spi_shutdown_chip(dws); | |
02f20387 AS |
502 | |
503 | free_irq(dws->irq, dws->master); | |
e24c7452 | 504 | } |
79290a2a | 505 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
506 | |
507 | int dw_spi_suspend_host(struct dw_spi *dws) | |
508 | { | |
1cc3f141 | 509 | int ret; |
e24c7452 | 510 | |
721483e2 | 511 | ret = spi_controller_suspend(dws->master); |
e24c7452 FT |
512 | if (ret) |
513 | return ret; | |
1cc3f141 AS |
514 | |
515 | spi_shutdown_chip(dws); | |
516 | return 0; | |
e24c7452 | 517 | } |
79290a2a | 518 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
519 | |
520 | int dw_spi_resume_host(struct dw_spi *dws) | |
521 | { | |
30b4b703 | 522 | spi_hw_init(&dws->master->dev, dws); |
7c5d8a24 | 523 | return spi_controller_resume(dws->master); |
e24c7452 | 524 | } |
79290a2a | 525 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
526 | |
527 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
528 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
529 | MODULE_LICENSE("GPL v2"); |