Commit | Line | Data |
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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e24c7452 | 2 | /* |
ca632f55 | 3 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
4 | * |
5 | * Copyright (c) 2009, Intel Corporation. | |
e24c7452 FT |
6 | */ |
7 | ||
8 | #include <linux/dma-mapping.h> | |
9 | #include <linux/interrupt.h> | |
d7614de4 | 10 | #include <linux/module.h> |
e24c7452 FT |
11 | #include <linux/highmem.h> |
12 | #include <linux/delay.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
e24c7452 FT |
14 | #include <linux/spi/spi.h> |
15 | ||
ca632f55 | 16 | #include "spi-dw.h" |
568a60ed | 17 | |
e24c7452 FT |
18 | #ifdef CONFIG_DEBUG_FS |
19 | #include <linux/debugfs.h> | |
20 | #endif | |
21 | ||
e24c7452 FT |
22 | /* Slave spi_dev related */ |
23 | struct chip_data { | |
e24c7452 FT |
24 | u8 tmode; /* TR/TO/RO/EEPROM */ |
25 | u8 type; /* SPI/SSP/MicroWire */ | |
26 | ||
27 | u8 poll_mode; /* 1 means use poll mode */ | |
28 | ||
e24c7452 FT |
29 | u16 clk_div; /* baud rate divider */ |
30 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
31 | void (*cs_control)(u32 command); |
32 | }; | |
33 | ||
34 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 35 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
36 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
37 | size_t count, loff_t *ppos) | |
e24c7452 | 38 | { |
53288fe9 | 39 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
40 | char *buf; |
41 | u32 len = 0; | |
42 | ssize_t ret; | |
43 | ||
e24c7452 FT |
44 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
45 | if (!buf) | |
46 | return 0; | |
47 | ||
d1d6bd78 | 48 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
53288fe9 | 49 | "%s registers:\n", dev_name(&dws->master->dev)); |
d1d6bd78 | 50 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
e24c7452 | 51 | "=================================\n"); |
d1d6bd78 | 52 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 53 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
d1d6bd78 | 54 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 55 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
d1d6bd78 | 56 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 57 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
d1d6bd78 | 58 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 59 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
d1d6bd78 | 60 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 61 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
d1d6bd78 | 62 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 63 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
d1d6bd78 | 64 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 65 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
d1d6bd78 | 66 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 67 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
d1d6bd78 | 68 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 69 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
d1d6bd78 | 70 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 71 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
d1d6bd78 | 72 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 73 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
d1d6bd78 | 74 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 75 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
d1d6bd78 | 76 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 77 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
d1d6bd78 | 78 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 79 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
d1d6bd78 | 80 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 81 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
d1d6bd78 | 82 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
e24c7452 FT |
83 | "=================================\n"); |
84 | ||
53288fe9 | 85 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
86 | kfree(buf); |
87 | return ret; | |
88 | } | |
89 | ||
53288fe9 | 90 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 91 | .owner = THIS_MODULE, |
234e3405 | 92 | .open = simple_open, |
53288fe9 | 93 | .read = dw_spi_show_regs, |
6038f373 | 94 | .llseek = default_llseek, |
e24c7452 FT |
95 | }; |
96 | ||
53288fe9 | 97 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 98 | { |
e70002c8 | 99 | char name[32]; |
13288bdf | 100 | |
e70002c8 | 101 | snprintf(name, 32, "dw_spi%d", dws->master->bus_num); |
13288bdf | 102 | dws->debugfs = debugfs_create_dir(name, NULL); |
e24c7452 FT |
103 | if (!dws->debugfs) |
104 | return -ENOMEM; | |
105 | ||
106 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 107 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
108 | return 0; |
109 | } | |
110 | ||
53288fe9 | 111 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 112 | { |
fadcace7 | 113 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
114 | } |
115 | ||
116 | #else | |
53288fe9 | 117 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 118 | { |
20a588fc | 119 | return 0; |
e24c7452 FT |
120 | } |
121 | ||
53288fe9 | 122 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
123 | { |
124 | } | |
125 | #endif /* CONFIG_DEBUG_FS */ | |
126 | ||
c79bdbb4 | 127 | void dw_spi_set_cs(struct spi_device *spi, bool enable) |
c22c62db | 128 | { |
721483e2 | 129 | struct dw_spi *dws = spi_controller_get_devdata(spi->controller); |
c22c62db AS |
130 | struct chip_data *chip = spi_get_ctldata(spi); |
131 | ||
ada9e3fc | 132 | /* Chip select logic is inverted from spi_set_cs() */ |
207cda93 | 133 | if (chip && chip->cs_control) |
ada9e3fc | 134 | chip->cs_control(!enable); |
c22c62db | 135 | |
ada9e3fc | 136 | if (!enable) |
c22c62db | 137 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); |
f2d70479 TS |
138 | else if (dws->cs_override) |
139 | dw_writel(dws, DW_SPI_SER, 0); | |
c22c62db | 140 | } |
c79bdbb4 | 141 | EXPORT_SYMBOL_GPL(dw_spi_set_cs); |
c22c62db | 142 | |
2ff271bf AD |
143 | /* Return the max entries we can fill into tx fifo */ |
144 | static inline u32 tx_max(struct dw_spi *dws) | |
145 | { | |
146 | u32 tx_left, tx_room, rxtx_gap; | |
147 | ||
148 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
dd114443 | 149 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
2ff271bf AD |
150 | |
151 | /* | |
152 | * Another concern is about the tx/rx mismatch, we | |
153 | * though to use (dws->fifo_len - rxflr - txflr) as | |
154 | * one maximum value for tx, but it doesn't cover the | |
155 | * data which is out of tx/rx fifo and inside the | |
156 | * shift registers. So a control from sw point of | |
157 | * view is taken. | |
158 | */ | |
159 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
160 | / dws->n_bytes; | |
161 | ||
162 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
163 | } | |
164 | ||
165 | /* Return the max entries we should read out of rx fifo */ | |
166 | static inline u32 rx_max(struct dw_spi *dws) | |
167 | { | |
168 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
169 | ||
dd114443 | 170 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
171 | } |
172 | ||
3b8a4dd3 | 173 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 174 | { |
19b61392 | 175 | u32 max; |
de6efe0a | 176 | u16 txw = 0; |
e24c7452 | 177 | |
19b61392 | 178 | spin_lock(&dws->buf_lock); |
179 | max = tx_max(dws); | |
2ff271bf AD |
180 | while (max--) { |
181 | /* Set the tx word if the transfer's original "tx" is not null */ | |
182 | if (dws->tx_end - dws->len) { | |
183 | if (dws->n_bytes == 1) | |
184 | txw = *(u8 *)(dws->tx); | |
185 | else | |
186 | txw = *(u16 *)(dws->tx); | |
187 | } | |
c4fe57f7 | 188 | dw_write_io_reg(dws, DW_SPI_DR, txw); |
2ff271bf | 189 | dws->tx += dws->n_bytes; |
e24c7452 | 190 | } |
19b61392 | 191 | spin_unlock(&dws->buf_lock); |
e24c7452 FT |
192 | } |
193 | ||
3b8a4dd3 | 194 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 195 | { |
19b61392 | 196 | u32 max; |
de6efe0a | 197 | u16 rxw; |
e24c7452 | 198 | |
19b61392 | 199 | spin_lock(&dws->buf_lock); |
200 | max = rx_max(dws); | |
2ff271bf | 201 | while (max--) { |
c4fe57f7 | 202 | rxw = dw_read_io_reg(dws, DW_SPI_DR); |
de6efe0a FT |
203 | /* Care rx only if the transfer's original "rx" is not null */ |
204 | if (dws->rx_end - dws->len) { | |
205 | if (dws->n_bytes == 1) | |
206 | *(u8 *)(dws->rx) = rxw; | |
207 | else | |
208 | *(u16 *)(dws->rx) = rxw; | |
209 | } | |
210 | dws->rx += dws->n_bytes; | |
e24c7452 | 211 | } |
19b61392 | 212 | spin_unlock(&dws->buf_lock); |
e24c7452 FT |
213 | } |
214 | ||
e24c7452 FT |
215 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
216 | { | |
45746e82 | 217 | spi_reset_chip(dws); |
e24c7452 FT |
218 | |
219 | dev_err(&dws->master->dev, "%s\n", msg); | |
c22c62db AS |
220 | dws->master->cur_msg->status = -EIO; |
221 | spi_finalize_current_transfer(dws->master); | |
e24c7452 FT |
222 | } |
223 | ||
e24c7452 FT |
224 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
225 | { | |
dd114443 | 226 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
e24c7452 | 227 | |
e24c7452 FT |
228 | /* Error handling */ |
229 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
dd114443 | 230 | dw_readl(dws, DW_SPI_ICR); |
3b8a4dd3 | 231 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
232 | return IRQ_HANDLED; |
233 | } | |
234 | ||
3b8a4dd3 AD |
235 | dw_reader(dws); |
236 | if (dws->rx_end == dws->rx) { | |
237 | spi_mask_intr(dws, SPI_INT_TXEI); | |
c22c62db | 238 | spi_finalize_current_transfer(dws->master); |
3b8a4dd3 AD |
239 | return IRQ_HANDLED; |
240 | } | |
552e4509 FT |
241 | if (irq_status & SPI_INT_TXEI) { |
242 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
243 | dw_writer(dws); |
244 | /* Enable TX irq always, it will be disabled when RX finished */ | |
245 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
246 | } |
247 | ||
e24c7452 FT |
248 | return IRQ_HANDLED; |
249 | } | |
250 | ||
251 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
252 | { | |
721483e2 JN |
253 | struct spi_controller *master = dev_id; |
254 | struct dw_spi *dws = spi_controller_get_devdata(master); | |
dd114443 | 255 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 256 | |
cbcc062a YW |
257 | if (!irq_status) |
258 | return IRQ_NONE; | |
e24c7452 | 259 | |
c22c62db | 260 | if (!master->cur_msg) { |
e24c7452 | 261 | spi_mask_intr(dws, SPI_INT_TXEI); |
e24c7452 FT |
262 | return IRQ_HANDLED; |
263 | } | |
264 | ||
265 | return dws->transfer_handler(dws); | |
266 | } | |
267 | ||
268 | /* Must be called inside pump_transfers() */ | |
c22c62db | 269 | static int poll_transfer(struct dw_spi *dws) |
e24c7452 | 270 | { |
2ff271bf AD |
271 | do { |
272 | dw_writer(dws); | |
de6efe0a | 273 | dw_reader(dws); |
2ff271bf AD |
274 | cpu_relax(); |
275 | } while (dws->rx_end > dws->rx); | |
e24c7452 | 276 | |
c22c62db | 277 | return 0; |
e24c7452 FT |
278 | } |
279 | ||
721483e2 | 280 | static int dw_spi_transfer_one(struct spi_controller *master, |
c22c62db | 281 | struct spi_device *spi, struct spi_transfer *transfer) |
e24c7452 | 282 | { |
721483e2 | 283 | struct dw_spi *dws = spi_controller_get_devdata(master); |
c22c62db | 284 | struct chip_data *chip = spi_get_ctldata(spi); |
19b61392 | 285 | unsigned long flags; |
e24c7452 | 286 | u8 imask = 0; |
ea11370f | 287 | u16 txlevel = 0; |
4adb1f8f | 288 | u32 cr0; |
9f14538e | 289 | int ret; |
e24c7452 | 290 | |
f89a6d8f | 291 | dws->dma_mapped = 0; |
19b61392 | 292 | spin_lock_irqsave(&dws->buf_lock, flags); |
e24c7452 FT |
293 | dws->tx = (void *)transfer->tx_buf; |
294 | dws->tx_end = dws->tx + transfer->len; | |
295 | dws->rx = transfer->rx_buf; | |
296 | dws->rx_end = dws->rx + transfer->len; | |
c22c62db | 297 | dws->len = transfer->len; |
19b61392 | 298 | spin_unlock_irqrestore(&dws->buf_lock, flags); |
e24c7452 | 299 | |
bfda0445 XK |
300 | /* Ensure dw->rx and dw->rx_end are visible */ |
301 | smp_mb(); | |
302 | ||
0b2e8915 AS |
303 | spi_enable_chip(dws, 0); |
304 | ||
e24c7452 | 305 | /* Handle per transfer options for bpw and speed */ |
13b10301 MS |
306 | if (transfer->speed_hz != dws->current_freq) { |
307 | if (transfer->speed_hz != chip->speed_hz) { | |
308 | /* clk_div doesn't support odd number */ | |
3aef4632 | 309 | chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe; |
13b10301 MS |
310 | chip->speed_hz = transfer->speed_hz; |
311 | } | |
312 | dws->current_freq = transfer->speed_hz; | |
0ed36990 | 313 | spi_set_clk(dws, chip->clk_div); |
e24c7452 | 314 | } |
af060b3f SG |
315 | |
316 | dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); | |
317 | dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); | |
318 | ||
4adb1f8f | 319 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
0ed36990 JN |
320 | cr0 = (transfer->bits_per_word - 1) |
321 | | (chip->type << SPI_FRF_OFFSET) | |
e1bc2048 | 322 | | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) | |
1403cfa6 TT |
323 | (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) | |
324 | (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET)) | |
0ed36990 | 325 | | (chip->tmode << SPI_TMOD_OFFSET); |
e24c7452 | 326 | |
052dc7c4 GS |
327 | /* |
328 | * Adjust transfer mode if necessary. Requires platform dependent | |
329 | * chipselect mechanism. | |
330 | */ | |
c22c62db | 331 | if (chip->cs_control) { |
052dc7c4 | 332 | if (dws->rx && dws->tx) |
e3e55ff5 | 333 | chip->tmode = SPI_TMOD_TR; |
052dc7c4 | 334 | else if (dws->rx) |
e3e55ff5 | 335 | chip->tmode = SPI_TMOD_RO; |
052dc7c4 | 336 | else |
e3e55ff5 | 337 | chip->tmode = SPI_TMOD_TO; |
052dc7c4 | 338 | |
e3e55ff5 | 339 | cr0 &= ~SPI_TMOD_MASK; |
052dc7c4 GS |
340 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
341 | } | |
342 | ||
dd114443 | 343 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
0b2e8915 | 344 | |
e24c7452 | 345 | /* Check if current transfer is a DMA transaction */ |
f89a6d8f AS |
346 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
347 | dws->dma_mapped = master->cur_msg_mapped; | |
e24c7452 | 348 | |
0b2e8915 AS |
349 | /* For poll mode just disable all interrupts */ |
350 | spi_mask_intr(dws, 0xff); | |
351 | ||
552e4509 FT |
352 | /* |
353 | * Interrupt mode | |
354 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
355 | */ | |
9f14538e | 356 | if (dws->dma_mapped) { |
f89a6d8f | 357 | ret = dws->dma_ops->dma_setup(dws, transfer); |
9f14538e AS |
358 | if (ret < 0) { |
359 | spi_enable_chip(dws, 1); | |
360 | return ret; | |
361 | } | |
362 | } else if (!chip->poll_mode) { | |
ea11370f | 363 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
dd114443 | 364 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
552e4509 | 365 | |
0b2e8915 | 366 | /* Set the interrupt mask */ |
fadcace7 JH |
367 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
368 | SPI_INT_RXUI | SPI_INT_RXOI; | |
0b2e8915 AS |
369 | spi_umask_intr(dws, imask); |
370 | ||
e24c7452 FT |
371 | dws->transfer_handler = interrupt_transfer; |
372 | } | |
373 | ||
0b2e8915 | 374 | spi_enable_chip(dws, 1); |
e24c7452 | 375 | |
9f14538e | 376 | if (dws->dma_mapped) { |
f89a6d8f | 377 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
9f14538e AS |
378 | if (ret < 0) |
379 | return ret; | |
380 | } | |
e24c7452 FT |
381 | |
382 | if (chip->poll_mode) | |
c22c62db | 383 | return poll_transfer(dws); |
e24c7452 | 384 | |
c22c62db | 385 | return 1; |
e24c7452 FT |
386 | } |
387 | ||
721483e2 | 388 | static void dw_spi_handle_err(struct spi_controller *master, |
ec37e8e1 | 389 | struct spi_message *msg) |
e24c7452 | 390 | { |
721483e2 | 391 | struct dw_spi *dws = spi_controller_get_devdata(master); |
e24c7452 | 392 | |
4d5ac1ed AS |
393 | if (dws->dma_mapped) |
394 | dws->dma_ops->dma_stop(dws); | |
395 | ||
c22c62db | 396 | spi_reset_chip(dws); |
e24c7452 FT |
397 | } |
398 | ||
399 | /* This may be called twice for each spi dev */ | |
400 | static int dw_spi_setup(struct spi_device *spi) | |
401 | { | |
402 | struct dw_spi_chip *chip_info = NULL; | |
403 | struct chip_data *chip; | |
404 | ||
e24c7452 FT |
405 | /* Only alloc on first setup */ |
406 | chip = spi_get_ctldata(spi); | |
407 | if (!chip) { | |
a97c883a | 408 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
e24c7452 FT |
409 | if (!chip) |
410 | return -ENOMEM; | |
43f627ac | 411 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
412 | } |
413 | ||
414 | /* | |
415 | * Protocol drivers may change the chip settings, so... | |
416 | * if chip_info exists, use it | |
417 | */ | |
418 | chip_info = spi->controller_data; | |
419 | ||
420 | /* chip_info doesn't always exist */ | |
421 | if (chip_info) { | |
422 | if (chip_info->cs_control) | |
423 | chip->cs_control = chip_info->cs_control; | |
424 | ||
425 | chip->poll_mode = chip_info->poll_mode; | |
426 | chip->type = chip_info->type; | |
e24c7452 FT |
427 | } |
428 | ||
6096828e | 429 | chip->tmode = SPI_TMOD_TR; |
c3ce15bf | 430 | |
e24c7452 FT |
431 | return 0; |
432 | } | |
433 | ||
a97c883a AL |
434 | static void dw_spi_cleanup(struct spi_device *spi) |
435 | { | |
436 | struct chip_data *chip = spi_get_ctldata(spi); | |
437 | ||
438 | kfree(chip); | |
439 | spi_set_ctldata(spi, NULL); | |
440 | } | |
441 | ||
e24c7452 | 442 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
30b4b703 | 443 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
e24c7452 | 444 | { |
45746e82 | 445 | spi_reset_chip(dws); |
c587b6fa FT |
446 | |
447 | /* | |
448 | * Try to detect the FIFO depth if not set by interface driver, | |
449 | * the depth could be from 2 to 256 from HW spec | |
450 | */ | |
451 | if (!dws->fifo_len) { | |
452 | u32 fifo; | |
fadcace7 | 453 | |
9d239d35 | 454 | for (fifo = 1; fifo < 256; fifo++) { |
dd114443 TT |
455 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
456 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
457 | break; |
458 | } | |
dd114443 | 459 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 460 | |
9d239d35 | 461 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
30b4b703 | 462 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
c587b6fa | 463 | } |
f2d70479 TS |
464 | |
465 | /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */ | |
466 | if (dws->cs_override) | |
467 | dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF); | |
e24c7452 FT |
468 | } |
469 | ||
04f421e7 | 470 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 | 471 | { |
721483e2 | 472 | struct spi_controller *master; |
e24c7452 FT |
473 | int ret; |
474 | ||
169f9aca AP |
475 | if (!dws) |
476 | return -EINVAL; | |
e24c7452 | 477 | |
04f421e7 BS |
478 | master = spi_alloc_master(dev, 0); |
479 | if (!master) | |
480 | return -ENOMEM; | |
e24c7452 FT |
481 | |
482 | dws->master = master; | |
483 | dws->type = SSI_MOTO_SPI; | |
e24c7452 | 484 | dws->dma_inited = 0; |
d7ef54ca | 485 | dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); |
19b61392 | 486 | spin_lock_init(&dws->buf_lock); |
e24c7452 | 487 | |
66b19d76 AB |
488 | spi_controller_set_devdata(master, dws); |
489 | ||
e70002c8 PR |
490 | ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), |
491 | master); | |
e24c7452 | 492 | if (ret < 0) { |
5f0966e6 | 493 | dev_err(dev, "can not get IRQ\n"); |
e24c7452 FT |
494 | goto err_free_master; |
495 | } | |
496 | ||
9400c41e | 497 | master->use_gpio_descriptors = true; |
c3ce15bf | 498 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
af060b3f | 499 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e24c7452 FT |
500 | master->bus_num = dws->bus_num; |
501 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 502 | master->setup = dw_spi_setup; |
a97c883a | 503 | master->cleanup = dw_spi_cleanup; |
c22c62db AS |
504 | master->set_cs = dw_spi_set_cs; |
505 | master->transfer_one = dw_spi_transfer_one; | |
506 | master->handle_err = dw_spi_handle_err; | |
765ee709 | 507 | master->max_speed_hz = dws->max_freq; |
9c6de47d | 508 | master->dev.of_node = dev->of_node; |
32215a6c | 509 | master->dev.fwnode = dev->fwnode; |
80b444e5 | 510 | master->flags = SPI_MASTER_GPIO_SS; |
1e695983 | 511 | master->auto_runtime_pm = true; |
e24c7452 | 512 | |
62dbbae4 AB |
513 | if (dws->set_cs) |
514 | master->set_cs = dws->set_cs; | |
515 | ||
e24c7452 | 516 | /* Basic HW init */ |
30b4b703 | 517 | spi_hw_init(dev, dws); |
e24c7452 | 518 | |
7063c0d9 FT |
519 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
520 | ret = dws->dma_ops->dma_init(dws); | |
521 | if (ret) { | |
3dbb3b98 | 522 | dev_warn(dev, "DMA init failed\n"); |
7063c0d9 | 523 | dws->dma_inited = 0; |
f89a6d8f AS |
524 | } else { |
525 | master->can_dma = dws->dma_ops->can_dma; | |
7063c0d9 FT |
526 | } |
527 | } | |
528 | ||
721483e2 | 529 | ret = devm_spi_register_controller(dev, master); |
e24c7452 FT |
530 | if (ret) { |
531 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 532 | goto err_dma_exit; |
e24c7452 FT |
533 | } |
534 | ||
53288fe9 | 535 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
536 | return 0; |
537 | ||
ec37e8e1 | 538 | err_dma_exit: |
7063c0d9 FT |
539 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
540 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 541 | spi_enable_chip(dws, 0); |
02f20387 | 542 | free_irq(dws->irq, master); |
e24c7452 | 543 | err_free_master: |
721483e2 | 544 | spi_controller_put(master); |
e24c7452 FT |
545 | return ret; |
546 | } | |
79290a2a | 547 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 548 | |
fd4a319b | 549 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 550 | { |
53288fe9 | 551 | dw_spi_debugfs_remove(dws); |
e24c7452 | 552 | |
7063c0d9 FT |
553 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
554 | dws->dma_ops->dma_exit(dws); | |
1cc3f141 AS |
555 | |
556 | spi_shutdown_chip(dws); | |
02f20387 AS |
557 | |
558 | free_irq(dws->irq, dws->master); | |
e24c7452 | 559 | } |
79290a2a | 560 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
561 | |
562 | int dw_spi_suspend_host(struct dw_spi *dws) | |
563 | { | |
1cc3f141 | 564 | int ret; |
e24c7452 | 565 | |
721483e2 | 566 | ret = spi_controller_suspend(dws->master); |
e24c7452 FT |
567 | if (ret) |
568 | return ret; | |
1cc3f141 AS |
569 | |
570 | spi_shutdown_chip(dws); | |
571 | return 0; | |
e24c7452 | 572 | } |
79290a2a | 573 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
574 | |
575 | int dw_spi_resume_host(struct dw_spi *dws) | |
576 | { | |
30b4b703 | 577 | spi_hw_init(&dws->master->dev, dws); |
7c5d8a24 | 578 | return spi_controller_resume(dws->master); |
e24c7452 | 579 | } |
79290a2a | 580 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
581 | |
582 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
583 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
584 | MODULE_LICENSE("GPL v2"); |