Commit | Line | Data |
---|---|---|
e24c7452 | 1 | /* |
ca632f55 | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
3 | * |
4 | * Copyright (c) 2009, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
e24c7452 FT |
14 | */ |
15 | ||
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/interrupt.h> | |
d7614de4 | 18 | #include <linux/module.h> |
e24c7452 FT |
19 | #include <linux/highmem.h> |
20 | #include <linux/delay.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
e24c7452 FT |
22 | #include <linux/spi/spi.h> |
23 | ||
ca632f55 | 24 | #include "spi-dw.h" |
568a60ed | 25 | |
e24c7452 FT |
26 | #ifdef CONFIG_DEBUG_FS |
27 | #include <linux/debugfs.h> | |
28 | #endif | |
29 | ||
e24c7452 FT |
30 | /* Slave spi_dev related */ |
31 | struct chip_data { | |
e24c7452 FT |
32 | u8 tmode; /* TR/TO/RO/EEPROM */ |
33 | u8 type; /* SPI/SSP/MicroWire */ | |
34 | ||
35 | u8 poll_mode; /* 1 means use poll mode */ | |
36 | ||
e24c7452 FT |
37 | u16 clk_div; /* baud rate divider */ |
38 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
39 | void (*cs_control)(u32 command); |
40 | }; | |
41 | ||
42 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 43 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
44 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
45 | size_t count, loff_t *ppos) | |
e24c7452 | 46 | { |
53288fe9 | 47 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
48 | char *buf; |
49 | u32 len = 0; | |
50 | ssize_t ret; | |
51 | ||
e24c7452 FT |
52 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
53 | if (!buf) | |
54 | return 0; | |
55 | ||
d1d6bd78 | 56 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
53288fe9 | 57 | "%s registers:\n", dev_name(&dws->master->dev)); |
d1d6bd78 | 58 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
e24c7452 | 59 | "=================================\n"); |
d1d6bd78 | 60 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 61 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
d1d6bd78 | 62 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 63 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
d1d6bd78 | 64 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 65 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
d1d6bd78 | 66 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 67 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
d1d6bd78 | 68 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 69 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
d1d6bd78 | 70 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 71 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
d1d6bd78 | 72 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 73 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
d1d6bd78 | 74 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 75 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
d1d6bd78 | 76 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 77 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
d1d6bd78 | 78 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 79 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
d1d6bd78 | 80 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 81 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
d1d6bd78 | 82 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 83 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
d1d6bd78 | 84 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 85 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
d1d6bd78 | 86 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 87 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
d1d6bd78 | 88 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 89 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
d1d6bd78 | 90 | len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, |
e24c7452 FT |
91 | "=================================\n"); |
92 | ||
53288fe9 | 93 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
94 | kfree(buf); |
95 | return ret; | |
96 | } | |
97 | ||
53288fe9 | 98 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 99 | .owner = THIS_MODULE, |
234e3405 | 100 | .open = simple_open, |
53288fe9 | 101 | .read = dw_spi_show_regs, |
6038f373 | 102 | .llseek = default_llseek, |
e24c7452 FT |
103 | }; |
104 | ||
53288fe9 | 105 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 106 | { |
e70002c8 | 107 | char name[32]; |
13288bdf | 108 | |
e70002c8 | 109 | snprintf(name, 32, "dw_spi%d", dws->master->bus_num); |
13288bdf | 110 | dws->debugfs = debugfs_create_dir(name, NULL); |
e24c7452 FT |
111 | if (!dws->debugfs) |
112 | return -ENOMEM; | |
113 | ||
114 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 115 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
116 | return 0; |
117 | } | |
118 | ||
53288fe9 | 119 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 120 | { |
fadcace7 | 121 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
122 | } |
123 | ||
124 | #else | |
53288fe9 | 125 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 126 | { |
20a588fc | 127 | return 0; |
e24c7452 FT |
128 | } |
129 | ||
53288fe9 | 130 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
131 | { |
132 | } | |
133 | #endif /* CONFIG_DEBUG_FS */ | |
134 | ||
c79bdbb4 | 135 | void dw_spi_set_cs(struct spi_device *spi, bool enable) |
c22c62db | 136 | { |
721483e2 | 137 | struct dw_spi *dws = spi_controller_get_devdata(spi->controller); |
c22c62db AS |
138 | struct chip_data *chip = spi_get_ctldata(spi); |
139 | ||
207cda93 | 140 | if (chip && chip->cs_control) |
6e0a32d6 | 141 | chip->cs_control(enable); |
c22c62db | 142 | |
6e0a32d6 | 143 | if (enable) |
c22c62db | 144 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); |
f2d70479 TS |
145 | else if (dws->cs_override) |
146 | dw_writel(dws, DW_SPI_SER, 0); | |
c22c62db | 147 | } |
c79bdbb4 | 148 | EXPORT_SYMBOL_GPL(dw_spi_set_cs); |
c22c62db | 149 | |
2ff271bf AD |
150 | /* Return the max entries we can fill into tx fifo */ |
151 | static inline u32 tx_max(struct dw_spi *dws) | |
152 | { | |
153 | u32 tx_left, tx_room, rxtx_gap; | |
154 | ||
155 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
dd114443 | 156 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
2ff271bf AD |
157 | |
158 | /* | |
159 | * Another concern is about the tx/rx mismatch, we | |
160 | * though to use (dws->fifo_len - rxflr - txflr) as | |
161 | * one maximum value for tx, but it doesn't cover the | |
162 | * data which is out of tx/rx fifo and inside the | |
163 | * shift registers. So a control from sw point of | |
164 | * view is taken. | |
165 | */ | |
166 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
167 | / dws->n_bytes; | |
168 | ||
169 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
170 | } | |
171 | ||
172 | /* Return the max entries we should read out of rx fifo */ | |
173 | static inline u32 rx_max(struct dw_spi *dws) | |
174 | { | |
175 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
176 | ||
dd114443 | 177 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
178 | } |
179 | ||
3b8a4dd3 | 180 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 181 | { |
2ff271bf | 182 | u32 max = tx_max(dws); |
de6efe0a | 183 | u16 txw = 0; |
e24c7452 | 184 | |
2ff271bf AD |
185 | while (max--) { |
186 | /* Set the tx word if the transfer's original "tx" is not null */ | |
187 | if (dws->tx_end - dws->len) { | |
188 | if (dws->n_bytes == 1) | |
189 | txw = *(u8 *)(dws->tx); | |
190 | else | |
191 | txw = *(u16 *)(dws->tx); | |
192 | } | |
c4fe57f7 | 193 | dw_write_io_reg(dws, DW_SPI_DR, txw); |
2ff271bf | 194 | dws->tx += dws->n_bytes; |
e24c7452 | 195 | } |
e24c7452 FT |
196 | } |
197 | ||
3b8a4dd3 | 198 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 199 | { |
2ff271bf | 200 | u32 max = rx_max(dws); |
de6efe0a | 201 | u16 rxw; |
e24c7452 | 202 | |
2ff271bf | 203 | while (max--) { |
c4fe57f7 | 204 | rxw = dw_read_io_reg(dws, DW_SPI_DR); |
de6efe0a FT |
205 | /* Care rx only if the transfer's original "rx" is not null */ |
206 | if (dws->rx_end - dws->len) { | |
207 | if (dws->n_bytes == 1) | |
208 | *(u8 *)(dws->rx) = rxw; | |
209 | else | |
210 | *(u16 *)(dws->rx) = rxw; | |
211 | } | |
212 | dws->rx += dws->n_bytes; | |
e24c7452 | 213 | } |
e24c7452 FT |
214 | } |
215 | ||
e24c7452 FT |
216 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
217 | { | |
45746e82 | 218 | spi_reset_chip(dws); |
e24c7452 FT |
219 | |
220 | dev_err(&dws->master->dev, "%s\n", msg); | |
c22c62db AS |
221 | dws->master->cur_msg->status = -EIO; |
222 | spi_finalize_current_transfer(dws->master); | |
e24c7452 FT |
223 | } |
224 | ||
e24c7452 FT |
225 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
226 | { | |
dd114443 | 227 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
e24c7452 | 228 | |
e24c7452 FT |
229 | /* Error handling */ |
230 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
dd114443 | 231 | dw_readl(dws, DW_SPI_ICR); |
3b8a4dd3 | 232 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
233 | return IRQ_HANDLED; |
234 | } | |
235 | ||
3b8a4dd3 AD |
236 | dw_reader(dws); |
237 | if (dws->rx_end == dws->rx) { | |
238 | spi_mask_intr(dws, SPI_INT_TXEI); | |
c22c62db | 239 | spi_finalize_current_transfer(dws->master); |
3b8a4dd3 AD |
240 | return IRQ_HANDLED; |
241 | } | |
552e4509 FT |
242 | if (irq_status & SPI_INT_TXEI) { |
243 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
244 | dw_writer(dws); |
245 | /* Enable TX irq always, it will be disabled when RX finished */ | |
246 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
247 | } |
248 | ||
e24c7452 FT |
249 | return IRQ_HANDLED; |
250 | } | |
251 | ||
252 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
253 | { | |
721483e2 JN |
254 | struct spi_controller *master = dev_id; |
255 | struct dw_spi *dws = spi_controller_get_devdata(master); | |
dd114443 | 256 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 257 | |
cbcc062a YW |
258 | if (!irq_status) |
259 | return IRQ_NONE; | |
e24c7452 | 260 | |
c22c62db | 261 | if (!master->cur_msg) { |
e24c7452 | 262 | spi_mask_intr(dws, SPI_INT_TXEI); |
e24c7452 FT |
263 | return IRQ_HANDLED; |
264 | } | |
265 | ||
266 | return dws->transfer_handler(dws); | |
267 | } | |
268 | ||
269 | /* Must be called inside pump_transfers() */ | |
c22c62db | 270 | static int poll_transfer(struct dw_spi *dws) |
e24c7452 | 271 | { |
2ff271bf AD |
272 | do { |
273 | dw_writer(dws); | |
de6efe0a | 274 | dw_reader(dws); |
2ff271bf AD |
275 | cpu_relax(); |
276 | } while (dws->rx_end > dws->rx); | |
e24c7452 | 277 | |
c22c62db | 278 | return 0; |
e24c7452 FT |
279 | } |
280 | ||
721483e2 | 281 | static int dw_spi_transfer_one(struct spi_controller *master, |
c22c62db | 282 | struct spi_device *spi, struct spi_transfer *transfer) |
e24c7452 | 283 | { |
721483e2 | 284 | struct dw_spi *dws = spi_controller_get_devdata(master); |
c22c62db | 285 | struct chip_data *chip = spi_get_ctldata(spi); |
e24c7452 | 286 | u8 imask = 0; |
ea11370f | 287 | u16 txlevel = 0; |
4adb1f8f | 288 | u32 cr0; |
9f14538e | 289 | int ret; |
e24c7452 | 290 | |
f89a6d8f | 291 | dws->dma_mapped = 0; |
e24c7452 | 292 | |
e24c7452 FT |
293 | dws->tx = (void *)transfer->tx_buf; |
294 | dws->tx_end = dws->tx + transfer->len; | |
295 | dws->rx = transfer->rx_buf; | |
296 | dws->rx_end = dws->rx + transfer->len; | |
c22c62db | 297 | dws->len = transfer->len; |
e24c7452 | 298 | |
0b2e8915 AS |
299 | spi_enable_chip(dws, 0); |
300 | ||
e24c7452 | 301 | /* Handle per transfer options for bpw and speed */ |
13b10301 MS |
302 | if (transfer->speed_hz != dws->current_freq) { |
303 | if (transfer->speed_hz != chip->speed_hz) { | |
304 | /* clk_div doesn't support odd number */ | |
3aef4632 | 305 | chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe; |
13b10301 MS |
306 | chip->speed_hz = transfer->speed_hz; |
307 | } | |
308 | dws->current_freq = transfer->speed_hz; | |
0ed36990 | 309 | spi_set_clk(dws, chip->clk_div); |
e24c7452 | 310 | } |
af060b3f SG |
311 | |
312 | dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); | |
313 | dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); | |
314 | ||
4adb1f8f | 315 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
0ed36990 JN |
316 | cr0 = (transfer->bits_per_word - 1) |
317 | | (chip->type << SPI_FRF_OFFSET) | |
e1bc2048 | 318 | | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) | |
319 | (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET)) | |
0ed36990 | 320 | | (chip->tmode << SPI_TMOD_OFFSET); |
e24c7452 | 321 | |
052dc7c4 GS |
322 | /* |
323 | * Adjust transfer mode if necessary. Requires platform dependent | |
324 | * chipselect mechanism. | |
325 | */ | |
c22c62db | 326 | if (chip->cs_control) { |
052dc7c4 | 327 | if (dws->rx && dws->tx) |
e3e55ff5 | 328 | chip->tmode = SPI_TMOD_TR; |
052dc7c4 | 329 | else if (dws->rx) |
e3e55ff5 | 330 | chip->tmode = SPI_TMOD_RO; |
052dc7c4 | 331 | else |
e3e55ff5 | 332 | chip->tmode = SPI_TMOD_TO; |
052dc7c4 | 333 | |
e3e55ff5 | 334 | cr0 &= ~SPI_TMOD_MASK; |
052dc7c4 GS |
335 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
336 | } | |
337 | ||
dd114443 | 338 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
0b2e8915 | 339 | |
e24c7452 | 340 | /* Check if current transfer is a DMA transaction */ |
f89a6d8f AS |
341 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
342 | dws->dma_mapped = master->cur_msg_mapped; | |
e24c7452 | 343 | |
0b2e8915 AS |
344 | /* For poll mode just disable all interrupts */ |
345 | spi_mask_intr(dws, 0xff); | |
346 | ||
552e4509 FT |
347 | /* |
348 | * Interrupt mode | |
349 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
350 | */ | |
9f14538e | 351 | if (dws->dma_mapped) { |
f89a6d8f | 352 | ret = dws->dma_ops->dma_setup(dws, transfer); |
9f14538e AS |
353 | if (ret < 0) { |
354 | spi_enable_chip(dws, 1); | |
355 | return ret; | |
356 | } | |
357 | } else if (!chip->poll_mode) { | |
ea11370f | 358 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
dd114443 | 359 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
552e4509 | 360 | |
0b2e8915 | 361 | /* Set the interrupt mask */ |
fadcace7 JH |
362 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
363 | SPI_INT_RXUI | SPI_INT_RXOI; | |
0b2e8915 AS |
364 | spi_umask_intr(dws, imask); |
365 | ||
e24c7452 FT |
366 | dws->transfer_handler = interrupt_transfer; |
367 | } | |
368 | ||
0b2e8915 | 369 | spi_enable_chip(dws, 1); |
e24c7452 | 370 | |
9f14538e | 371 | if (dws->dma_mapped) { |
f89a6d8f | 372 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
9f14538e AS |
373 | if (ret < 0) |
374 | return ret; | |
375 | } | |
e24c7452 FT |
376 | |
377 | if (chip->poll_mode) | |
c22c62db | 378 | return poll_transfer(dws); |
e24c7452 | 379 | |
c22c62db | 380 | return 1; |
e24c7452 FT |
381 | } |
382 | ||
721483e2 | 383 | static void dw_spi_handle_err(struct spi_controller *master, |
ec37e8e1 | 384 | struct spi_message *msg) |
e24c7452 | 385 | { |
721483e2 | 386 | struct dw_spi *dws = spi_controller_get_devdata(master); |
e24c7452 | 387 | |
4d5ac1ed AS |
388 | if (dws->dma_mapped) |
389 | dws->dma_ops->dma_stop(dws); | |
390 | ||
c22c62db | 391 | spi_reset_chip(dws); |
e24c7452 FT |
392 | } |
393 | ||
394 | /* This may be called twice for each spi dev */ | |
395 | static int dw_spi_setup(struct spi_device *spi) | |
396 | { | |
397 | struct dw_spi_chip *chip_info = NULL; | |
398 | struct chip_data *chip; | |
399 | ||
e24c7452 FT |
400 | /* Only alloc on first setup */ |
401 | chip = spi_get_ctldata(spi); | |
402 | if (!chip) { | |
a97c883a | 403 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
e24c7452 FT |
404 | if (!chip) |
405 | return -ENOMEM; | |
43f627ac | 406 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
407 | } |
408 | ||
409 | /* | |
410 | * Protocol drivers may change the chip settings, so... | |
411 | * if chip_info exists, use it | |
412 | */ | |
413 | chip_info = spi->controller_data; | |
414 | ||
415 | /* chip_info doesn't always exist */ | |
416 | if (chip_info) { | |
417 | if (chip_info->cs_control) | |
418 | chip->cs_control = chip_info->cs_control; | |
419 | ||
420 | chip->poll_mode = chip_info->poll_mode; | |
421 | chip->type = chip_info->type; | |
e24c7452 FT |
422 | } |
423 | ||
6096828e | 424 | chip->tmode = SPI_TMOD_TR; |
c3ce15bf | 425 | |
e24c7452 FT |
426 | return 0; |
427 | } | |
428 | ||
a97c883a AL |
429 | static void dw_spi_cleanup(struct spi_device *spi) |
430 | { | |
431 | struct chip_data *chip = spi_get_ctldata(spi); | |
432 | ||
433 | kfree(chip); | |
434 | spi_set_ctldata(spi, NULL); | |
435 | } | |
436 | ||
e24c7452 | 437 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
30b4b703 | 438 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
e24c7452 | 439 | { |
45746e82 | 440 | spi_reset_chip(dws); |
c587b6fa FT |
441 | |
442 | /* | |
443 | * Try to detect the FIFO depth if not set by interface driver, | |
444 | * the depth could be from 2 to 256 from HW spec | |
445 | */ | |
446 | if (!dws->fifo_len) { | |
447 | u32 fifo; | |
fadcace7 | 448 | |
9d239d35 | 449 | for (fifo = 1; fifo < 256; fifo++) { |
dd114443 TT |
450 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
451 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
452 | break; |
453 | } | |
dd114443 | 454 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 455 | |
9d239d35 | 456 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
30b4b703 | 457 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
c587b6fa | 458 | } |
f2d70479 TS |
459 | |
460 | /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */ | |
461 | if (dws->cs_override) | |
462 | dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF); | |
e24c7452 FT |
463 | } |
464 | ||
04f421e7 | 465 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 | 466 | { |
721483e2 | 467 | struct spi_controller *master; |
e24c7452 FT |
468 | int ret; |
469 | ||
470 | BUG_ON(dws == NULL); | |
471 | ||
04f421e7 BS |
472 | master = spi_alloc_master(dev, 0); |
473 | if (!master) | |
474 | return -ENOMEM; | |
e24c7452 FT |
475 | |
476 | dws->master = master; | |
477 | dws->type = SSI_MOTO_SPI; | |
e24c7452 | 478 | dws->dma_inited = 0; |
d7ef54ca | 479 | dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); |
e24c7452 | 480 | |
66b19d76 AB |
481 | spi_controller_set_devdata(master, dws); |
482 | ||
e70002c8 PR |
483 | ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), |
484 | master); | |
e24c7452 | 485 | if (ret < 0) { |
5f0966e6 | 486 | dev_err(dev, "can not get IRQ\n"); |
e24c7452 FT |
487 | goto err_free_master; |
488 | } | |
489 | ||
9400c41e | 490 | master->use_gpio_descriptors = true; |
c3ce15bf | 491 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
af060b3f | 492 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e24c7452 FT |
493 | master->bus_num = dws->bus_num; |
494 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 495 | master->setup = dw_spi_setup; |
a97c883a | 496 | master->cleanup = dw_spi_cleanup; |
c22c62db AS |
497 | master->set_cs = dw_spi_set_cs; |
498 | master->transfer_one = dw_spi_transfer_one; | |
499 | master->handle_err = dw_spi_handle_err; | |
765ee709 | 500 | master->max_speed_hz = dws->max_freq; |
9c6de47d | 501 | master->dev.of_node = dev->of_node; |
32215a6c | 502 | master->dev.fwnode = dev->fwnode; |
80b444e5 | 503 | master->flags = SPI_MASTER_GPIO_SS; |
e24c7452 | 504 | |
62dbbae4 AB |
505 | if (dws->set_cs) |
506 | master->set_cs = dws->set_cs; | |
507 | ||
e24c7452 | 508 | /* Basic HW init */ |
30b4b703 | 509 | spi_hw_init(dev, dws); |
e24c7452 | 510 | |
7063c0d9 FT |
511 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
512 | ret = dws->dma_ops->dma_init(dws); | |
513 | if (ret) { | |
3dbb3b98 | 514 | dev_warn(dev, "DMA init failed\n"); |
7063c0d9 | 515 | dws->dma_inited = 0; |
f89a6d8f AS |
516 | } else { |
517 | master->can_dma = dws->dma_ops->can_dma; | |
7063c0d9 FT |
518 | } |
519 | } | |
520 | ||
721483e2 | 521 | ret = devm_spi_register_controller(dev, master); |
e24c7452 FT |
522 | if (ret) { |
523 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 524 | goto err_dma_exit; |
e24c7452 FT |
525 | } |
526 | ||
53288fe9 | 527 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
528 | return 0; |
529 | ||
ec37e8e1 | 530 | err_dma_exit: |
7063c0d9 FT |
531 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
532 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 533 | spi_enable_chip(dws, 0); |
02f20387 | 534 | free_irq(dws->irq, master); |
e24c7452 | 535 | err_free_master: |
721483e2 | 536 | spi_controller_put(master); |
e24c7452 FT |
537 | return ret; |
538 | } | |
79290a2a | 539 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 540 | |
fd4a319b | 541 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 542 | { |
53288fe9 | 543 | dw_spi_debugfs_remove(dws); |
e24c7452 | 544 | |
7063c0d9 FT |
545 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
546 | dws->dma_ops->dma_exit(dws); | |
1cc3f141 AS |
547 | |
548 | spi_shutdown_chip(dws); | |
02f20387 AS |
549 | |
550 | free_irq(dws->irq, dws->master); | |
e24c7452 | 551 | } |
79290a2a | 552 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
553 | |
554 | int dw_spi_suspend_host(struct dw_spi *dws) | |
555 | { | |
1cc3f141 | 556 | int ret; |
e24c7452 | 557 | |
721483e2 | 558 | ret = spi_controller_suspend(dws->master); |
e24c7452 FT |
559 | if (ret) |
560 | return ret; | |
1cc3f141 AS |
561 | |
562 | spi_shutdown_chip(dws); | |
563 | return 0; | |
e24c7452 | 564 | } |
79290a2a | 565 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
566 | |
567 | int dw_spi_resume_host(struct dw_spi *dws) | |
568 | { | |
30b4b703 | 569 | spi_hw_init(&dws->master->dev, dws); |
7c5d8a24 | 570 | return spi_controller_resume(dws->master); |
e24c7452 | 571 | } |
79290a2a | 572 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
573 | |
574 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
575 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
576 | MODULE_LICENSE("GPL v2"); |