Commit | Line | Data |
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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e24c7452 | 2 | /* |
ca632f55 | 3 | * PCI interface driver for DW SPI Core |
e24c7452 | 4 | * |
5dc23c44 | 5 | * Copyright (c) 2009, 2014 Intel Corporation. |
e24c7452 FT |
6 | */ |
7 | ||
e24c7452 | 8 | #include <linux/pci.h> |
c8169580 | 9 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 10 | #include <linux/slab.h> |
e24c7452 | 11 | #include <linux/spi/spi.h> |
d7614de4 | 12 | #include <linux/module.h> |
e24c7452 | 13 | |
ca632f55 | 14 | #include "spi-dw.h" |
568a60ed | 15 | |
e24c7452 FT |
16 | #define DRIVER_NAME "dw_spi_pci" |
17 | ||
6c710c0c SS |
18 | /* HW info for MRST Clk Control Unit, 32b reg per controller */ |
19 | #define MRST_SPI_CLK_BASE 100000000 /* 100m */ | |
20 | #define MRST_CLK_SPI_REG 0xff11d86c | |
21 | #define CLK_SPI_BDIV_OFFSET 0 | |
22 | #define CLK_SPI_BDIV_MASK 0x00000007 | |
23 | #define CLK_SPI_CDIV_OFFSET 9 | |
24 | #define CLK_SPI_CDIV_MASK 0x00000e00 | |
25 | #define CLK_SPI_DISABLE_OFFSET 8 | |
26 | ||
725b0e3e | 27 | struct dw_spi_pci_desc { |
c95791b6 | 28 | int (*setup)(struct dw_spi *); |
d58cf5ff AS |
29 | u16 num_cs; |
30 | u16 bus_num; | |
52718908 | 31 | u32 max_freq; |
c95791b6 AS |
32 | }; |
33 | ||
725b0e3e | 34 | static int dw_spi_pci_mid_init(struct dw_spi *dws) |
6c710c0c SS |
35 | { |
36 | void __iomem *clk_reg; | |
37 | u32 clk_cdiv; | |
38 | ||
39 | clk_reg = ioremap(MRST_CLK_SPI_REG, 16); | |
40 | if (!clk_reg) | |
41 | return -ENOMEM; | |
42 | ||
43 | /* Get SPI controller operating freq info */ | |
44 | clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32)); | |
45 | clk_cdiv &= CLK_SPI_CDIV_MASK; | |
46 | clk_cdiv >>= CLK_SPI_CDIV_OFFSET; | |
47 | dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1); | |
48 | ||
49 | iounmap(clk_reg); | |
50 | ||
57784411 | 51 | dw_spi_dma_setup_mfld(dws); |
6c710c0c SS |
52 | |
53 | return 0; | |
54 | } | |
55 | ||
725b0e3e | 56 | static int dw_spi_pci_generic_init(struct dw_spi *dws) |
6c710c0c | 57 | { |
57784411 | 58 | dw_spi_dma_setup_generic(dws); |
6c710c0c SS |
59 | |
60 | return 0; | |
61 | } | |
62 | ||
725b0e3e SS |
63 | static struct dw_spi_pci_desc dw_spi_pci_mid_desc_1 = { |
64 | .setup = dw_spi_pci_mid_init, | |
307ed83c | 65 | .num_cs = 5, |
d58cf5ff AS |
66 | .bus_num = 0, |
67 | }; | |
68 | ||
725b0e3e SS |
69 | static struct dw_spi_pci_desc dw_spi_pci_mid_desc_2 = { |
70 | .setup = dw_spi_pci_mid_init, | |
307ed83c | 71 | .num_cs = 2, |
d58cf5ff | 72 | .bus_num = 1, |
c95791b6 AS |
73 | }; |
74 | ||
725b0e3e SS |
75 | static struct dw_spi_pci_desc dw_spi_pci_ehl_desc = { |
76 | .setup = dw_spi_pci_generic_init, | |
c97905ca | 77 | .num_cs = 2, |
52718908 JN |
78 | .bus_num = -1, |
79 | .max_freq = 100000000, | |
80 | }; | |
81 | ||
725b0e3e | 82 | static int dw_spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
e24c7452 | 83 | { |
725b0e3e | 84 | struct dw_spi_pci_desc *desc = (struct dw_spi_pci_desc *)ent->driver_data; |
e24c7452 FT |
85 | struct dw_spi *dws; |
86 | int pci_bar = 0; | |
87 | int ret; | |
88 | ||
04f421e7 | 89 | ret = pcim_enable_device(pdev); |
e24c7452 FT |
90 | if (ret) |
91 | return ret; | |
92 | ||
1c2df965 AS |
93 | dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL); |
94 | if (!dws) | |
04f421e7 | 95 | return -ENOMEM; |
e24c7452 | 96 | |
e24c7452 FT |
97 | /* Get basic io resource and map it */ |
98 | dws->paddr = pci_resource_start(pdev, pci_bar); | |
8f5c285f | 99 | pci_set_master(pdev); |
e24c7452 | 100 | |
ceb86de9 | 101 | ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev)); |
e24c7452 | 102 | if (ret) |
04f421e7 | 103 | return ret; |
e24c7452 | 104 | |
8f5c285f FB |
105 | ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
106 | if (ret < 0) | |
107 | return ret; | |
108 | ||
c9d5d6fe | 109 | dws->regs = pcim_iomap_table(pdev)[pci_bar]; |
8f5c285f | 110 | dws->irq = pci_irq_vector(pdev, 0); |
7063c0d9 FT |
111 | |
112 | /* | |
3208a1cc | 113 | * Specific handling for platforms, like dma setup, |
7063c0d9 FT |
114 | * clock rate, FIFO depth. |
115 | */ | |
d58cf5ff | 116 | if (desc) { |
d9c14743 AS |
117 | dws->num_cs = desc->num_cs; |
118 | dws->bus_num = desc->bus_num; | |
52718908 | 119 | dws->max_freq = desc->max_freq; |
d9c14743 | 120 | |
d58cf5ff AS |
121 | if (desc->setup) { |
122 | ret = desc->setup(dws); | |
123 | if (ret) | |
9599f341 | 124 | goto err_free_irq_vectors; |
d58cf5ff | 125 | } |
d58cf5ff | 126 | } else { |
9599f341 JF |
127 | ret = -ENODEV; |
128 | goto err_free_irq_vectors; | |
7063c0d9 | 129 | } |
e24c7452 | 130 | |
04f421e7 | 131 | ret = dw_spi_add_host(&pdev->dev, dws); |
9599f341 JF |
132 | if (ret) |
133 | goto err_free_irq_vectors; | |
e24c7452 FT |
134 | |
135 | /* PCI hook and SPI hook use the same drv data */ | |
1c2df965 | 136 | pci_set_drvdata(pdev, dws); |
e24c7452 | 137 | |
fcf0af44 AS |
138 | dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n", |
139 | pdev->vendor, pdev->device); | |
140 | ||
c8169580 RT |
141 | pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); |
142 | pm_runtime_use_autosuspend(&pdev->dev); | |
143 | pm_runtime_put_autosuspend(&pdev->dev); | |
144 | pm_runtime_allow(&pdev->dev); | |
145 | ||
04f421e7 | 146 | return 0; |
9599f341 JF |
147 | |
148 | err_free_irq_vectors: | |
149 | pci_free_irq_vectors(pdev); | |
150 | return ret; | |
e24c7452 FT |
151 | } |
152 | ||
725b0e3e | 153 | static void dw_spi_pci_remove(struct pci_dev *pdev) |
e24c7452 | 154 | { |
1c2df965 | 155 | struct dw_spi *dws = pci_get_drvdata(pdev); |
e24c7452 | 156 | |
c8169580 RT |
157 | pm_runtime_forbid(&pdev->dev); |
158 | pm_runtime_get_noresume(&pdev->dev); | |
159 | ||
1c2df965 | 160 | dw_spi_remove_host(dws); |
8f5c285f | 161 | pci_free_irq_vectors(pdev); |
e24c7452 FT |
162 | } |
163 | ||
35f2d413 | 164 | #ifdef CONFIG_PM_SLEEP |
725b0e3e | 165 | static int dw_spi_pci_suspend(struct device *dev) |
e24c7452 | 166 | { |
2a3b6f7b | 167 | struct dw_spi *dws = dev_get_drvdata(dev); |
e24c7452 | 168 | |
1c2df965 | 169 | return dw_spi_suspend_host(dws); |
e24c7452 FT |
170 | } |
171 | ||
725b0e3e | 172 | static int dw_spi_pci_resume(struct device *dev) |
e24c7452 | 173 | { |
2a3b6f7b | 174 | struct dw_spi *dws = dev_get_drvdata(dev); |
e24c7452 | 175 | |
1c2df965 | 176 | return dw_spi_resume_host(dws); |
e24c7452 | 177 | } |
e24c7452 FT |
178 | #endif |
179 | ||
725b0e3e | 180 | static SIMPLE_DEV_PM_OPS(dw_spi_pci_pm_ops, dw_spi_pci_suspend, dw_spi_pci_resume); |
35f2d413 | 181 | |
725b0e3e | 182 | static const struct pci_device_id dw_spi_pci_ids[] = { |
7063c0d9 | 183 | /* Intel MID platform SPI controller 0 */ |
d58cf5ff AS |
184 | /* |
185 | * The access to the device 8086:0801 is disabled by HW, since it's | |
186 | * exclusively used by SCU to communicate with MSIC. | |
187 | */ | |
188 | /* Intel MID platform SPI controller 1 */ | |
725b0e3e | 189 | { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&dw_spi_pci_mid_desc_1}, |
d58cf5ff | 190 | /* Intel MID platform SPI controller 2 */ |
725b0e3e | 191 | { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&dw_spi_pci_mid_desc_2}, |
52718908 | 192 | /* Intel Elkhart Lake PSE SPI controllers */ |
725b0e3e SS |
193 | { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, |
194 | { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, | |
195 | { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, | |
196 | { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&dw_spi_pci_ehl_desc}, | |
e24c7452 FT |
197 | {}, |
198 | }; | |
725b0e3e | 199 | MODULE_DEVICE_TABLE(pci, dw_spi_pci_ids); |
e24c7452 | 200 | |
725b0e3e | 201 | static struct pci_driver dw_spi_pci_driver = { |
e24c7452 | 202 | .name = DRIVER_NAME, |
725b0e3e SS |
203 | .id_table = dw_spi_pci_ids, |
204 | .probe = dw_spi_pci_probe, | |
205 | .remove = dw_spi_pci_remove, | |
35f2d413 | 206 | .driver = { |
725b0e3e | 207 | .pm = &dw_spi_pci_pm_ops, |
35f2d413 | 208 | }, |
e24c7452 | 209 | }; |
725b0e3e | 210 | module_pci_driver(dw_spi_pci_driver); |
e24c7452 FT |
211 | |
212 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
213 | MODULE_DESCRIPTION("PCI interface driver for DW SPI Core"); | |
214 | MODULE_LICENSE("GPL v2"); | |
a62bacba | 215 | MODULE_IMPORT_NS(SPI_DW_CORE); |