[linux-2.6-block.git] / drivers / spi / spi-dw-mmio.c

/*
 * Memory-mapped interface driver for DW SPI Core
 *
 * Copyright (c) 2010, Octasic semiconductor.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/scatterlist.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/acpi.h>
#include <linux/property.h>
#include <linux/regmap.h>

#include "spi-dw.h"

#define DRIVER_NAME "dw_spi_mmio"

struct dw_spi_mmio {
	struct dw_spi  dws;
	struct clk     *clk;
	struct clk     *pclk;
	void           *priv;
};

#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL	0x24
#define OCELOT_IF_SI_OWNER_OFFSET		4
#define JAGUAR2_IF_SI_OWNER_OFFSET		6
#define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
#define MSCC_IF_SI_OWNER_SISL			0
#define MSCC_IF_SI_OWNER_SIBM			1
#define MSCC_IF_SI_OWNER_SIMC			2

#define MSCC_SPI_MST_SW_MODE			0x14
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)
#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)

struct dw_spi_mscc {
	struct regmap       *syscon;
	void __iomem        *spi_mst;
};

/*
 * The Designware SPI controller (referred to as master in the documentation)
 * automatically deasserts chip select when the tx fifo is empty. The chip
 * selects then needs to be either driven as GPIOs or, for the first 4 using the
 * the SPI boot controller registers. the final chip select is an OR gate
 * between the Designware SPI controller and the SPI boot controller.
 */
static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	u32 cs = spi->chip_select;

	if (cs < 4) {
		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;

		if (!enable)
			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));

		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	}

	dw_spi_set_cs(spi, enable);
}

static int dw_spi_mscc_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio,
			    const char *cpu_syscon, u32 if_si_owner_offset)
{
	struct dw_spi_mscc *dwsmscc;
	struct resource *res;

	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	if (!dwsmscc)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dwsmscc->spi_mst)) {
		dev_err(&pdev->dev, "SPI_MST region map failed\n");
		return PTR_ERR(dwsmscc->spi_mst);
	}

	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
	if (IS_ERR(dwsmscc->syscon))
		return PTR_ERR(dwsmscc->syscon);

	/* Deassert all CS */
	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);

	/* Select the owner of the SI interface */
	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
			   MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
			   MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);

	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	dwsmmio->priv = dwsmscc;

	return 0;
}

static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
				OCELOT_IF_SI_OWNER_OFFSET);
}

static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
				    struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
				JAGUAR2_IF_SI_OWNER_OFFSET);
}

static int dw_spi_alpine_init(struct platform_device *pdev,
			      struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.cs_override = 1;

	return 0;
}

static int dw_spi_mmio_probe(struct platform_device *pdev)
{
	int (*init_func)(struct platform_device *pdev,
			 struct dw_spi_mmio *dwsmmio);
	struct dw_spi_mmio *dwsmmio;
	struct dw_spi *dws;
	struct resource *mem;
	int ret;
	int num_cs;

	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
			GFP_KERNEL);
	if (!dwsmmio)
		return -ENOMEM;

	dws = &dwsmmio->dws;

	/* Get basic io resource and map it */
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	dws->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(dws->regs)) {
		dev_err(&pdev->dev, "SPI region map failed\n");
		return PTR_ERR(dws->regs);
	}

	dws->irq = platform_get_irq(pdev, 0);
	if (dws->irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return dws->irq; /* -ENXIO */
	}

	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(dwsmmio->clk))
		return PTR_ERR(dwsmmio->clk);
	ret = clk_prepare_enable(dwsmmio->clk);
	if (ret)
		return ret;

	/* Optional clock needed to access the registers */
	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
	if (IS_ERR(dwsmmio->pclk))
		return PTR_ERR(dwsmmio->pclk);
	ret = clk_prepare_enable(dwsmmio->pclk);
	if (ret)
		goto out_clk;

	dws->bus_num = pdev->id;

	dws->max_freq = clk_get_rate(dwsmmio->clk);

	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);

	num_cs = 4;

	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);

	dws->num_cs = num_cs;

	init_func = device_get_match_data(&pdev->dev);
	if (init_func) {
		ret = init_func(pdev, dwsmmio);
		if (ret)
			goto out;
	}

	ret = dw_spi_add_host(&pdev->dev, dws);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, dwsmmio);
	return 0;

out:
	clk_disable_unprepare(dwsmmio->pclk);
out_clk:
	clk_disable_unprepare(dwsmmio->clk);
	return ret;
}

static int dw_spi_mmio_remove(struct platform_device *pdev)
{
	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);

	dw_spi_remove_host(&dwsmmio->dws);
	clk_disable_unprepare(dwsmmio->pclk);
	clk_disable_unprepare(dwsmmio->clk);

	return 0;
}

static const struct of_device_id dw_spi_mmio_of_match[] = {
	{ .compatible = "snps,dw-apb-ssi", },
	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
	{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);

static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	{"HISI0173", 0},
	{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);

static struct platform_driver dw_spi_mmio_driver = {
	.probe		= dw_spi_mmio_probe,
	.remove		= dw_spi_mmio_remove,
	.driver		= {
		.name	= DRIVER_NAME,
		.of_match_table = dw_spi_mmio_of_match,
		.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
	},
};
module_platform_driver(dw_spi_mmio_driver);

MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f7b6fd6d	1	/*
ca632f55	2	* Memory-mapped interface driver for DW SPI Core
f7b6fd6d JHD	3	*
	4	* Copyright (c) 2010, Octasic semiconductor.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
50c01fc3	12	#include <linux/err.h>
f7b6fd6d JHD	13	#include <linux/interrupt.h>
f7b6fd6d JHD	14	#include <linux/platform_device.h>
5a0e3ad6	15	#include <linux/slab.h>
f7b6fd6d	16	#include <linux/spi/spi.h>
568a60ed	17	#include <linux/scatterlist.h>
c2c25cc3	18	#include <linux/mfd/syscon.h>
d7614de4	19	#include <linux/module.h>
22dae17e	20	#include <linux/of.h>
22dae17e	21	#include <linux/of_platform.h>
32215a6c	22	#include <linux/acpi.h>
9899995e	23	#include <linux/property.h>
c2c25cc3	24	#include <linux/regmap.h>
568a60ed	25
ca632f55	26	#include "spi-dw.h"
f7b6fd6d JHD	27
	28	#define DRIVER_NAME "dw_spi_mmio"
	29
	30	struct dw_spi_mmio {
0a4c1d7d JHD	31	struct dw_spi dws;
0a4c1d7d JHD	32	struct clk *clk;
560ee7e9	33	struct clk *pclk;
c2c25cc3	34	void *priv;
f7b6fd6d JHD	35	};
f7b6fd6d JHD	36
c2c25cc3	37	#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
c2c25cc3	38	#define OCELOT_IF_SI_OWNER_OFFSET 4
be17ee0d	39	#define JAGUAR2_IF_SI_OWNER_OFFSET 6
c1d8b082	40	#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
c2c25cc3 AB	41	#define MSCC_IF_SI_OWNER_SISL 0
	42	#define MSCC_IF_SI_OWNER_SIBM 1
	43	#define MSCC_IF_SI_OWNER_SIMC 2
	44
	45	#define MSCC_SPI_MST_SW_MODE 0x14
	46	#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
	47	#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
	48
	49	struct dw_spi_mscc {
	50	struct regmap *syscon;
	51	void __iomem *spi_mst;
	52	};
	53
	54	/*
	55	* The Designware SPI controller (referred to as master in the documentation)
	56	* automatically deasserts chip select when the tx fifo is empty. The chip
	57	* selects then needs to be either driven as GPIOs or, for the first 4 using the
	58	* the SPI boot controller registers. the final chip select is an OR gate
	59	* between the Designware SPI controller and the SPI boot controller.
	60	*/
	61	static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
	62	{
	63	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	64	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	65	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	66	u32 cs = spi->chip_select;
	67
	68	if (cs < 4) {
	69	u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
	70
	71	if (!enable)
	72	sw_mode \|= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
	73
	74	writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	75	}
	76
	77	dw_spi_set_cs(spi, enable);
	78	}
	79
	80	static int dw_spi_mscc_init(struct platform_device *pdev,
be17ee0d AB	81	struct dw_spi_mmio *dwsmmio,
be17ee0d AB	82	const char *cpu_syscon, u32 if_si_owner_offset)
c2c25cc3 AB	83	{
	84	struct dw_spi_mscc *dwsmscc;
	85	struct resource *res;
	86
	87	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	88	if (!dwsmscc)
	89	return -ENOMEM;
	90
	91	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	92	dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
	93	if (IS_ERR(dwsmscc->spi_mst)) {
	94	dev_err(&pdev->dev, "SPI_MST region map failed\n");
	95	return PTR_ERR(dwsmscc->spi_mst);
	96	}
	97
be17ee0d	98	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
c2c25cc3 AB	99	if (IS_ERR(dwsmscc->syscon))
	100	return PTR_ERR(dwsmscc->syscon);
	101
	102	/* Deassert all CS */
	103	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	104
	105	/* Select the owner of the SI interface */
	106	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
c1d8b082	107	MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
be17ee0d	108	MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
c2c25cc3 AB	109
	110	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	111	dwsmmio->priv = dwsmscc;
	112
	113	return 0;
	114	}
	115
be17ee0d AB	116	static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
	117	struct dw_spi_mmio *dwsmmio)
	118	{
	119	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
	120	OCELOT_IF_SI_OWNER_OFFSET);
	121	}
	122
	123	static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
	124	struct dw_spi_mmio *dwsmmio)
	125	{
	126	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
	127	JAGUAR2_IF_SI_OWNER_OFFSET);
	128	}
	129
f2d70479 TS	130	static int dw_spi_alpine_init(struct platform_device *pdev,
	131	struct dw_spi_mmio *dwsmmio)
	132	{
	133	dwsmmio->dws.cs_override = 1;
	134
	135	return 0;
	136	}
	137
fd4a319b	138	static int dw_spi_mmio_probe(struct platform_device *pdev)
f7b6fd6d	139	{
c2c25cc3 AB	140	int (init_func)(struct platform_device pdev,
c2c25cc3 AB	141	struct dw_spi_mmio *dwsmmio);
f7b6fd6d JHD	142	struct dw_spi_mmio *dwsmmio;
f7b6fd6d JHD	143	struct dw_spi *dws;
04f421e7	144	struct resource *mem;
f7b6fd6d	145	int ret;
22dae17e	146	int num_cs;
f7b6fd6d	147
04f421e7 BS	148	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
	149	GFP_KERNEL);
	150	if (!dwsmmio)
	151	return -ENOMEM;
f7b6fd6d JHD	152
	153	dws = &dwsmmio->dws;
	154
	155	/* Get basic io resource and map it */
	156	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
04f421e7 BS	157	dws->regs = devm_ioremap_resource(&pdev->dev, mem);
	158	if (IS_ERR(dws->regs)) {
	159	dev_err(&pdev->dev, "SPI region map failed\n");
	160	return PTR_ERR(dws->regs);
f7b6fd6d JHD	161	}
	162
	163	dws->irq = platform_get_irq(pdev, 0);
	164	if (dws->irq < 0) {
	165	dev_err(&pdev->dev, "no irq resource?\n");
04f421e7	166	return dws->irq; /* -ENXIO */
f7b6fd6d JHD	167	}
f7b6fd6d JHD	168
04f421e7 BS	169	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	170	if (IS_ERR(dwsmmio->clk))
	171	return PTR_ERR(dwsmmio->clk);
020fe3fe	172	ret = clk_prepare_enable(dwsmmio->clk);
04f421e7 BS	173	if (ret)
04f421e7 BS	174	return ret;
f7b6fd6d	175
560ee7e9 PE	176	/* Optional clock needed to access the registers */
	177	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
	178	if (IS_ERR(dwsmmio->pclk))
	179	return PTR_ERR(dwsmmio->pclk);
	180	ret = clk_prepare_enable(dwsmmio->pclk);
	181	if (ret)
	182	goto out_clk;
	183
2418991e	184	dws->bus_num = pdev->id;
22dae17e	185
f7b6fd6d JHD	186	dws->max_freq = clk_get_rate(dwsmmio->clk);
f7b6fd6d JHD	187
9899995e	188	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
c4fe57f7	189
22dae17e ST	190	num_cs = 4;
22dae17e ST	191
9899995e	192	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
22dae17e ST	193
	194	dws->num_cs = num_cs;
	195
c2c25cc3 AB	196	init_func = device_get_match_data(&pdev->dev);
	197	if (init_func) {
	198	ret = init_func(pdev, dwsmmio);
	199	if (ret)
	200	goto out;
	201	}
	202
04f421e7	203	ret = dw_spi_add_host(&pdev->dev, dws);
f7b6fd6d	204	if (ret)
04f421e7	205	goto out;
f7b6fd6d JHD	206
	207	platform_set_drvdata(pdev, dwsmmio);
	208	return 0;
	209
04f421e7	210	out:
560ee7e9 PE	211	clk_disable_unprepare(dwsmmio->pclk);
560ee7e9 PE	212	out_clk:
020fe3fe	213	clk_disable_unprepare(dwsmmio->clk);
f7b6fd6d JHD	214	return ret;
	215	}
	216
fd4a319b	217	static int dw_spi_mmio_remove(struct platform_device *pdev)
f7b6fd6d JHD	218	{
f7b6fd6d JHD	219	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
f7b6fd6d	220
f7b6fd6d	221	dw_spi_remove_host(&dwsmmio->dws);
560ee7e9	222	clk_disable_unprepare(dwsmmio->pclk);
400c18e3	223	clk_disable_unprepare(dwsmmio->clk);
f7b6fd6d	224
f7b6fd6d JHD	225	return 0;
	226	}
	227
22dae17e ST	228	static const struct of_device_id dw_spi_mmio_of_match[] = {
22dae17e ST	229	{ .compatible = "snps,dw-apb-ssi", },
be17ee0d AB	230	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
be17ee0d AB	231	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
f2d70479	232	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
22dae17e ST	233	{ /* end of table */}
	234	};
	235	MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
	236
32215a6c JF	237	static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	238	{"HISI0173", 0},
	239	{},
	240	};
	241	MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
	242
f7b6fd6d	243	static struct platform_driver dw_spi_mmio_driver = {
940ab889	244	.probe = dw_spi_mmio_probe,
fd4a319b	245	.remove = dw_spi_mmio_remove,
f7b6fd6d JHD	246	.driver = {
f7b6fd6d JHD	247	.name = DRIVER_NAME,
22dae17e	248	.of_match_table = dw_spi_mmio_of_match,
32215a6c	249	.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
f7b6fd6d JHD	250	},
f7b6fd6d JHD	251	};
940ab889	252	module_platform_driver(dw_spi_mmio_driver);
f7b6fd6d JHD	253
	254	MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
	255	MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
	256	MODULE_LICENSE("GPL v2");