[linux-2.6-block.git] / drivers / spi / spi-dw-mmio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Memory-mapped interface driver for DW SPI Core
 *
 * Copyright (c) 2010, Octasic semiconductor.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/scatterlist.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/acpi.h>
#include <linux/property.h>
#include <linux/regmap.h>

#include "spi-dw.h"

#define DRIVER_NAME "dw_spi_mmio"

struct dw_spi_mmio {
	struct dw_spi  dws;
	struct clk     *clk;
	struct clk     *pclk;
	void           *priv;
};

#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL	0x24
#define OCELOT_IF_SI_OWNER_OFFSET		4
#define JAGUAR2_IF_SI_OWNER_OFFSET		6
#define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
#define MSCC_IF_SI_OWNER_SISL			0
#define MSCC_IF_SI_OWNER_SIBM			1
#define MSCC_IF_SI_OWNER_SIMC			2

#define MSCC_SPI_MST_SW_MODE			0x14
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)
#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)

struct dw_spi_mscc {
	struct regmap       *syscon;
	void __iomem        *spi_mst;
};

/*
 * The Designware SPI controller (referred to as master in the documentation)
 * automatically deasserts chip select when the tx fifo is empty. The chip
 * selects then needs to be either driven as GPIOs or, for the first 4 using the
 * the SPI boot controller registers. the final chip select is an OR gate
 * between the Designware SPI controller and the SPI boot controller.
 */
static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	u32 cs = spi->chip_select;

	if (cs < 4) {
		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;

		if (!enable)
			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));

		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	}

	dw_spi_set_cs(spi, enable);
}

static int dw_spi_mscc_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio,
			    const char *cpu_syscon, u32 if_si_owner_offset)
{
	struct dw_spi_mscc *dwsmscc;
	struct resource *res;

	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	if (!dwsmscc)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dwsmscc->spi_mst)) {
		dev_err(&pdev->dev, "SPI_MST region map failed\n");
		return PTR_ERR(dwsmscc->spi_mst);
	}

	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
	if (IS_ERR(dwsmscc->syscon))
		return PTR_ERR(dwsmscc->syscon);

	/* Deassert all CS */
	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);

	/* Select the owner of the SI interface */
	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
			   MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
			   MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);

	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	dwsmmio->priv = dwsmscc;

	return 0;
}

static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
				OCELOT_IF_SI_OWNER_OFFSET);
}

static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
				    struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
				JAGUAR2_IF_SI_OWNER_OFFSET);
}

static int dw_spi_alpine_init(struct platform_device *pdev,
			      struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.cs_override = 1;

	return 0;
}

static int dw_spi_mmio_probe(struct platform_device *pdev)
{
	int (*init_func)(struct platform_device *pdev,
			 struct dw_spi_mmio *dwsmmio);
	struct dw_spi_mmio *dwsmmio;
	struct dw_spi *dws;
	struct resource *mem;
	int ret;
	int num_cs;

	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
			GFP_KERNEL);
	if (!dwsmmio)
		return -ENOMEM;

	dws = &dwsmmio->dws;

	/* Get basic io resource and map it */
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	dws->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(dws->regs)) {
		dev_err(&pdev->dev, "SPI region map failed\n");
		return PTR_ERR(dws->regs);
	}

	dws->irq = platform_get_irq(pdev, 0);
	if (dws->irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return dws->irq; /* -ENXIO */
	}

	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(dwsmmio->clk))
		return PTR_ERR(dwsmmio->clk);
	ret = clk_prepare_enable(dwsmmio->clk);
	if (ret)
		return ret;

	/* Optional clock needed to access the registers */
	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
	if (IS_ERR(dwsmmio->pclk))
		return PTR_ERR(dwsmmio->pclk);
	ret = clk_prepare_enable(dwsmmio->pclk);
	if (ret)
		goto out_clk;

	dws->bus_num = pdev->id;

	dws->max_freq = clk_get_rate(dwsmmio->clk);

	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);

	num_cs = 4;

	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);

	dws->num_cs = num_cs;

	init_func = device_get_match_data(&pdev->dev);
	if (init_func) {
		ret = init_func(pdev, dwsmmio);
		if (ret)
			goto out;
	}

	ret = dw_spi_add_host(&pdev->dev, dws);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, dwsmmio);
	return 0;

out:
	clk_disable_unprepare(dwsmmio->pclk);
out_clk:
	clk_disable_unprepare(dwsmmio->clk);
	return ret;
}

static int dw_spi_mmio_remove(struct platform_device *pdev)
{
	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);

	dw_spi_remove_host(&dwsmmio->dws);
	clk_disable_unprepare(dwsmmio->pclk);
	clk_disable_unprepare(dwsmmio->clk);

	return 0;
}

static const struct of_device_id dw_spi_mmio_of_match[] = {
	{ .compatible = "snps,dw-apb-ssi", },
	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
	{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);

static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	{"HISI0173", 0},
	{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);

static struct platform_driver dw_spi_mmio_driver = {
	.probe		= dw_spi_mmio_probe,
	.remove		= dw_spi_mmio_remove,
	.driver		= {
		.name	= DRIVER_NAME,
		.of_match_table = dw_spi_mmio_of_match,
		.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
	},
};
module_platform_driver(dw_spi_mmio_driver);

MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
f7b6fd6d	2	/*
ca632f55	3	* Memory-mapped interface driver for DW SPI Core
f7b6fd6d JHD	4	*
f7b6fd6d JHD	5	* Copyright (c) 2010, Octasic semiconductor.
f7b6fd6d JHD	6	*/
	7
	8	#include <linux/clk.h>
50c01fc3	9	#include <linux/err.h>
f7b6fd6d JHD	10	#include <linux/interrupt.h>
f7b6fd6d JHD	11	#include <linux/platform_device.h>
5a0e3ad6	12	#include <linux/slab.h>
f7b6fd6d	13	#include <linux/spi/spi.h>
568a60ed	14	#include <linux/scatterlist.h>
c2c25cc3	15	#include <linux/mfd/syscon.h>
d7614de4	16	#include <linux/module.h>
22dae17e	17	#include <linux/of.h>
22dae17e	18	#include <linux/of_platform.h>
32215a6c	19	#include <linux/acpi.h>
9899995e	20	#include <linux/property.h>
c2c25cc3	21	#include <linux/regmap.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
f7b6fd6d JHD	24
	25	#define DRIVER_NAME "dw_spi_mmio"
	26
	27	struct dw_spi_mmio {
0a4c1d7d JHD	28	struct dw_spi dws;
0a4c1d7d JHD	29	struct clk *clk;
560ee7e9	30	struct clk *pclk;
c2c25cc3	31	void *priv;
f7b6fd6d JHD	32	};
f7b6fd6d JHD	33
c2c25cc3	34	#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
c2c25cc3	35	#define OCELOT_IF_SI_OWNER_OFFSET 4
be17ee0d	36	#define JAGUAR2_IF_SI_OWNER_OFFSET 6
c1d8b082	37	#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
c2c25cc3 AB	38	#define MSCC_IF_SI_OWNER_SISL 0
	39	#define MSCC_IF_SI_OWNER_SIBM 1
	40	#define MSCC_IF_SI_OWNER_SIMC 2
	41
	42	#define MSCC_SPI_MST_SW_MODE 0x14
	43	#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
	44	#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
	45
	46	struct dw_spi_mscc {
	47	struct regmap *syscon;
	48	void __iomem *spi_mst;
	49	};
	50
	51	/*
	52	* The Designware SPI controller (referred to as master in the documentation)
	53	* automatically deasserts chip select when the tx fifo is empty. The chip
	54	* selects then needs to be either driven as GPIOs or, for the first 4 using the
	55	* the SPI boot controller registers. the final chip select is an OR gate
	56	* between the Designware SPI controller and the SPI boot controller.
	57	*/
	58	static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
	59	{
	60	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	61	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	62	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	63	u32 cs = spi->chip_select;
	64
	65	if (cs < 4) {
	66	u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
	67
	68	if (!enable)
	69	sw_mode \|= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
	70
	71	writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	72	}
	73
	74	dw_spi_set_cs(spi, enable);
	75	}
	76
	77	static int dw_spi_mscc_init(struct platform_device *pdev,
be17ee0d AB	78	struct dw_spi_mmio *dwsmmio,
be17ee0d AB	79	const char *cpu_syscon, u32 if_si_owner_offset)
c2c25cc3 AB	80	{
	81	struct dw_spi_mscc *dwsmscc;
	82	struct resource *res;
	83
	84	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	85	if (!dwsmscc)
	86	return -ENOMEM;
	87
	88	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	89	dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
	90	if (IS_ERR(dwsmscc->spi_mst)) {
	91	dev_err(&pdev->dev, "SPI_MST region map failed\n");
	92	return PTR_ERR(dwsmscc->spi_mst);
	93	}
	94
be17ee0d	95	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
c2c25cc3 AB	96	if (IS_ERR(dwsmscc->syscon))
	97	return PTR_ERR(dwsmscc->syscon);
	98
	99	/* Deassert all CS */
	100	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	101
	102	/* Select the owner of the SI interface */
	103	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
c1d8b082	104	MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
be17ee0d	105	MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
c2c25cc3 AB	106
	107	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	108	dwsmmio->priv = dwsmscc;
	109
	110	return 0;
	111	}
	112
be17ee0d AB	113	static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
	114	struct dw_spi_mmio *dwsmmio)
	115	{
	116	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
	117	OCELOT_IF_SI_OWNER_OFFSET);
	118	}
	119
	120	static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
	121	struct dw_spi_mmio *dwsmmio)
	122	{
	123	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
	124	JAGUAR2_IF_SI_OWNER_OFFSET);
	125	}
	126
f2d70479 TS	127	static int dw_spi_alpine_init(struct platform_device *pdev,
	128	struct dw_spi_mmio *dwsmmio)
	129	{
	130	dwsmmio->dws.cs_override = 1;
	131
	132	return 0;
	133	}
	134
fd4a319b	135	static int dw_spi_mmio_probe(struct platform_device *pdev)
f7b6fd6d	136	{
c2c25cc3 AB	137	int (init_func)(struct platform_device pdev,
c2c25cc3 AB	138	struct dw_spi_mmio *dwsmmio);
f7b6fd6d JHD	139	struct dw_spi_mmio *dwsmmio;
f7b6fd6d JHD	140	struct dw_spi *dws;
04f421e7	141	struct resource *mem;
f7b6fd6d	142	int ret;
22dae17e	143	int num_cs;
f7b6fd6d	144
04f421e7 BS	145	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
	146	GFP_KERNEL);
	147	if (!dwsmmio)
	148	return -ENOMEM;
f7b6fd6d JHD	149
	150	dws = &dwsmmio->dws;
	151
	152	/* Get basic io resource and map it */
	153	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
04f421e7 BS	154	dws->regs = devm_ioremap_resource(&pdev->dev, mem);
	155	if (IS_ERR(dws->regs)) {
	156	dev_err(&pdev->dev, "SPI region map failed\n");
	157	return PTR_ERR(dws->regs);
f7b6fd6d JHD	158	}
	159
	160	dws->irq = platform_get_irq(pdev, 0);
	161	if (dws->irq < 0) {
	162	dev_err(&pdev->dev, "no irq resource?\n");
04f421e7	163	return dws->irq; /* -ENXIO */
f7b6fd6d JHD	164	}
f7b6fd6d JHD	165
04f421e7 BS	166	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	167	if (IS_ERR(dwsmmio->clk))
	168	return PTR_ERR(dwsmmio->clk);
020fe3fe	169	ret = clk_prepare_enable(dwsmmio->clk);
04f421e7 BS	170	if (ret)
04f421e7 BS	171	return ret;
f7b6fd6d	172
560ee7e9 PE	173	/* Optional clock needed to access the registers */
	174	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
	175	if (IS_ERR(dwsmmio->pclk))
	176	return PTR_ERR(dwsmmio->pclk);
	177	ret = clk_prepare_enable(dwsmmio->pclk);
	178	if (ret)
	179	goto out_clk;
	180
2418991e	181	dws->bus_num = pdev->id;
22dae17e	182
f7b6fd6d JHD	183	dws->max_freq = clk_get_rate(dwsmmio->clk);
f7b6fd6d JHD	184
9899995e	185	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
c4fe57f7	186
22dae17e ST	187	num_cs = 4;
22dae17e ST	188
9899995e	189	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
22dae17e ST	190
	191	dws->num_cs = num_cs;
	192
c2c25cc3 AB	193	init_func = device_get_match_data(&pdev->dev);
	194	if (init_func) {
	195	ret = init_func(pdev, dwsmmio);
	196	if (ret)
	197	goto out;
	198	}
	199
04f421e7	200	ret = dw_spi_add_host(&pdev->dev, dws);
f7b6fd6d	201	if (ret)
04f421e7	202	goto out;
f7b6fd6d JHD	203
	204	platform_set_drvdata(pdev, dwsmmio);
	205	return 0;
	206
04f421e7	207	out:
560ee7e9 PE	208	clk_disable_unprepare(dwsmmio->pclk);
560ee7e9 PE	209	out_clk:
020fe3fe	210	clk_disable_unprepare(dwsmmio->clk);
f7b6fd6d JHD	211	return ret;
	212	}
	213
fd4a319b	214	static int dw_spi_mmio_remove(struct platform_device *pdev)
f7b6fd6d JHD	215	{
f7b6fd6d JHD	216	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
f7b6fd6d	217
f7b6fd6d	218	dw_spi_remove_host(&dwsmmio->dws);
560ee7e9	219	clk_disable_unprepare(dwsmmio->pclk);
400c18e3	220	clk_disable_unprepare(dwsmmio->clk);
f7b6fd6d	221
f7b6fd6d JHD	222	return 0;
	223	}
	224
22dae17e ST	225	static const struct of_device_id dw_spi_mmio_of_match[] = {
22dae17e ST	226	{ .compatible = "snps,dw-apb-ssi", },
be17ee0d AB	227	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
be17ee0d AB	228	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
f2d70479	229	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
22dae17e ST	230	{ /* end of table */}
	231	};
	232	MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
	233
32215a6c JF	234	static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	235	{"HISI0173", 0},
	236	{},
	237	};
	238	MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
	239
f7b6fd6d	240	static struct platform_driver dw_spi_mmio_driver = {
940ab889	241	.probe = dw_spi_mmio_probe,
fd4a319b	242	.remove = dw_spi_mmio_remove,
f7b6fd6d JHD	243	.driver = {
f7b6fd6d JHD	244	.name = DRIVER_NAME,
22dae17e	245	.of_match_table = dw_spi_mmio_of_match,
32215a6c	246	.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
f7b6fd6d JHD	247	},
f7b6fd6d JHD	248	};
940ab889	249	module_platform_driver(dw_spi_mmio_driver);
f7b6fd6d JHD	250
	251	MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
	252	MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
	253	MODULE_LICENSE("GPL v2");