[linux-2.6-block.git] / drivers / spi / spi-dw-mmio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Memory-mapped interface driver for DW SPI Core
 *
 * Copyright (c) 2010, Octasic semiconductor.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/scatterlist.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/acpi.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include "spi-dw.h"

#define DRIVER_NAME "dw_spi_mmio"

struct dw_spi_mmio {
	struct dw_spi  dws;
	struct clk     *clk;
	struct clk     *pclk;
	void           *priv;
	struct reset_control *rstc;
};

#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL	0x24
#define OCELOT_IF_SI_OWNER_OFFSET		4
#define JAGUAR2_IF_SI_OWNER_OFFSET		6
#define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
#define MSCC_IF_SI_OWNER_SISL			0
#define MSCC_IF_SI_OWNER_SIBM			1
#define MSCC_IF_SI_OWNER_SIMC			2

#define MSCC_SPI_MST_SW_MODE			0x14
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)
#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)

#define SPARX5_FORCE_ENA			0xa4
#define SPARX5_FORCE_VAL			0xa8

struct dw_spi_mscc {
	struct regmap       *syscon;
	void __iomem        *spi_mst; /* Not sparx5 */
};

/*
 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
 * gpios for cs 2,3 as defined in the device tree.
 *
 * cs:  |       1               0
 * bit: |---3-------2-------1-------0
 *      |  cs1   cs1_ovr   cs0   cs0_ovr
 */
#define ELBA_SPICS_REG			0x2468
#define ELBA_SPICS_OFFSET(cs)		((cs) << 1)
#define ELBA_SPICS_MASK(cs)		(GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
#define ELBA_SPICS_SET(cs, val)		\
		((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))

/*
 * The Designware SPI controller (referred to as master in the documentation)
 * automatically deasserts chip select when the tx fifo is empty. The chip
 * selects then needs to be either driven as GPIOs or, for the first 4 using
 * the SPI boot controller registers. the final chip select is an OR gate
 * between the Designware SPI controller and the SPI boot controller.
 */
static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	u32 cs = spi_get_chipselect(spi, 0);

	if (cs < 4) {
		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;

		if (!enable)
			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));

		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	}

	dw_spi_set_cs(spi, enable);
}

static int dw_spi_mscc_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio,
			    const char *cpu_syscon, u32 if_si_owner_offset)
{
	struct dw_spi_mscc *dwsmscc;

	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	if (!dwsmscc)
		return -ENOMEM;

	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(dwsmscc->spi_mst)) {
		dev_err(&pdev->dev, "SPI_MST region map failed\n");
		return PTR_ERR(dwsmscc->spi_mst);
	}

	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
	if (IS_ERR(dwsmscc->syscon))
		return PTR_ERR(dwsmscc->syscon);

	/* Deassert all CS */
	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);

	/* Select the owner of the SI interface */
	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
			   MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
			   MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);

	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	dwsmmio->priv = dwsmscc;

	return 0;
}

static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
				OCELOT_IF_SI_OWNER_OFFSET);
}

static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
				    struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
				JAGUAR2_IF_SI_OWNER_OFFSET);
}

/*
 * The Designware SPI controller (referred to as master in the
 * documentation) automatically deasserts chip select when the tx fifo
 * is empty. The chip selects then needs to be driven by a CS override
 * register. enable is an active low signal.
 */
static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	u8 cs = spi_get_chipselect(spi, 0);

	if (!enable) {
		/* CS override drive enable */
		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
		/* Now set CSx enabled */
		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
		/* Allow settle */
		usleep_range(1, 5);
	} else {
		/* CS value */
		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
		/* Allow settle */
		usleep_range(1, 5);
		/* CS override drive disable */
		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
	}

	dw_spi_set_cs(spi, enable);
}

static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	const char *syscon_name = "microchip,sparx5-cpu-syscon";
	struct device *dev = &pdev->dev;
	struct dw_spi_mscc *dwsmscc;

	if (!IS_ENABLED(CONFIG_SPI_MUX)) {
		dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
		return -EOPNOTSUPP;
	}

	dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
	if (!dwsmscc)
		return -ENOMEM;

	dwsmscc->syscon =
		syscon_regmap_lookup_by_compatible(syscon_name);
	if (IS_ERR(dwsmscc->syscon)) {
		dev_err(dev, "No syscon map %s\n", syscon_name);
		return PTR_ERR(dwsmscc->syscon);
	}

	dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
	dwsmmio->priv = dwsmscc;

	return 0;
}

static int dw_spi_alpine_init(struct platform_device *pdev,
			      struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;

	return 0;
}

static int dw_spi_pssi_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio)
{
	dw_spi_dma_setup_generic(&dwsmmio->dws);

	return 0;
}

static int dw_spi_hssi_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.ip = DW_HSSI_ID;

	dw_spi_dma_setup_generic(&dwsmmio->dws);

	return 0;
}

static int dw_spi_intel_init(struct platform_device *pdev,
			     struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.ip = DW_HSSI_ID;

	return 0;
}

static int dw_spi_canaan_k210_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	/*
	 * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
	 * documented to have a 32 word deep TX and RX FIFO, which
	 * spi_hw_init() detects. However, when the RX FIFO is filled up to
	 * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
	 * problem by force setting fifo_len to 31.
	 */
	dwsmmio->dws.fifo_len = 31;

	return 0;
}

static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
{
	regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
			   ELBA_SPICS_SET(cs, enable));
}

static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct regmap *syscon = dwsmmio->priv;
	u8 cs;

	cs = spi_get_chipselect(spi, 0);
	if (cs < 2)
		dw_spi_elba_override_cs(syscon, spi_get_chipselect(spi, 0), enable);

	/*
	 * The DW SPI controller needs a native CS bit selected to start
	 * the serial engine.
	 */
	spi_set_chipselect(spi, 0, 0);
	dw_spi_set_cs(spi, enable);
	spi_set_chipselect(spi, 0, cs);
}

static int dw_spi_elba_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio)
{
	struct regmap *syscon;

	syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
						 "amd,pensando-elba-syscon");
	if (IS_ERR(syscon))
		return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
				     "syscon regmap lookup failed\n");

	dwsmmio->priv = syscon;
	dwsmmio->dws.set_cs = dw_spi_elba_set_cs;

	return 0;
}

static int dw_spi_mmio_probe(struct platform_device *pdev)
{
	int (*init_func)(struct platform_device *pdev,
			 struct dw_spi_mmio *dwsmmio);
	struct dw_spi_mmio *dwsmmio;
	struct resource *mem;
	struct dw_spi *dws;
	int ret;
	int num_cs;

	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
			GFP_KERNEL);
	if (!dwsmmio)
		return -ENOMEM;

	dws = &dwsmmio->dws;

	/* Get basic io resource and map it */
	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
	if (IS_ERR(dws->regs))
		return PTR_ERR(dws->regs);

	dws->paddr = mem->start;

	dws->irq = platform_get_irq(pdev, 0);
	if (dws->irq < 0)
		return dws->irq; /* -ENXIO */

	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(dwsmmio->clk))
		return PTR_ERR(dwsmmio->clk);
	ret = clk_prepare_enable(dwsmmio->clk);
	if (ret)
		return ret;

	/* Optional clock needed to access the registers */
	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
	if (IS_ERR(dwsmmio->pclk)) {
		ret = PTR_ERR(dwsmmio->pclk);
		goto out_clk;
	}
	ret = clk_prepare_enable(dwsmmio->pclk);
	if (ret)
		goto out_clk;

	/* find an optional reset controller */
	dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
	if (IS_ERR(dwsmmio->rstc)) {
		ret = PTR_ERR(dwsmmio->rstc);
		goto out_clk;
	}
	reset_control_deassert(dwsmmio->rstc);

	dws->bus_num = pdev->id;

	dws->max_freq = clk_get_rate(dwsmmio->clk);

	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);

	num_cs = 4;

	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);

	dws->num_cs = num_cs;

	init_func = device_get_match_data(&pdev->dev);
	if (init_func) {
		ret = init_func(pdev, dwsmmio);
		if (ret)
			goto out;
	}

	pm_runtime_enable(&pdev->dev);

	ret = dw_spi_add_host(&pdev->dev, dws);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, dwsmmio);
	return 0;

out:
	pm_runtime_disable(&pdev->dev);
	clk_disable_unprepare(dwsmmio->pclk);
out_clk:
	clk_disable_unprepare(dwsmmio->clk);
	reset_control_assert(dwsmmio->rstc);

	return ret;
}

static void dw_spi_mmio_remove(struct platform_device *pdev)
{
	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);

	dw_spi_remove_host(&dwsmmio->dws);
	pm_runtime_disable(&pdev->dev);
	clk_disable_unprepare(dwsmmio->pclk);
	clk_disable_unprepare(dwsmmio->clk);
	reset_control_assert(dwsmmio->rstc);
}

static const struct of_device_id dw_spi_mmio_of_match[] = {
	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
	{ .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
	{ .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
	{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
	{ .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
	{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);

#ifdef CONFIG_ACPI
static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	{"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
	{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
#endif

static struct platform_driver dw_spi_mmio_driver = {
	.probe		= dw_spi_mmio_probe,
	.remove_new	= dw_spi_mmio_remove,
	.driver		= {
		.name	= DRIVER_NAME,
		.of_match_table = dw_spi_mmio_of_match,
		.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
	},
};
module_platform_driver(dw_spi_mmio_driver);

MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(SPI_DW_CORE);
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
f7b6fd6d	2	/*
ca632f55	3	* Memory-mapped interface driver for DW SPI Core
f7b6fd6d JHD	4	*
f7b6fd6d JHD	5	* Copyright (c) 2010, Octasic semiconductor.
f7b6fd6d JHD	6	*/
	7
	8	#include <linux/clk.h>
50c01fc3	9	#include <linux/err.h>
f7b6fd6d	10	#include <linux/platform_device.h>
b9fc2d20	11	#include <linux/pm_runtime.h>
5a0e3ad6	12	#include <linux/slab.h>
f7b6fd6d	13	#include <linux/spi/spi.h>
568a60ed	14	#include <linux/scatterlist.h>
c2c25cc3	15	#include <linux/mfd/syscon.h>
d7614de4	16	#include <linux/module.h>
22dae17e	17	#include <linux/of.h>
22dae17e	18	#include <linux/of_platform.h>
32215a6c	19	#include <linux/acpi.h>
9899995e	20	#include <linux/property.h>
c2c25cc3	21	#include <linux/regmap.h>
7830c0ef	22	#include <linux/reset.h>
568a60ed	23
ca632f55	24	#include "spi-dw.h"
f7b6fd6d JHD	25
	26	#define DRIVER_NAME "dw_spi_mmio"
	27
	28	struct dw_spi_mmio {
0a4c1d7d JHD	29	struct dw_spi dws;
0a4c1d7d JHD	30	struct clk *clk;
560ee7e9	31	struct clk *pclk;
c2c25cc3	32	void *priv;
7830c0ef	33	struct reset_control *rstc;
f7b6fd6d JHD	34	};
f7b6fd6d JHD	35
c2c25cc3	36	#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
c2c25cc3	37	#define OCELOT_IF_SI_OWNER_OFFSET 4
be17ee0d	38	#define JAGUAR2_IF_SI_OWNER_OFFSET 6
c1d8b082	39	#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
c2c25cc3 AB	40	#define MSCC_IF_SI_OWNER_SISL 0
	41	#define MSCC_IF_SI_OWNER_SIBM 1
	42	#define MSCC_IF_SI_OWNER_SIMC 2
	43
	44	#define MSCC_SPI_MST_SW_MODE 0x14
	45	#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
	46	#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
	47
53a09635 LP	48	#define SPARX5_FORCE_ENA 0xa4
	49	#define SPARX5_FORCE_VAL 0xa8
	50
c2c25cc3 AB	51	struct dw_spi_mscc {
c2c25cc3 AB	52	struct regmap *syscon;
53a09635	53	void __iomem spi_mst; / Not sparx5 */
c2c25cc3 AB	54	};
c2c25cc3 AB	55
2c860604 BL	56	/*
	57	* Elba SoC does not use ssi, pin override is used for cs 0,1 and
	58	* gpios for cs 2,3 as defined in the device tree.
	59	*
	60	* cs: \| 1 0
	61	* bit: \|---3-------2-------1-------0
	62	* \| cs1 cs1_ovr cs0 cs0_ovr
	63	*/
	64	#define ELBA_SPICS_REG 0x2468
	65	#define ELBA_SPICS_OFFSET(cs) ((cs) << 1)
	66	#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
	67	#define ELBA_SPICS_SET(cs, val) \
	68	((((val) << 1) \| BIT(0)) << ELBA_SPICS_OFFSET(cs))
	69
c2c25cc3 AB	70	/*
	71	* The Designware SPI controller (referred to as master in the documentation)
	72	* automatically deasserts chip select when the tx fifo is empty. The chip
db56d030	73	* selects then needs to be either driven as GPIOs or, for the first 4 using
c2c25cc3 AB	74	* the SPI boot controller registers. the final chip select is an OR gate
	75	* between the Designware SPI controller and the SPI boot controller.
	76	*/
	77	static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
	78	{
	79	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	80	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	81	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
9e264f3f	82	u32 cs = spi_get_chipselect(spi, 0);
c2c25cc3 AB	83
	84	if (cs < 4) {
	85	u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
	86
	87	if (!enable)
	88	sw_mode \|= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
	89
	90	writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	91	}
	92
	93	dw_spi_set_cs(spi, enable);
	94	}
	95
	96	static int dw_spi_mscc_init(struct platform_device *pdev,
be17ee0d AB	97	struct dw_spi_mmio *dwsmmio,
be17ee0d AB	98	const char *cpu_syscon, u32 if_si_owner_offset)
c2c25cc3 AB	99	{
c2c25cc3 AB	100	struct dw_spi_mscc *dwsmscc;
c2c25cc3 AB	101
	102	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	103	if (!dwsmscc)
	104	return -ENOMEM;
	105
5cc6fdcc	106	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
c2c25cc3 AB	107	if (IS_ERR(dwsmscc->spi_mst)) {
	108	dev_err(&pdev->dev, "SPI_MST region map failed\n");
	109	return PTR_ERR(dwsmscc->spi_mst);
	110	}
	111
be17ee0d	112	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
c2c25cc3 AB	113	if (IS_ERR(dwsmscc->syscon))
	114	return PTR_ERR(dwsmscc->syscon);
	115
	116	/* Deassert all CS */
	117	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	118
	119	/* Select the owner of the SI interface */
	120	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
c1d8b082	121	MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
be17ee0d	122	MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
c2c25cc3 AB	123
	124	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	125	dwsmmio->priv = dwsmscc;
	126
	127	return 0;
	128	}
	129
be17ee0d AB	130	static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
	131	struct dw_spi_mmio *dwsmmio)
	132	{
	133	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
	134	OCELOT_IF_SI_OWNER_OFFSET);
	135	}
	136
	137	static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
	138	struct dw_spi_mmio *dwsmmio)
	139	{
	140	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
	141	JAGUAR2_IF_SI_OWNER_OFFSET);
	142	}
	143
53a09635 LP	144	/*
	145	* The Designware SPI controller (referred to as master in the
	146	* documentation) automatically deasserts chip select when the tx fifo
	147	* is empty. The chip selects then needs to be driven by a CS override
	148	* register. enable is an active low signal.
	149	*/
	150	static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
	151	{
	152	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	153	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	154	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
9e264f3f	155	u8 cs = spi_get_chipselect(spi, 0);
53a09635 LP	156
	157	if (!enable) {
	158	/* CS override drive enable */
	159	regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
	160	/* Now set CSx enabled */
	161	regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
	162	/* Allow settle */
	163	usleep_range(1, 5);
	164	} else {
	165	/* CS value */
	166	regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
	167	/* Allow settle */
	168	usleep_range(1, 5);
	169	/* CS override drive disable */
	170	regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
	171	}
	172
	173	dw_spi_set_cs(spi, enable);
	174	}
	175
	176	static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
	177	struct dw_spi_mmio *dwsmmio)
	178	{
	179	const char *syscon_name = "microchip,sparx5-cpu-syscon";
	180	struct device *dev = &pdev->dev;
	181	struct dw_spi_mscc *dwsmscc;
	182
	183	if (!IS_ENABLED(CONFIG_SPI_MUX)) {
	184	dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
	185	return -EOPNOTSUPP;
	186	}
	187
	188	dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
	189	if (!dwsmscc)
	190	return -ENOMEM;
	191
	192	dwsmscc->syscon =
	193	syscon_regmap_lookup_by_compatible(syscon_name);
	194	if (IS_ERR(dwsmscc->syscon)) {
	195	dev_err(dev, "No syscon map %s\n", syscon_name);
	196	return PTR_ERR(dwsmscc->syscon);
	197	}
	198
	199	dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
	200	dwsmmio->priv = dwsmscc;
	201
53a09635 LP	202	return 0;
	203	}
	204
f2d70479 TS	205	static int dw_spi_alpine_init(struct platform_device *pdev,
	206	struct dw_spi_mmio *dwsmmio)
	207	{
cc760f31	208	dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;
f2d70479	209
c4eadee2 WAZ	210	return 0;
	211	}
	212
725b0e3e SS	213	static int dw_spi_pssi_init(struct platform_device *pdev,
725b0e3e SS	214	struct dw_spi_mmio *dwsmmio)
c4eadee2	215	{
0fdad596 SS	216	dw_spi_dma_setup_generic(&dwsmmio->dws);
0fdad596 SS	217
f2d70479 TS	218	return 0;
	219	}
	220
725b0e3e SS	221	static int dw_spi_hssi_init(struct platform_device *pdev,
725b0e3e SS	222	struct dw_spi_mmio *dwsmmio)
e539f435	223	{
2b8a47e0	224	dwsmmio->dws.ip = DW_HSSI_ID;
e539f435	225
0fdad596 SS	226	dw_spi_dma_setup_generic(&dwsmmio->dws);
0fdad596 SS	227
e539f435 WAZ	228	return 0;
	229	}
	230
dc4e6d9f NS	231	static int dw_spi_intel_init(struct platform_device *pdev,
dc4e6d9f NS	232	struct dw_spi_mmio *dwsmmio)
f4237791	233	{
2b8a47e0	234	dwsmmio->dws.ip = DW_HSSI_ID;
f4237791 WAZ	235
	236	return 0;
	237	}
	238
b0dfd948 DLM	239	static int dw_spi_canaan_k210_init(struct platform_device *pdev,
	240	struct dw_spi_mmio *dwsmmio)
	241	{
	242	/*
	243	* The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
	244	* documented to have a 32 word deep TX and RX FIFO, which
	245	* spi_hw_init() detects. However, when the RX FIFO is filled up to
	246	* 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
	247	* problem by force setting fifo_len to 31.
	248	*/
	249	dwsmmio->dws.fifo_len = 31;
	250
	251	return 0;
	252	}
	253
2c860604 BL	254	static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
	255	{
	256	regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
	257	ELBA_SPICS_SET(cs, enable));
	258	}
	259
	260	static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
	261	{
	262	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	263	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	264	struct regmap *syscon = dwsmmio->priv;
	265	u8 cs;
	266
445164e8	267	cs = spi_get_chipselect(spi, 0);
2c860604	268	if (cs < 2)
445164e8	269	dw_spi_elba_override_cs(syscon, spi_get_chipselect(spi, 0), enable);
2c860604 BL	270
	271	/*
	272	* The DW SPI controller needs a native CS bit selected to start
	273	* the serial engine.
	274	*/
445164e8	275	spi_set_chipselect(spi, 0, 0);
2c860604	276	dw_spi_set_cs(spi, enable);
eee43699	277	spi_set_chipselect(spi, 0, cs);
2c860604 BL	278	}
	279
	280	static int dw_spi_elba_init(struct platform_device *pdev,
	281	struct dw_spi_mmio *dwsmmio)
	282	{
	283	struct regmap *syscon;
	284
	285	syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
	286	"amd,pensando-elba-syscon");
	287	if (IS_ERR(syscon))
	288	return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
	289	"syscon regmap lookup failed\n");
	290
	291	dwsmmio->priv = syscon;
	292	dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
	293
	294	return 0;
	295	}
	296
fd4a319b	297	static int dw_spi_mmio_probe(struct platform_device *pdev)
f7b6fd6d	298	{
c2c25cc3 AB	299	int (init_func)(struct platform_device pdev,
c2c25cc3 AB	300	struct dw_spi_mmio *dwsmmio);
f7b6fd6d	301	struct dw_spi_mmio *dwsmmio;
77810d48	302	struct resource *mem;
f7b6fd6d	303	struct dw_spi *dws;
f7b6fd6d	304	int ret;
22dae17e	305	int num_cs;
f7b6fd6d	306
04f421e7 BS	307	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
	308	GFP_KERNEL);
	309	if (!dwsmmio)
	310	return -ENOMEM;
f7b6fd6d JHD	311
	312	dws = &dwsmmio->dws;
	313
	314	/* Get basic io resource and map it */
77810d48	315	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
afb7f565	316	if (IS_ERR(dws->regs))
04f421e7	317	return PTR_ERR(dws->regs);
f7b6fd6d	318
77810d48 SS	319	dws->paddr = mem->start;
77810d48 SS	320
f7b6fd6d	321	dws->irq = platform_get_irq(pdev, 0);
6b8ac10e	322	if (dws->irq < 0)
04f421e7	323	return dws->irq; /* -ENXIO */
f7b6fd6d	324
04f421e7 BS	325	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	326	if (IS_ERR(dwsmmio->clk))
	327	return PTR_ERR(dwsmmio->clk);
020fe3fe	328	ret = clk_prepare_enable(dwsmmio->clk);
04f421e7 BS	329	if (ret)
04f421e7 BS	330	return ret;
f7b6fd6d	331
560ee7e9 PE	332	/* Optional clock needed to access the registers */
560ee7e9 PE	333	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
3da9834d AS	334	if (IS_ERR(dwsmmio->pclk)) {
	335	ret = PTR_ERR(dwsmmio->pclk);
	336	goto out_clk;
	337	}
560ee7e9 PE	338	ret = clk_prepare_enable(dwsmmio->pclk);
	339	if (ret)
	340	goto out_clk;
	341
7830c0ef DN	342	/* find an optional reset controller */
	343	dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
	344	if (IS_ERR(dwsmmio->rstc)) {
	345	ret = PTR_ERR(dwsmmio->rstc);
	346	goto out_clk;
	347	}
	348	reset_control_deassert(dwsmmio->rstc);
	349
2418991e	350	dws->bus_num = pdev->id;
22dae17e	351
f7b6fd6d JHD	352	dws->max_freq = clk_get_rate(dwsmmio->clk);
f7b6fd6d JHD	353
9899995e	354	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
c4fe57f7	355
22dae17e ST	356	num_cs = 4;
22dae17e ST	357
9899995e	358	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
22dae17e ST	359
	360	dws->num_cs = num_cs;
	361
c2c25cc3 AB	362	init_func = device_get_match_data(&pdev->dev);
	363	if (init_func) {
	364	ret = init_func(pdev, dwsmmio);
	365	if (ret)
	366	goto out;
	367	}
	368
b9fc2d20 JN	369	pm_runtime_enable(&pdev->dev);
b9fc2d20 JN	370
04f421e7	371	ret = dw_spi_add_host(&pdev->dev, dws);
f7b6fd6d	372	if (ret)
04f421e7	373	goto out;
f7b6fd6d JHD	374
	375	platform_set_drvdata(pdev, dwsmmio);
	376	return 0;
	377
04f421e7	378	out:
b9fc2d20	379	pm_runtime_disable(&pdev->dev);
560ee7e9 PE	380	clk_disable_unprepare(dwsmmio->pclk);
560ee7e9 PE	381	out_clk:
020fe3fe	382	clk_disable_unprepare(dwsmmio->clk);
7830c0ef DN	383	reset_control_assert(dwsmmio->rstc);
7830c0ef DN	384
f7b6fd6d JHD	385	return ret;
	386	}
	387
f74abea2	388	static void dw_spi_mmio_remove(struct platform_device *pdev)
f7b6fd6d JHD	389	{
f7b6fd6d JHD	390	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
f7b6fd6d	391
f7b6fd6d	392	dw_spi_remove_host(&dwsmmio->dws);
b9fc2d20	393	pm_runtime_disable(&pdev->dev);
560ee7e9	394	clk_disable_unprepare(dwsmmio->pclk);
400c18e3	395	clk_disable_unprepare(dwsmmio->clk);
7830c0ef	396	reset_control_assert(dwsmmio->rstc);
f7b6fd6d JHD	397	}
f7b6fd6d JHD	398
22dae17e	399	static const struct of_device_id dw_spi_mmio_of_match[] = {
725b0e3e	400	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
be17ee0d AB	401	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
be17ee0d AB	402	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
f2d70479	403	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
725b0e3e SS	404	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
725b0e3e SS	405	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
dc4e6d9f NS	406	{ .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
dc4e6d9f NS	407	{ .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
53a09635	408	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
b0dfd948	409	{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
2c860604	410	{ .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
22dae17e ST	411	{ /* end of table */}
	412	};
	413	MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
	414
4dd227a5	415	#ifdef CONFIG_ACPI
32215a6c	416	static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
725b0e3e	417	{"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
32215a6c JF	418	{},
	419	};
	420	MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
4dd227a5	421	#endif
32215a6c	422
f7b6fd6d	423	static struct platform_driver dw_spi_mmio_driver = {
940ab889	424	.probe = dw_spi_mmio_probe,
f74abea2	425	.remove_new = dw_spi_mmio_remove,
f7b6fd6d JHD	426	.driver = {
f7b6fd6d JHD	427	.name = DRIVER_NAME,
22dae17e	428	.of_match_table = dw_spi_mmio_of_match,
32215a6c	429	.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
f7b6fd6d JHD	430	},
f7b6fd6d JHD	431	};
940ab889	432	module_platform_driver(dw_spi_mmio_driver);
f7b6fd6d JHD	433
	434	MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
	435	MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
	436	MODULE_LICENSE("GPL v2");
a62bacba	437	MODULE_IMPORT_NS(SPI_DW_CORE);