[linux-2.6-block.git] / drivers / spi / spi-dw-core.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Designware SPI core controller driver (refer pxa2xx_spi.c)
 *
 * Copyright (c) 2009, Intel Corporation.
 */

#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/highmem.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>

#include "spi-dw.h"

#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#endif

/* Slave spi_dev related */
struct chip_data {
	u8 tmode;		/* TR/TO/RO/EEPROM */
	u8 type;		/* SPI/SSP/MicroWire */

	u16 clk_div;		/* baud rate divider */
	u32 speed_hz;		/* baud rate */
};

#ifdef CONFIG_DEBUG_FS

#define DW_SPI_DBGFS_REG(_name, _off)	\
{					\
	.name = _name,			\
	.offset = _off,			\
}

static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
	DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
	DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
	DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
	DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
	DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
	DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
	DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
	DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
	DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
	DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
	DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
	DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
	DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
	DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
	DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
};

static int dw_spi_debugfs_init(struct dw_spi *dws)
{
	char name[32];

	snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
	dws->debugfs = debugfs_create_dir(name, NULL);
	if (!dws->debugfs)
		return -ENOMEM;

	dws->regset.regs = dw_spi_dbgfs_regs;
	dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
	dws->regset.base = dws->regs;
	debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);

	return 0;
}

static void dw_spi_debugfs_remove(struct dw_spi *dws)
{
	debugfs_remove_recursive(dws->debugfs);
}

#else
static inline int dw_spi_debugfs_init(struct dw_spi *dws)
{
	return 0;
}

static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
{
}
#endif /* CONFIG_DEBUG_FS */

void dw_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
	bool cs_high = !!(spi->mode & SPI_CS_HIGH);

	/*
	 * DW SPI controller demands any native CS being set in order to
	 * proceed with data transfer. So in order to activate the SPI
	 * communications we must set a corresponding bit in the Slave
	 * Enable register no matter whether the SPI core is configured to
	 * support active-high or active-low CS level.
	 */
	if (cs_high == enable)
		dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
	else if (dws->cs_override)
		dw_writel(dws, DW_SPI_SER, 0);
}
EXPORT_SYMBOL_GPL(dw_spi_set_cs);

/* Return the max entries we can fill into tx fifo */
static inline u32 tx_max(struct dw_spi *dws)
{
	u32 tx_left, tx_room, rxtx_gap;

	tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
	tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);

	/*
	 * Another concern is about the tx/rx mismatch, we
	 * though to use (dws->fifo_len - rxflr - txflr) as
	 * one maximum value for tx, but it doesn't cover the
	 * data which is out of tx/rx fifo and inside the
	 * shift registers. So a control from sw point of
	 * view is taken.
	 */
	rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
			/ dws->n_bytes;

	return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
}

/* Return the max entries we should read out of rx fifo */
static inline u32 rx_max(struct dw_spi *dws)
{
	u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;

	return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
}

static void dw_writer(struct dw_spi *dws)
{
	u32 max;
	u16 txw = 0;

	spin_lock(&dws->buf_lock);
	max = tx_max(dws);
	while (max--) {
		/* Set the tx word if the transfer's original "tx" is not null */
		if (dws->tx_end - dws->len) {
			if (dws->n_bytes == 1)
				txw = *(u8 *)(dws->tx);
			else
				txw = *(u16 *)(dws->tx);
		}
		dw_write_io_reg(dws, DW_SPI_DR, txw);
		dws->tx += dws->n_bytes;
	}
	spin_unlock(&dws->buf_lock);
}

static void dw_reader(struct dw_spi *dws)
{
	u32 max;
	u16 rxw;

	spin_lock(&dws->buf_lock);
	max = rx_max(dws);
	while (max--) {
		rxw = dw_read_io_reg(dws, DW_SPI_DR);
		/* Care rx only if the transfer's original "rx" is not null */
		if (dws->rx_end - dws->len) {
			if (dws->n_bytes == 1)
				*(u8 *)(dws->rx) = rxw;
			else
				*(u16 *)(dws->rx) = rxw;
		}
		dws->rx += dws->n_bytes;
	}
	spin_unlock(&dws->buf_lock);
}

static void int_error_stop(struct dw_spi *dws, const char *msg)
{
	spi_reset_chip(dws);

	dev_err(&dws->master->dev, "%s\n", msg);
	dws->master->cur_msg->status = -EIO;
	spi_finalize_current_transfer(dws->master);
}

static irqreturn_t interrupt_transfer(struct dw_spi *dws)
{
	u16 irq_status = dw_readl(dws, DW_SPI_ISR);

	/* Error handling */
	if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
		dw_readl(dws, DW_SPI_ICR);
		int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
		return IRQ_HANDLED;
	}

	dw_reader(dws);
	if (dws->rx_end == dws->rx) {
		spi_mask_intr(dws, SPI_INT_TXEI);
		spi_finalize_current_transfer(dws->master);
		return IRQ_HANDLED;
	}
	if (irq_status & SPI_INT_TXEI) {
		spi_mask_intr(dws, SPI_INT_TXEI);
		dw_writer(dws);
		/* Enable TX irq always, it will be disabled when RX finished */
		spi_umask_intr(dws, SPI_INT_TXEI);
	}

	return IRQ_HANDLED;
}

static irqreturn_t dw_spi_irq(int irq, void *dev_id)
{
	struct spi_controller *master = dev_id;
	struct dw_spi *dws = spi_controller_get_devdata(master);
	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;

	if (!irq_status)
		return IRQ_NONE;

	if (!master->cur_msg) {
		spi_mask_intr(dws, SPI_INT_TXEI);
		return IRQ_HANDLED;
	}

	return dws->transfer_handler(dws);
}

/* Configure CTRLR0 for DW_apb_ssi */
u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi,
		      struct spi_transfer *transfer)
{
	struct chip_data *chip = spi_get_ctldata(spi);
	u32 cr0;

	/* Default SPI mode is SCPOL = 0, SCPH = 0 */
	cr0 = (transfer->bits_per_word - 1)
		| (chip->type << SPI_FRF_OFFSET)
		| ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |
		   (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |
		   (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
		| (chip->tmode << SPI_TMOD_OFFSET);

	return cr0;
}
EXPORT_SYMBOL_GPL(dw_spi_update_cr0);

/* Configure CTRLR0 for DWC_ssi */
u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
			     struct spi_device *spi,
			     struct spi_transfer *transfer)
{
	struct chip_data *chip = spi_get_ctldata(spi);
	u32 cr0;

	/* CTRLR0[ 4: 0] Data Frame Size */
	cr0 = (transfer->bits_per_word - 1);

	/* CTRLR0[ 7: 6] Frame Format */
	cr0 |= chip->type << DWC_SSI_CTRLR0_FRF_OFFSET;

	/*
	 * SPI mode (SCPOL|SCPH)
	 * CTRLR0[ 8] Serial Clock Phase
	 * CTRLR0[ 9] Serial Clock Polarity
	 */
	cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET;
	cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET;

	/* CTRLR0[11:10] Transfer Mode */
	cr0 |= chip->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET;

	/* CTRLR0[13] Shift Register Loop */
	cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET;

	return cr0;
}
EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a);

static int dw_spi_transfer_one(struct spi_controller *master,
		struct spi_device *spi, struct spi_transfer *transfer)
{
	struct dw_spi *dws = spi_controller_get_devdata(master);
	struct chip_data *chip = spi_get_ctldata(spi);
	unsigned long flags;
	u8 imask = 0;
	u16 txlevel = 0;
	u32 cr0;
	int ret;

	dws->dma_mapped = 0;
	spin_lock_irqsave(&dws->buf_lock, flags);
	dws->tx = (void *)transfer->tx_buf;
	dws->tx_end = dws->tx + transfer->len;
	dws->rx = transfer->rx_buf;
	dws->rx_end = dws->rx + transfer->len;
	dws->len = transfer->len;
	spin_unlock_irqrestore(&dws->buf_lock, flags);

	/* Ensure dw->rx and dw->rx_end are visible */
	smp_mb();

	spi_enable_chip(dws, 0);

	/* Handle per transfer options for bpw and speed */
	if (transfer->speed_hz != dws->current_freq) {
		if (transfer->speed_hz != chip->speed_hz) {
			/* clk_div doesn't support odd number */
			chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
			chip->speed_hz = transfer->speed_hz;
		}
		dws->current_freq = transfer->speed_hz;
		spi_set_clk(dws, chip->clk_div);
	}

	transfer->effective_speed_hz = dws->max_freq / chip->clk_div;
	dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);

	cr0 = dws->update_cr0(master, spi, transfer);
	dw_writel(dws, DW_SPI_CTRLR0, cr0);

	/* Check if current transfer is a DMA transaction */
	if (master->can_dma && master->can_dma(master, spi, transfer))
		dws->dma_mapped = master->cur_msg_mapped;

	/* For poll mode just disable all interrupts */
	spi_mask_intr(dws, 0xff);

	/*
	 * Interrupt mode
	 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
	 */
	if (dws->dma_mapped) {
		ret = dws->dma_ops->dma_setup(dws, transfer);
		if (ret < 0) {
			spi_enable_chip(dws, 1);
			return ret;
		}
	} else {
		txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
		dw_writel(dws, DW_SPI_TXFTLR, txlevel);

		/* Set the interrupt mask */
		imask |= SPI_INT_TXEI | SPI_INT_TXOI |
			 SPI_INT_RXUI | SPI_INT_RXOI;
		spi_umask_intr(dws, imask);

		dws->transfer_handler = interrupt_transfer;
	}

	spi_enable_chip(dws, 1);

	if (dws->dma_mapped)
		return dws->dma_ops->dma_transfer(dws, transfer);

	return 1;
}

static void dw_spi_handle_err(struct spi_controller *master,
		struct spi_message *msg)
{
	struct dw_spi *dws = spi_controller_get_devdata(master);

	if (dws->dma_mapped)
		dws->dma_ops->dma_stop(dws);

	spi_reset_chip(dws);
}

/* This may be called twice for each spi dev */
static int dw_spi_setup(struct spi_device *spi)
{
	struct chip_data *chip;

	/* Only alloc on first setup */
	chip = spi_get_ctldata(spi);
	if (!chip) {
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
		if (!chip)
			return -ENOMEM;
		spi_set_ctldata(spi, chip);
	}

	chip->tmode = SPI_TMOD_TR;

	return 0;
}

static void dw_spi_cleanup(struct spi_device *spi)
{
	struct chip_data *chip = spi_get_ctldata(spi);

	kfree(chip);
	spi_set_ctldata(spi, NULL);
}

/* Restart the controller, disable all interrupts, clean rx fifo */
static void spi_hw_init(struct device *dev, struct dw_spi *dws)
{
	spi_reset_chip(dws);

	/*
	 * Try to detect the FIFO depth if not set by interface driver,
	 * the depth could be from 2 to 256 from HW spec
	 */
	if (!dws->fifo_len) {
		u32 fifo;

		for (fifo = 1; fifo < 256; fifo++) {
			dw_writel(dws, DW_SPI_TXFTLR, fifo);
			if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
				break;
		}
		dw_writel(dws, DW_SPI_TXFTLR, 0);

		dws->fifo_len = (fifo == 1) ? 0 : fifo;
		dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
	}

	/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
	if (dws->cs_override)
		dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
}

int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
{
	struct spi_controller *master;
	int ret;

	if (!dws)
		return -EINVAL;

	master = spi_alloc_master(dev, 0);
	if (!master)
		return -ENOMEM;

	dws->master = master;
	dws->type = SSI_MOTO_SPI;
	dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
	spin_lock_init(&dws->buf_lock);

	spi_controller_set_devdata(master, dws);

	ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
			  master);
	if (ret < 0) {
		dev_err(dev, "can not get IRQ\n");
		goto err_free_master;
	}

	master->use_gpio_descriptors = true;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
	master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(4, 16);
	master->bus_num = dws->bus_num;
	master->num_chipselect = dws->num_cs;
	master->setup = dw_spi_setup;
	master->cleanup = dw_spi_cleanup;
	master->set_cs = dw_spi_set_cs;
	master->transfer_one = dw_spi_transfer_one;
	master->handle_err = dw_spi_handle_err;
	master->max_speed_hz = dws->max_freq;
	master->dev.of_node = dev->of_node;
	master->dev.fwnode = dev->fwnode;
	master->flags = SPI_MASTER_GPIO_SS;
	master->auto_runtime_pm = true;

	if (dws->set_cs)
		master->set_cs = dws->set_cs;

	/* Basic HW init */
	spi_hw_init(dev, dws);

	if (dws->dma_ops && dws->dma_ops->dma_init) {
		ret = dws->dma_ops->dma_init(dev, dws);
		if (ret) {
			dev_warn(dev, "DMA init failed\n");
		} else {
			master->can_dma = dws->dma_ops->can_dma;
			master->flags |= SPI_CONTROLLER_MUST_TX;
		}
	}

	ret = spi_register_controller(master);
	if (ret) {
		dev_err(&master->dev, "problem registering spi master\n");
		goto err_dma_exit;
	}

	dw_spi_debugfs_init(dws);
	return 0;

err_dma_exit:
	if (dws->dma_ops && dws->dma_ops->dma_exit)
		dws->dma_ops->dma_exit(dws);
	spi_enable_chip(dws, 0);
	free_irq(dws->irq, master);
err_free_master:
	spi_controller_put(master);
	return ret;
}
EXPORT_SYMBOL_GPL(dw_spi_add_host);

void dw_spi_remove_host(struct dw_spi *dws)
{
	dw_spi_debugfs_remove(dws);

	spi_unregister_controller(dws->master);

	if (dws->dma_ops && dws->dma_ops->dma_exit)
		dws->dma_ops->dma_exit(dws);

	spi_shutdown_chip(dws);

	free_irq(dws->irq, dws->master);
}
EXPORT_SYMBOL_GPL(dw_spi_remove_host);

int dw_spi_suspend_host(struct dw_spi *dws)
{
	int ret;

	ret = spi_controller_suspend(dws->master);
	if (ret)
		return ret;

	spi_shutdown_chip(dws);
	return 0;
}
EXPORT_SYMBOL_GPL(dw_spi_suspend_host);

int dw_spi_resume_host(struct dw_spi *dws)
{
	spi_hw_init(&dws->master->dev, dws);
	return spi_controller_resume(dws->master);
}
EXPORT_SYMBOL_GPL(dw_spi_resume_host);

MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2025cf9e	1	// SPDX-License-Identifier: GPL-2.0-only
e24c7452	2	/*
ca632f55	3	* Designware SPI core controller driver (refer pxa2xx_spi.c)
e24c7452 FT	4	*
e24c7452 FT	5	* Copyright (c) 2009, Intel Corporation.
e24c7452 FT	6	*/
	7
	8	#include <linux/dma-mapping.h>
	9	#include <linux/interrupt.h>
d7614de4	10	#include <linux/module.h>
e24c7452 FT	11	#include <linux/highmem.h>
e24c7452 FT	12	#include <linux/delay.h>
5a0e3ad6	13	#include <linux/slab.h>
e24c7452 FT	14	#include <linux/spi/spi.h>
e24c7452 FT	15
ca632f55	16	#include "spi-dw.h"
568a60ed	17
e24c7452 FT	18	#ifdef CONFIG_DEBUG_FS
	19	#include <linux/debugfs.h>
	20	#endif
	21
e24c7452 FT	22	/* Slave spi_dev related */
e24c7452 FT	23	struct chip_data {
e24c7452 FT	24	u8 tmode; /* TR/TO/RO/EEPROM */
	25	u8 type; /* SPI/SSP/MicroWire */
	26
e24c7452 FT	27	u16 clk_div; /* baud rate divider */
e24c7452 FT	28	u32 speed_hz; /* baud rate */
e24c7452 FT	29	};
	30
	31	#ifdef CONFIG_DEBUG_FS
8378449d SS	32
	33	#define DW_SPI_DBGFS_REG(_name, _off) \
	34	{ \
	35	.name = _name, \
	36	.offset = _off, \
e24c7452 FT	37	}
e24c7452 FT	38
8378449d SS	39	static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
	40	DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
	41	DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
	42	DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
	43	DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
	44	DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
	45	DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
	46	DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
	47	DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
	48	DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
	49	DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
	50	DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
	51	DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
	52	DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
	53	DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
	54	DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
e24c7452 FT	55	};
e24c7452 FT	56
53288fe9	57	static int dw_spi_debugfs_init(struct dw_spi *dws)
e24c7452	58	{
e70002c8	59	char name[32];
13288bdf	60
e70002c8	61	snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
13288bdf	62	dws->debugfs = debugfs_create_dir(name, NULL);
e24c7452 FT	63	if (!dws->debugfs)
	64	return -ENOMEM;
	65
8378449d SS	66	dws->regset.regs = dw_spi_dbgfs_regs;
	67	dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
	68	dws->regset.base = dws->regs;
	69	debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
	70
e24c7452 FT	71	return 0;
	72	}
	73
53288fe9	74	static void dw_spi_debugfs_remove(struct dw_spi *dws)
e24c7452	75	{
fadcace7	76	debugfs_remove_recursive(dws->debugfs);
e24c7452 FT	77	}
	78
	79	#else
53288fe9	80	static inline int dw_spi_debugfs_init(struct dw_spi *dws)
e24c7452	81	{
20a588fc	82	return 0;
e24c7452 FT	83	}
e24c7452 FT	84
53288fe9	85	static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
e24c7452 FT	86	{
	87	}
	88	#endif /* CONFIG_DEBUG_FS */
	89
c79bdbb4	90	void dw_spi_set_cs(struct spi_device *spi, bool enable)
c22c62db	91	{
721483e2	92	struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
9aea644c	93	bool cs_high = !!(spi->mode & SPI_CS_HIGH);
c22c62db	94
9aea644c SS	95	/*
	96	* DW SPI controller demands any native CS being set in order to
	97	* proceed with data transfer. So in order to activate the SPI
	98	* communications we must set a corresponding bit in the Slave
	99	* Enable register no matter whether the SPI core is configured to
	100	* support active-high or active-low CS level.
	101	*/
	102	if (cs_high == enable)
c22c62db	103	dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
f2d70479 TS	104	else if (dws->cs_override)
f2d70479 TS	105	dw_writel(dws, DW_SPI_SER, 0);
c22c62db	106	}
c79bdbb4	107	EXPORT_SYMBOL_GPL(dw_spi_set_cs);
c22c62db	108
2ff271bf AD	109	/* Return the max entries we can fill into tx fifo */
	110	static inline u32 tx_max(struct dw_spi *dws)
	111	{
	112	u32 tx_left, tx_room, rxtx_gap;
	113
	114	tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
dd114443	115	tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
2ff271bf AD	116
	117	/*
	118	* Another concern is about the tx/rx mismatch, we
	119	* though to use (dws->fifo_len - rxflr - txflr) as
	120	* one maximum value for tx, but it doesn't cover the
	121	* data which is out of tx/rx fifo and inside the
	122	* shift registers. So a control from sw point of
	123	* view is taken.
	124	*/
	125	rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
	126	/ dws->n_bytes;
	127
	128	return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
	129	}
	130
	131	/* Return the max entries we should read out of rx fifo */
	132	static inline u32 rx_max(struct dw_spi *dws)
	133	{
	134	u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
	135
dd114443	136	return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
2ff271bf AD	137	}
2ff271bf AD	138
3b8a4dd3	139	static void dw_writer(struct dw_spi *dws)
e24c7452	140	{
19b61392	141	u32 max;
de6efe0a	142	u16 txw = 0;
e24c7452	143
19b61392	144	spin_lock(&dws->buf_lock);
19b61392	145	max = tx_max(dws);
2ff271bf AD	146	while (max--) {
	147	/* Set the tx word if the transfer's original "tx" is not null */
	148	if (dws->tx_end - dws->len) {
	149	if (dws->n_bytes == 1)
	150	txw = (u8 )(dws->tx);
	151	else
	152	txw = (u16 )(dws->tx);
	153	}
c4fe57f7	154	dw_write_io_reg(dws, DW_SPI_DR, txw);
2ff271bf	155	dws->tx += dws->n_bytes;
e24c7452	156	}
19b61392	157	spin_unlock(&dws->buf_lock);
e24c7452 FT	158	}
e24c7452 FT	159
3b8a4dd3	160	static void dw_reader(struct dw_spi *dws)
e24c7452	161	{
19b61392	162	u32 max;
de6efe0a	163	u16 rxw;
e24c7452	164
19b61392	165	spin_lock(&dws->buf_lock);
19b61392	166	max = rx_max(dws);
2ff271bf	167	while (max--) {
c4fe57f7	168	rxw = dw_read_io_reg(dws, DW_SPI_DR);
de6efe0a FT	169	/* Care rx only if the transfer's original "rx" is not null */
	170	if (dws->rx_end - dws->len) {
	171	if (dws->n_bytes == 1)
	172	(u8 )(dws->rx) = rxw;
	173	else
	174	(u16 )(dws->rx) = rxw;
	175	}
	176	dws->rx += dws->n_bytes;
e24c7452	177	}
19b61392	178	spin_unlock(&dws->buf_lock);
e24c7452 FT	179	}
e24c7452 FT	180
e24c7452 FT	181	static void int_error_stop(struct dw_spi dws, const char msg)
e24c7452 FT	182	{
45746e82	183	spi_reset_chip(dws);
e24c7452 FT	184
e24c7452 FT	185	dev_err(&dws->master->dev, "%s\n", msg);
c22c62db AS	186	dws->master->cur_msg->status = -EIO;
c22c62db AS	187	spi_finalize_current_transfer(dws->master);
e24c7452 FT	188	}
e24c7452 FT	189
e24c7452 FT	190	static irqreturn_t interrupt_transfer(struct dw_spi *dws)
e24c7452 FT	191	{
dd114443	192	u16 irq_status = dw_readl(dws, DW_SPI_ISR);
e24c7452	193
e24c7452 FT	194	/* Error handling */
e24c7452 FT	195	if (irq_status & (SPI_INT_TXOI \| SPI_INT_RXOI \| SPI_INT_RXUI)) {
dd114443	196	dw_readl(dws, DW_SPI_ICR);
3b8a4dd3	197	int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
e24c7452 FT	198	return IRQ_HANDLED;
	199	}
	200
3b8a4dd3 AD	201	dw_reader(dws);
	202	if (dws->rx_end == dws->rx) {
	203	spi_mask_intr(dws, SPI_INT_TXEI);
c22c62db	204	spi_finalize_current_transfer(dws->master);
3b8a4dd3 AD	205	return IRQ_HANDLED;
3b8a4dd3 AD	206	}
552e4509 FT	207	if (irq_status & SPI_INT_TXEI) {
552e4509 FT	208	spi_mask_intr(dws, SPI_INT_TXEI);
3b8a4dd3 AD	209	dw_writer(dws);
	210	/* Enable TX irq always, it will be disabled when RX finished */
	211	spi_umask_intr(dws, SPI_INT_TXEI);
e24c7452 FT	212	}
e24c7452 FT	213
e24c7452 FT	214	return IRQ_HANDLED;
	215	}
	216
	217	static irqreturn_t dw_spi_irq(int irq, void *dev_id)
	218	{
721483e2 JN	219	struct spi_controller *master = dev_id;
721483e2 JN	220	struct dw_spi *dws = spi_controller_get_devdata(master);
dd114443	221	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
cbcc062a	222
cbcc062a YW	223	if (!irq_status)
cbcc062a YW	224	return IRQ_NONE;
e24c7452	225
c22c62db	226	if (!master->cur_msg) {
e24c7452	227	spi_mask_intr(dws, SPI_INT_TXEI);
e24c7452 FT	228	return IRQ_HANDLED;
	229	}
	230
	231	return dws->transfer_handler(dws);
	232	}
	233
c4eadee2 WAZ	234	/* Configure CTRLR0 for DW_apb_ssi */
	235	u32 dw_spi_update_cr0(struct spi_controller master, struct spi_device spi,
	236	struct spi_transfer *transfer)
e24c7452	237	{
c4eadee2 WAZ	238	struct chip_data *chip = spi_get_ctldata(spi);
c4eadee2 WAZ	239	u32 cr0;
e24c7452	240
c4eadee2 WAZ	241	/* Default SPI mode is SCPOL = 0, SCPH = 0 */
	242	cr0 = (transfer->bits_per_word - 1)
	243	\| (chip->type << SPI_FRF_OFFSET)
	244	\| ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) \|
	245	(((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) \|
	246	(((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
	247	\| (chip->tmode << SPI_TMOD_OFFSET);
	248
	249	return cr0;
	250	}
	251	EXPORT_SYMBOL_GPL(dw_spi_update_cr0);
	252
e539f435 WAZ	253	/* Configure CTRLR0 for DWC_ssi */
	254	u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
	255	struct spi_device *spi,
	256	struct spi_transfer *transfer)
	257	{
e539f435 WAZ	258	struct chip_data *chip = spi_get_ctldata(spi);
	259	u32 cr0;
	260
	261	/* CTRLR0[ 4: 0] Data Frame Size */
	262	cr0 = (transfer->bits_per_word - 1);
	263
	264	/* CTRLR0[ 7: 6] Frame Format */
	265	cr0 \|= chip->type << DWC_SSI_CTRLR0_FRF_OFFSET;
	266
	267	/*
	268	* SPI mode (SCPOL\|SCPH)
	269	* CTRLR0[ 8] Serial Clock Phase
	270	* CTRLR0[ 9] Serial Clock Polarity
	271	*/
	272	cr0 \|= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET;
	273	cr0 \|= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET;
	274
	275	/* CTRLR0[11:10] Transfer Mode */
	276	cr0 \|= chip->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET;
	277
	278	/* CTRLR0[13] Shift Register Loop */
	279	cr0 \|= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET;
	280
	281	return cr0;
e24c7452	282	}
e539f435	283	EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a);
e24c7452	284
721483e2	285	static int dw_spi_transfer_one(struct spi_controller *master,
c22c62db	286	struct spi_device spi, struct spi_transfer transfer)
e24c7452	287	{
721483e2	288	struct dw_spi *dws = spi_controller_get_devdata(master);
c22c62db	289	struct chip_data *chip = spi_get_ctldata(spi);
19b61392	290	unsigned long flags;
e24c7452	291	u8 imask = 0;
ea11370f	292	u16 txlevel = 0;
4adb1f8f	293	u32 cr0;
9f14538e	294	int ret;
e24c7452	295
f89a6d8f	296	dws->dma_mapped = 0;
19b61392	297	spin_lock_irqsave(&dws->buf_lock, flags);
e24c7452 FT	298	dws->tx = (void *)transfer->tx_buf;
	299	dws->tx_end = dws->tx + transfer->len;
	300	dws->rx = transfer->rx_buf;
	301	dws->rx_end = dws->rx + transfer->len;
c22c62db	302	dws->len = transfer->len;
19b61392	303	spin_unlock_irqrestore(&dws->buf_lock, flags);
e24c7452	304
bfda0445 XK	305	/* Ensure dw->rx and dw->rx_end are visible */
	306	smp_mb();
	307
0b2e8915 AS	308	spi_enable_chip(dws, 0);
0b2e8915 AS	309
e24c7452	310	/* Handle per transfer options for bpw and speed */
13b10301 MS	311	if (transfer->speed_hz != dws->current_freq) {
	312	if (transfer->speed_hz != chip->speed_hz) {
	313	/* clk_div doesn't support odd number */
3aef4632	314	chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
13b10301 MS	315	chip->speed_hz = transfer->speed_hz;
	316	}
	317	dws->current_freq = transfer->speed_hz;
0ed36990	318	spi_set_clk(dws, chip->clk_div);
e24c7452	319	}
af060b3f	320
de4c2875	321	transfer->effective_speed_hz = dws->max_freq / chip->clk_div;
af060b3f	322	dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
052dc7c4	323
c4eadee2	324	cr0 = dws->update_cr0(master, spi, transfer);
299cb65c	325	dw_writel(dws, DW_SPI_CTRLR0, cr0);
0b2e8915	326
e24c7452	327	/* Check if current transfer is a DMA transaction */
f89a6d8f AS	328	if (master->can_dma && master->can_dma(master, spi, transfer))
f89a6d8f AS	329	dws->dma_mapped = master->cur_msg_mapped;
e24c7452	330
0b2e8915 AS	331	/* For poll mode just disable all interrupts */
	332	spi_mask_intr(dws, 0xff);
	333
552e4509 FT	334	/*
	335	* Interrupt mode
	336	* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
	337	*/
9f14538e	338	if (dws->dma_mapped) {
f89a6d8f	339	ret = dws->dma_ops->dma_setup(dws, transfer);
9f14538e AS	340	if (ret < 0) {
	341	spi_enable_chip(dws, 1);
	342	return ret;
	343	}
33e8fd4b	344	} else {
ea11370f	345	txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
299cb65c	346	dw_writel(dws, DW_SPI_TXFTLR, txlevel);
552e4509	347
0b2e8915	348	/* Set the interrupt mask */
fadcace7 JH	349	imask \|= SPI_INT_TXEI \| SPI_INT_TXOI \|
fadcace7 JH	350	SPI_INT_RXUI \| SPI_INT_RXOI;
0b2e8915 AS	351	spi_umask_intr(dws, imask);
0b2e8915 AS	352
e24c7452 FT	353	dws->transfer_handler = interrupt_transfer;
	354	}
	355
0b2e8915	356	spi_enable_chip(dws, 1);
e24c7452	357
f0410bbf SS	358	if (dws->dma_mapped)
f0410bbf SS	359	return dws->dma_ops->dma_transfer(dws, transfer);
e24c7452	360
c22c62db	361	return 1;
e24c7452 FT	362	}
e24c7452 FT	363
721483e2	364	static void dw_spi_handle_err(struct spi_controller *master,
ec37e8e1	365	struct spi_message *msg)
e24c7452	366	{
721483e2	367	struct dw_spi *dws = spi_controller_get_devdata(master);
e24c7452	368
4d5ac1ed AS	369	if (dws->dma_mapped)
	370	dws->dma_ops->dma_stop(dws);
	371
c22c62db	372	spi_reset_chip(dws);
e24c7452 FT	373	}
	374
	375	/* This may be called twice for each spi dev */
	376	static int dw_spi_setup(struct spi_device *spi)
	377	{
e24c7452 FT	378	struct chip_data *chip;
e24c7452 FT	379
e24c7452 FT	380	/* Only alloc on first setup */
	381	chip = spi_get_ctldata(spi);
	382	if (!chip) {
a97c883a	383	chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
e24c7452 FT	384	if (!chip)
e24c7452 FT	385	return -ENOMEM;
43f627ac	386	spi_set_ctldata(spi, chip);
e24c7452 FT	387	}
e24c7452 FT	388
6096828e	389	chip->tmode = SPI_TMOD_TR;
c3ce15bf	390
e24c7452 FT	391	return 0;
	392	}
	393
a97c883a AL	394	static void dw_spi_cleanup(struct spi_device *spi)
	395	{
	396	struct chip_data *chip = spi_get_ctldata(spi);
	397
	398	kfree(chip);
	399	spi_set_ctldata(spi, NULL);
	400	}
	401
e24c7452	402	/* Restart the controller, disable all interrupts, clean rx fifo */
30b4b703	403	static void spi_hw_init(struct device dev, struct dw_spi dws)
e24c7452	404	{
45746e82	405	spi_reset_chip(dws);
c587b6fa FT	406
	407	/*
	408	* Try to detect the FIFO depth if not set by interface driver,
	409	* the depth could be from 2 to 256 from HW spec
	410	*/
	411	if (!dws->fifo_len) {
	412	u32 fifo;
fadcace7	413
9d239d35	414	for (fifo = 1; fifo < 256; fifo++) {
299cb65c WAZ	415	dw_writel(dws, DW_SPI_TXFTLR, fifo);
299cb65c WAZ	416	if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
c587b6fa FT	417	break;
c587b6fa FT	418	}
299cb65c	419	dw_writel(dws, DW_SPI_TXFTLR, 0);
c587b6fa	420
9d239d35	421	dws->fifo_len = (fifo == 1) ? 0 : fifo;
30b4b703	422	dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
c587b6fa	423	}
f2d70479 TS	424
	425	/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
	426	if (dws->cs_override)
	427	dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
e24c7452 FT	428	}
e24c7452 FT	429
04f421e7	430	int dw_spi_add_host(struct device dev, struct dw_spi dws)
e24c7452	431	{
721483e2	432	struct spi_controller *master;
e24c7452 FT	433	int ret;
e24c7452 FT	434
169f9aca AP	435	if (!dws)
169f9aca AP	436	return -EINVAL;
e24c7452	437
04f421e7 BS	438	master = spi_alloc_master(dev, 0);
	439	if (!master)
	440	return -ENOMEM;
e24c7452 FT	441
	442	dws->master = master;
	443	dws->type = SSI_MOTO_SPI;
d7ef54ca	444	dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
19b61392	445	spin_lock_init(&dws->buf_lock);
e24c7452	446
66b19d76 AB	447	spi_controller_set_devdata(master, dws);
66b19d76 AB	448
e70002c8 PR	449	ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
e70002c8 PR	450	master);
e24c7452	451	if (ret < 0) {
5f0966e6	452	dev_err(dev, "can not get IRQ\n");
e24c7452 FT	453	goto err_free_master;
	454	}
	455
9400c41e	456	master->use_gpio_descriptors = true;
c3ce15bf	457	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP;
af060b3f	458	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
e24c7452 FT	459	master->bus_num = dws->bus_num;
e24c7452 FT	460	master->num_chipselect = dws->num_cs;
e24c7452	461	master->setup = dw_spi_setup;
a97c883a	462	master->cleanup = dw_spi_cleanup;
c22c62db AS	463	master->set_cs = dw_spi_set_cs;
	464	master->transfer_one = dw_spi_transfer_one;
	465	master->handle_err = dw_spi_handle_err;
765ee709	466	master->max_speed_hz = dws->max_freq;
9c6de47d	467	master->dev.of_node = dev->of_node;
32215a6c	468	master->dev.fwnode = dev->fwnode;
80b444e5	469	master->flags = SPI_MASTER_GPIO_SS;
1e695983	470	master->auto_runtime_pm = true;
e24c7452	471
62dbbae4 AB	472	if (dws->set_cs)
	473	master->set_cs = dws->set_cs;
	474
e24c7452	475	/* Basic HW init */
30b4b703	476	spi_hw_init(dev, dws);
e24c7452	477
7063c0d9	478	if (dws->dma_ops && dws->dma_ops->dma_init) {
6370abab	479	ret = dws->dma_ops->dma_init(dev, dws);
7063c0d9	480	if (ret) {
3dbb3b98	481	dev_warn(dev, "DMA init failed\n");
f89a6d8f AS	482	} else {
f89a6d8f AS	483	master->can_dma = dws->dma_ops->can_dma;
46164fde	484	master->flags \|= SPI_CONTROLLER_MUST_TX;
7063c0d9 FT	485	}
	486	}
	487
ca8b19d6	488	ret = spi_register_controller(master);
e24c7452 FT	489	if (ret) {
e24c7452 FT	490	dev_err(&master->dev, "problem registering spi master\n");
ec37e8e1	491	goto err_dma_exit;
e24c7452 FT	492	}
e24c7452 FT	493
53288fe9	494	dw_spi_debugfs_init(dws);
e24c7452 FT	495	return 0;
e24c7452 FT	496
ec37e8e1	497	err_dma_exit:
7063c0d9 FT	498	if (dws->dma_ops && dws->dma_ops->dma_exit)
7063c0d9 FT	499	dws->dma_ops->dma_exit(dws);
e24c7452	500	spi_enable_chip(dws, 0);
02f20387	501	free_irq(dws->irq, master);
e24c7452	502	err_free_master:
721483e2	503	spi_controller_put(master);
e24c7452 FT	504	return ret;
e24c7452 FT	505	}
79290a2a	506	EXPORT_SYMBOL_GPL(dw_spi_add_host);
e24c7452	507
fd4a319b	508	void dw_spi_remove_host(struct dw_spi *dws)
e24c7452	509	{
53288fe9	510	dw_spi_debugfs_remove(dws);
e24c7452	511
ca8b19d6 LW	512	spi_unregister_controller(dws->master);
ca8b19d6 LW	513
7063c0d9 FT	514	if (dws->dma_ops && dws->dma_ops->dma_exit)
7063c0d9 FT	515	dws->dma_ops->dma_exit(dws);
1cc3f141 AS	516
1cc3f141 AS	517	spi_shutdown_chip(dws);
02f20387 AS	518
02f20387 AS	519	free_irq(dws->irq, dws->master);
e24c7452	520	}
79290a2a	521	EXPORT_SYMBOL_GPL(dw_spi_remove_host);
e24c7452 FT	522
	523	int dw_spi_suspend_host(struct dw_spi *dws)
	524	{
1cc3f141	525	int ret;
e24c7452	526
721483e2	527	ret = spi_controller_suspend(dws->master);
e24c7452 FT	528	if (ret)
e24c7452 FT	529	return ret;
1cc3f141 AS	530
	531	spi_shutdown_chip(dws);
	532	return 0;
e24c7452	533	}
79290a2a	534	EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
e24c7452 FT	535
	536	int dw_spi_resume_host(struct dw_spi *dws)
	537	{
30b4b703	538	spi_hw_init(&dws->master->dev, dws);
7c5d8a24	539	return spi_controller_resume(dws->master);
e24c7452	540	}
79290a2a	541	EXPORT_SYMBOL_GPL(dw_spi_resume_host);
e24c7452 FT	542
	543	MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
	544	MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
	545	MODULE_LICENSE("GPL v2");