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Merge tag 'pm-5.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[linux-2.6-block.git] / drivers / spi / spi-dln2.c
CommitLineData
a10e763b 1// SPDX-License-Identifier: GPL-2.0-only
3d8c0d74
LP		 2/*
3 * Driver for the Diolan DLN-2 USB-SPI adapter
4 *
5 * Copyright (c) 2014 Intel Corporation
3d8c0d74
LP		 6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/mfd/dln2.h>
12#include <linux/spi/spi.h>
13#include <linux/pm_runtime.h>
14#include <asm/unaligned.h>
15
16#define DLN2_SPI_MODULE_ID 0x02
17#define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
18
19/* SPI commands */
20#define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00)
21#define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11)
22#define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12)
23#define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13)
24#define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14)
25#define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15)
26#define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16)
27#define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17)
28#define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18)
29#define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19)
30#define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A)
31#define DLN2_SPI_READ DLN2_SPI_CMD(0x1B)
32#define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C)
33#define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20)
34#define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21)
35#define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22)
36#define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23)
37#define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24)
38#define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25)
39#define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26)
40#define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27)
41#define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28)
42#define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B)
43#define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C)
44#define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D)
45#define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E)
46#define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F)
47#define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30)
48#define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31)
49#define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32)
50#define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33)
51#define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34)
52#define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35)
53#define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36)
54#define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37)
55#define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38)
56#define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39)
57#define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A)
58#define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40)
59#define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41)
60#define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42)
61#define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43)
62#define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44)
63#define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45)
64#define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46)
65#define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47)
66#define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48)
67#define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49)
68#define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A)
69#define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B)
70#define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C)
71
72#define DLN2_SPI_MAX_XFER_SIZE 256
73#define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16)
74#define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0)
75#define DLN2_TRANSFERS_WAIT_COMPLETE 1
76#define DLN2_TRANSFERS_CANCEL 0
77#define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000
78
79struct dln2_spi {
80 struct platform_device *pdev;
81 struct spi_master *master;
82 u8 port;
83
84 /*
85 * This buffer will be used mainly for read/write operations. Since
86 * they're quite large, we cannot use the stack. Protection is not
87 * needed because all SPI communication is serialized by the SPI core.
88 */
89 void *buf;
90
91 u8 bpw;
92 u32 speed;
93 u16 mode;
94 u8 cs;
95};
96
97/*
98 * Enable/Disable SPI module. The disable command will wait for transfers to
99 * complete first.
100 */
101static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
102{
3d8c0d74
LP		 103 u16 cmd;
104 struct {
105 u8 port;
106 u8 wait_for_completion;
107 } tx;
108 unsigned len = sizeof(tx);
109
110 tx.port = dln2->port;
111
112 if (enable) {
113 cmd = DLN2_SPI_ENABLE;
114 len -= sizeof(tx.wait_for_completion);
115 } else {
116 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
117 cmd = DLN2_SPI_DISABLE;
118 }
119
2b5e368e 120 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
3d8c0d74
LP		 121}
122
123/*
124 * Select/unselect multiple CS lines. The selected lines will be automatically
125 * toggled LOW/HIGH by the board firmware during transfers, provided they're
126 * enabled first.
127 *
128 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
129 * will toggle the lines LOW/HIGH automatically.
130 */
131static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
132{
133 struct {
134 u8 port;
135 u8 cs;
136 } tx;
137
138 tx.port = dln2->port;
139
140 /*
141 * According to Diolan docs, "a slave device can be selected by changing
142 * the corresponding bit value to 0". The rest must be set to 1. Hence
143 * the bitwise NOT in front.
144 */
145 tx.cs = ~cs_mask;
146
147 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
148}
149
150/*
151 * Select one CS line. The other lines will be un-selected.
152 */
153static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
154{
155 return dln2_spi_cs_set(dln2, BIT(cs));
156}
157
158/*
159 * Enable/disable CS lines for usage. The module has to be disabled first.
160 */
161static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
162{
163 struct {
164 u8 port;
165 u8 cs;
166 } tx;
167 u16 cmd;
168
169 tx.port = dln2->port;
170 tx.cs = cs_mask;
171 cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
172
173 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
174}
175
176static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
177{
178 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
179
180 return dln2_spi_cs_enable(dln2, cs_mask, enable);
181}
182
183static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
184{
185 int ret;
186 struct {
187 u8 port;
188 } tx;
189 struct {
190 __le16 cs_count;
191 } rx;
192 unsigned rx_len = sizeof(rx);
193
194 tx.port = dln2->port;
195 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
196 &rx, &rx_len);
197 if (ret < 0)
198 return ret;
199 if (rx_len < sizeof(rx))
200 return -EPROTO;
201
202 *cs_num = le16_to_cpu(rx.cs_count);
203
204 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
205
206 return 0;
207}
208
209static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
210{
211 int ret;
212 struct {
213 u8 port;
214 } tx;
215 struct {
216 __le32 speed;
217 } rx;
218 unsigned rx_len = sizeof(rx);
219
220 tx.port = dln2->port;
221
222 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
223 if (ret < 0)
224 return ret;
225 if (rx_len < sizeof(rx))
226 return -EPROTO;
227
228 *freq = le32_to_cpu(rx.speed);
229
230 return 0;
231}
232
233/*
234 * Get bus min/max frequencies.
235 */
236static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
237{
238 int ret;
239
240 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
241 if (ret < 0)
242 return ret;
243
244 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
245 if (ret < 0)
246 return ret;
247
248 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
249 *fmin, *fmax);
250
251 return 0;
252}
253
254/*
255 * Set the bus speed. The module will automatically round down to the closest
256 * available frequency and returns it. The module has to be disabled first.
257 */
258static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
259{
260 int ret;
261 struct {
262 u8 port;
263 __le32 speed;
264 } __packed tx;
265 struct {
266 __le32 speed;
267 } rx;
268 int rx_len = sizeof(rx);
269
270 tx.port = dln2->port;
271 tx.speed = cpu_to_le32(speed);
272
273 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
274 &rx, &rx_len);
275 if (ret < 0)
276 return ret;
277 if (rx_len < sizeof(rx))
278 return -EPROTO;
279
280 return 0;
281}
282
283/*
284 * Change CPOL & CPHA. The module has to be disabled first.
285 */
286static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
287{
288 struct {
289 u8 port;
290 u8 mode;
291 } tx;
292
293 tx.port = dln2->port;
294 tx.mode = mode;
295
296 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
297}
298
299/*
300 * Change frame size. The module has to be disabled first.
301 */
302static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
303{
304 struct {
305 u8 port;
306 u8 bpw;
307 } tx;
308
309 tx.port = dln2->port;
310 tx.bpw = bpw;
311
312 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
313 &tx, sizeof(tx));
314}
315
316static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
317 u32 *bpw_mask)
318{
319 int ret;
320 struct {
321 u8 port;
322 } tx;
323 struct {
324 u8 count;
325 u8 frame_sizes[36];
326 } *rx = dln2->buf;
327 unsigned rx_len = sizeof(*rx);
328 int i;
329
330 tx.port = dln2->port;
331
332 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
333 &tx, sizeof(tx), rx, &rx_len);
334 if (ret < 0)
335 return ret;
336 if (rx_len < sizeof(*rx))
337 return -EPROTO;
338 if (rx->count > ARRAY_SIZE(rx->frame_sizes))
339 return -EPROTO;
340
341 *bpw_mask = 0;
342 for (i = 0; i < rx->count; i++)
343 *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
344
345 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
346
347 return 0;
348}
349
350/*
351 * Copy the data to DLN2 buffer and change the byte order to LE, requested by
352 * DLN2 module. SPI core makes sure that the data length is a multiple of word
353 * size.
354 */
355static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
356{
357#ifdef __LITTLE_ENDIAN
358 memcpy(dln2_buf, src, len);
359#else
360 if (bpw <= 8) {
361 memcpy(dln2_buf, src, len);
362 } else if (bpw <= 16) {
363 __le16 *d = (__le16 *)dln2_buf;
364 u16 *s = (u16 *)src;
365
366 len = len / 2;
367 while (len--)
368 *d++ = cpu_to_le16p(s++);
369 } else {
370 __le32 *d = (__le32 *)dln2_buf;
371 u32 *s = (u32 *)src;
372
373 len = len / 4;
374 while (len--)
375 *d++ = cpu_to_le32p(s++);
376 }
377#endif
378
379 return 0;
380}
381
382/*
383 * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
384 * buffer is LE ordered. SPI core makes sure that the data length is a multiple
385 * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
386 * sure we avoid unaligned accesses for 32 bit case.
387 */
388static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
389{
390#ifdef __LITTLE_ENDIAN
391 memcpy(dest, dln2_buf, len);
392#else
393 if (bpw <= 8) {
394 memcpy(dest, dln2_buf, len);
395 } else if (bpw <= 16) {
396 u16 *d = (u16 *)dest;
397 __le16 *s = (__le16 *)dln2_buf;
398
399 len = len / 2;
400 while (len--)
401 *d++ = le16_to_cpup(s++);
402 } else {
403 u32 *d = (u32 *)dest;
404 __le32 *s = (__le32 *)dln2_buf;
405
406 len = len / 4;
407 while (len--)
408 *d++ = get_unaligned_le32(s++);
409 }
410#endif
411
412 return 0;
413}
414
415/*
416 * Perform one write operation.
417 */
418static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
419 u16 data_len, u8 attr)
420{
421 struct {
422 u8 port;
423 __le16 size;
424 u8 attr;
425 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
426 } __packed *tx = dln2->buf;
427 unsigned tx_len;
428
429 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
430
431 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
432 return -EINVAL;
433
434 tx->port = dln2->port;
435 tx->size = cpu_to_le16(data_len);
436 tx->attr = attr;
437
438 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
439
440 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
441 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
442}
443
444/*
445 * Perform one read operation.
446 */
447static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
448 u16 data_len, u8 attr)
449{
450 int ret;
451 struct {
452 u8 port;
453 __le16 size;
454 u8 attr;
455 } __packed tx;
456 struct {
457 __le16 size;
458 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
459 } __packed *rx = dln2->buf;
460 unsigned rx_len = sizeof(*rx);
461
462 BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
463
464 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
465 return -EINVAL;
466
467 tx.port = dln2->port;
468 tx.size = cpu_to_le16(data_len);
469 tx.attr = attr;
470
471 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
472 rx, &rx_len);
473 if (ret < 0)
474 return ret;
475 if (rx_len < sizeof(rx->size) + data_len)
476 return -EPROTO;
477 if (le16_to_cpu(rx->size) != data_len)
478 return -EPROTO;
479
480 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
481
482 return 0;
483}
484
485/*
486 * Perform one write & read operation.
487 */
488static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
489 u8 *rx_data, u16 data_len, u8 attr)
490{
491 int ret;
492 struct {
493 u8 port;
494 __le16 size;
495 u8 attr;
496 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
497 } __packed *tx;
498 struct {
499 __le16 size;
500 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
501 } __packed *rx;
502 unsigned tx_len, rx_len;
503
504 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
505 sizeof(*rx) > DLN2_SPI_BUF_SIZE);
506
507 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
508 return -EINVAL;
509
510 /*
511 * Since this is a pseudo full-duplex communication, we're perfectly
512 * safe to use the same buffer for both tx and rx. When DLN2 sends the
513 * response back, with the rx data, we don't need the tx buffer anymore.
514 */
515 tx = dln2->buf;
516 rx = dln2->buf;
517
518 tx->port = dln2->port;
519 tx->size = cpu_to_le16(data_len);
520 tx->attr = attr;
521
522 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
523
524 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
525 rx_len = sizeof(*rx);
526
527 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
528 rx, &rx_len);
529 if (ret < 0)
530 return ret;
531 if (rx_len < sizeof(rx->size) + data_len)
532 return -EPROTO;
533 if (le16_to_cpu(rx->size) != data_len)
534 return -EPROTO;
535
536 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
537
538 return 0;
539}
540
541/*
542 * Read/Write wrapper. It will automatically split an operation into multiple
543 * single ones due to device buffer constraints.
544 */
545static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
546 u8 *rx_data, u16 data_len, u8 attr) {
547 int ret;
548 u16 len;
549 u8 temp_attr;
550 u16 remaining = data_len;
551 u16 offset;
552
553 do {
554 if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
555 len = DLN2_SPI_MAX_XFER_SIZE;
556 temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
557 } else {
558 len = remaining;
559 temp_attr = attr;
560 }
561
562 offset = data_len - remaining;
563
564 if (tx_data && rx_data) {
565 ret = dln2_spi_read_write_one(dln2,
566 tx_data + offset,
567 rx_data + offset,
568 len, temp_attr);
569 } else if (tx_data) {
570 ret = dln2_spi_write_one(dln2,
571 tx_data + offset,
572 len, temp_attr);
573 } else if (rx_data) {
574 ret = dln2_spi_read_one(dln2,
575 rx_data + offset,
576 len, temp_attr);
577 } else {
578 return -EINVAL;
579 }
580
581 if (ret < 0)
582 return ret;
583
584 remaining -= len;
585 } while (remaining);
586
587 return 0;
588}
589
590static int dln2_spi_prepare_message(struct spi_master *master,
591 struct spi_message *message)
592{
593 int ret;
594 struct dln2_spi *dln2 = spi_master_get_devdata(master);
595 struct spi_device *spi = message->spi;
596
597 if (dln2->cs != spi->chip_select) {
598 ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
599 if (ret < 0)
600 return ret;
601
602 dln2->cs = spi->chip_select;
603 }
604
605 return 0;
606}
607
608static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
609 u8 bpw, u8 mode)
610{
611 int ret;
612 bool bus_setup_change;
613
614 bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
615 dln2->bpw != bpw;
616
617 if (!bus_setup_change)
618 return 0;
619
620 ret = dln2_spi_enable(dln2, false);
621 if (ret < 0)
622 return ret;
623
624 if (dln2->speed != speed) {
625 ret = dln2_spi_set_speed(dln2, speed);
626 if (ret < 0)
627 return ret;
628
629 dln2->speed = speed;
630 }
631
632 if (dln2->mode != mode) {
633 ret = dln2_spi_set_mode(dln2, mode & 0x3);
634 if (ret < 0)
635 return ret;
636
637 dln2->mode = mode;
638 }
639
640 if (dln2->bpw != bpw) {
641 ret = dln2_spi_set_bpw(dln2, bpw);
642 if (ret < 0)
643 return ret;
644
645 dln2->bpw = bpw;
646 }
647
2b5e368e 648 return dln2_spi_enable(dln2, true);
3d8c0d74
LP		 649}
650
651static int dln2_spi_transfer_one(struct spi_master *master,
652 struct spi_device *spi,
653 struct spi_transfer *xfer)
654{
655 struct dln2_spi *dln2 = spi_master_get_devdata(master);
656 int status;
657 u8 attr = 0;
658
659 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
660 xfer->bits_per_word,
661 spi->mode);
662 if (status < 0) {
663 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
664 return status;
665 }
666
667 if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
668 attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
669
670 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
671 xfer->len, attr);
672 if (status < 0)
673 dev_err(&dln2->pdev->dev, "write/read failed!\n");
674
675 return status;
676}
677
678static int dln2_spi_probe(struct platform_device *pdev)
679{
680 struct spi_master *master;
681 struct dln2_spi *dln2;
682 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
83835fb0 683 struct device *dev = &pdev->dev;
3d8c0d74
LP		 684 int ret;
685
686 master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
687 if (!master)
688 return -ENOMEM;
689
690 platform_set_drvdata(pdev, master);
691
692 dln2 = spi_master_get_devdata(master);
693
694 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
695 if (!dln2->buf) {
696 ret = -ENOMEM;
697 goto exit_free_master;
698 }
699
700 dln2->master = master;
83835fb0 701 dln2->master->dev.of_node = dev->of_node;
3d8c0d74
LP		 702 dln2->pdev = pdev;
703 dln2->port = pdata->port;
704 /* cs/mode can never be 0xff, so the first transfer will set them */
705 dln2->cs = 0xff;
706 dln2->mode = 0xff;
707
708 /* disable SPI module before continuing with the setup */
709 ret = dln2_spi_enable(dln2, false);
710 if (ret < 0) {
711 dev_err(&pdev->dev, "Failed to disable SPI module\n");
712 goto exit_free_master;
713 }
714
715 ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
716 if (ret < 0) {
717 dev_err(&pdev->dev, "Failed to get number of CS pins\n");
718 goto exit_free_master;
719 }
720
721 ret = dln2_spi_get_speed_range(dln2,
722 &master->min_speed_hz,
723 &master->max_speed_hz);
724 if (ret < 0) {
725 dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
726 goto exit_free_master;
727 }
728
729 ret = dln2_spi_get_supported_frame_sizes(dln2,
730 &master->bits_per_word_mask);
731 if (ret < 0) {
732 dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
733 goto exit_free_master;
734 }
735
736 ret = dln2_spi_cs_enable_all(dln2, true);
737 if (ret < 0) {
738 dev_err(&pdev->dev, "Failed to enable CS pins\n");
739 goto exit_free_master;
740 }
741
742 master->bus_num = -1;
743 master->mode_bits = SPI_CPOL | SPI_CPHA;
744 master->prepare_message = dln2_spi_prepare_message;
745 master->transfer_one = dln2_spi_transfer_one;
746 master->auto_runtime_pm = true;
747
748 /* enable SPI module, we're good to go */
749 ret = dln2_spi_enable(dln2, true);
750 if (ret < 0) {
751 dev_err(&pdev->dev, "Failed to enable SPI module\n");
752 goto exit_free_master;
753 }
754
755 pm_runtime_set_autosuspend_delay(&pdev->dev,
756 DLN2_RPM_AUTOSUSPEND_TIMEOUT);
757 pm_runtime_use_autosuspend(&pdev->dev);
758 pm_runtime_set_active(&pdev->dev);
759 pm_runtime_enable(&pdev->dev);
760
761 ret = devm_spi_register_master(&pdev->dev, master);
762 if (ret < 0) {
763 dev_err(&pdev->dev, "Failed to register master\n");
764 goto exit_register;
765 }
766
767 return ret;
768
769exit_register:
770 pm_runtime_disable(&pdev->dev);
771 pm_runtime_set_suspended(&pdev->dev);
772
773 if (dln2_spi_enable(dln2, false) < 0)
774 dev_err(&pdev->dev, "Failed to disable SPI module\n");
775exit_free_master:
776 spi_master_put(master);
777
778 return ret;
779}
780
781static int dln2_spi_remove(struct platform_device *pdev)
782{
783 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
784 struct dln2_spi *dln2 = spi_master_get_devdata(master);
785
786 pm_runtime_disable(&pdev->dev);
787
788 if (dln2_spi_enable(dln2, false) < 0)
789 dev_err(&pdev->dev, "Failed to disable SPI module\n");
790
791 return 0;
792}
793
794#ifdef CONFIG_PM_SLEEP
795static int dln2_spi_suspend(struct device *dev)
796{
797 int ret;
798 struct spi_master *master = dev_get_drvdata(dev);
799 struct dln2_spi *dln2 = spi_master_get_devdata(master);
800
801 ret = spi_master_suspend(master);
802 if (ret < 0)
803 return ret;
804
805 if (!pm_runtime_suspended(dev)) {
806 ret = dln2_spi_enable(dln2, false);
807 if (ret < 0)
808 return ret;
809 }
810
811 /*
812 * USB power may be cut off during sleep. Resetting the following
813 * parameters will force the board to be set up before first transfer.
814 */
815 dln2->cs = 0xff;
816 dln2->speed = 0;
817 dln2->bpw = 0;
818 dln2->mode = 0xff;
819
820 return 0;
821}
822
823static int dln2_spi_resume(struct device *dev)
824{
825 int ret;
826 struct spi_master *master = dev_get_drvdata(dev);
827 struct dln2_spi *dln2 = spi_master_get_devdata(master);
828
829 if (!pm_runtime_suspended(dev)) {
830 ret = dln2_spi_cs_enable_all(dln2, true);
831 if (ret < 0)
832 return ret;
833
834 ret = dln2_spi_enable(dln2, true);
835 if (ret < 0)
836 return ret;
837 }
838
839 return spi_master_resume(master);
840}
841#endif /* CONFIG_PM_SLEEP */
842
b2e5dda1 843#ifdef CONFIG_PM
3d8c0d74
LP		 844static int dln2_spi_runtime_suspend(struct device *dev)
845{
846 struct spi_master *master = dev_get_drvdata(dev);
847 struct dln2_spi *dln2 = spi_master_get_devdata(master);
848
849 return dln2_spi_enable(dln2, false);
850}
851
852static int dln2_spi_runtime_resume(struct device *dev)
853{
854 struct spi_master *master = dev_get_drvdata(dev);
855 struct dln2_spi *dln2 = spi_master_get_devdata(master);
856
857 return dln2_spi_enable(dln2, true);
858}
2b5e368e 859#endif /* CONFIG_PM */
3d8c0d74
LP		 860
861static const struct dev_pm_ops dln2_spi_pm = {
862 SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
863 SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
864 dln2_spi_runtime_resume, NULL)
865};
866
867static struct platform_driver spi_dln2_driver = {
868 .driver = {
869 .name = "dln2-spi",
870 .pm = &dln2_spi_pm,
871 },
872 .probe = dln2_spi_probe,
873 .remove = dln2_spi_remove,
874};
875module_platform_driver(spi_dln2_driver);
876
877MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
878MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
879MODULE_LICENSE("GPL v2");
880MODULE_ALIAS("platform:dln2-spi");
Linux 6.x block layer and io_uring tree(s)