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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 3 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
358934a6 SP |
14 | */ |
15 | ||
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/clk.h> | |
048177ce | 24 | #include <linux/dmaengine.h> |
358934a6 | 25 | #include <linux/dma-mapping.h> |
aae7147d MK |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
a88e34ea | 28 | #include <linux/of_gpio.h> |
358934a6 SP |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
358934a6 | 32 | |
ec2a0833 | 33 | #include <linux/platform_data/spi-davinci.h> |
358934a6 | 34 | |
358934a6 SP |
35 | #define CS_DEFAULT 0xFF |
36 | ||
358934a6 SP |
37 | #define SPIFMT_PHASE_MASK BIT(16) |
38 | #define SPIFMT_POLARITY_MASK BIT(17) | |
39 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
40 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
41 | #define SPIFMT_WAITENA_MASK BIT(21) | |
42 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
43 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
44 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
45 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 46 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 47 | |
358934a6 SP |
48 | /* SPIPC0 */ |
49 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
50 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
51 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
52 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
53 | |
54 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
55 | #define SPIINT_MASKINT 0x0000015F |
56 | #define SPI_INTLVL_1 0x000001FF | |
57 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 58 | |
cfbc5d1d BN |
59 | /* SPIDAT1 (upper 16 bit defines) */ |
60 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
365a7bb3 | 61 | #define SPIDAT1_WDEL BIT(10) |
cfbc5d1d BN |
62 | |
63 | /* SPIGCR1 */ | |
358934a6 SP |
64 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
65 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 66 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 67 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 68 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
69 | |
70 | /* SPIBUF */ | |
71 | #define SPIBUF_TXFULL_MASK BIT(29) | |
72 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
73 | ||
7abbf23c BN |
74 | /* SPIDELAY */ |
75 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
76 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
77 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
78 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
79 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
80 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
81 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
82 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
83 | ||
358934a6 SP |
84 | /* Error Masks */ |
85 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
86 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
87 | #define SPIFLG_PARERR_MASK BIT(2) | |
88 | #define SPIFLG_DESYNC_MASK BIT(3) | |
89 | #define SPIFLG_BITERR_MASK BIT(4) | |
90 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 91 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
92 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
93 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
94 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
95 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 96 | |
358934a6 | 97 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 98 | |
358934a6 SP |
99 | /* SPI Controller registers */ |
100 | #define SPIGCR0 0x00 | |
101 | #define SPIGCR1 0x04 | |
102 | #define SPIINT 0x08 | |
103 | #define SPILVL 0x0c | |
104 | #define SPIFLG 0x10 | |
105 | #define SPIPC0 0x14 | |
358934a6 SP |
106 | #define SPIDAT1 0x3c |
107 | #define SPIBUF 0x40 | |
358934a6 SP |
108 | #define SPIDELAY 0x48 |
109 | #define SPIDEF 0x4c | |
110 | #define SPIFMT0 0x50 | |
358934a6 | 111 | |
0718b764 FI |
112 | #define DMA_MIN_BYTES 16 |
113 | ||
358934a6 SP |
114 | /* SPI Controller driver's private data. */ |
115 | struct davinci_spi { | |
116 | struct spi_bitbang bitbang; | |
117 | struct clk *clk; | |
118 | ||
119 | u8 version; | |
120 | resource_size_t pbase; | |
121 | void __iomem *base; | |
e0d205e9 BN |
122 | u32 irq; |
123 | struct completion done; | |
358934a6 SP |
124 | |
125 | const void *tx; | |
126 | void *rx; | |
e0d205e9 BN |
127 | int rcount; |
128 | int wcount; | |
048177ce MP |
129 | |
130 | struct dma_chan *dma_rx; | |
131 | struct dma_chan *dma_tx; | |
048177ce | 132 | |
aae7147d | 133 | struct davinci_spi_platform_data pdata; |
358934a6 SP |
134 | |
135 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
136 | u32 (*get_tx)(struct davinci_spi *); | |
137 | ||
7480e755 | 138 | u8 *bytes_per_word; |
fa466c91 FCJ |
139 | |
140 | u8 prescaler_limit; | |
358934a6 SP |
141 | }; |
142 | ||
53a31b07 BN |
143 | static struct davinci_spi_config davinci_spi_default_cfg; |
144 | ||
212d4b69 | 145 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 146 | { |
212d4b69 SN |
147 | if (dspi->rx) { |
148 | u8 *rx = dspi->rx; | |
53d454a1 | 149 | *rx++ = (u8)data; |
212d4b69 | 150 | dspi->rx = rx; |
53d454a1 | 151 | } |
358934a6 SP |
152 | } |
153 | ||
212d4b69 | 154 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 155 | { |
212d4b69 SN |
156 | if (dspi->rx) { |
157 | u16 *rx = dspi->rx; | |
53d454a1 | 158 | *rx++ = (u16)data; |
212d4b69 | 159 | dspi->rx = rx; |
53d454a1 | 160 | } |
358934a6 SP |
161 | } |
162 | ||
212d4b69 | 163 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 164 | { |
53d454a1 | 165 | u32 data = 0; |
859c3377 | 166 | |
212d4b69 SN |
167 | if (dspi->tx) { |
168 | const u8 *tx = dspi->tx; | |
859c3377 | 169 | |
53d454a1 | 170 | data = *tx++; |
212d4b69 | 171 | dspi->tx = tx; |
53d454a1 | 172 | } |
358934a6 SP |
173 | return data; |
174 | } | |
175 | ||
212d4b69 | 176 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 177 | { |
53d454a1 | 178 | u32 data = 0; |
859c3377 | 179 | |
212d4b69 SN |
180 | if (dspi->tx) { |
181 | const u16 *tx = dspi->tx; | |
859c3377 | 182 | |
53d454a1 | 183 | data = *tx++; |
212d4b69 | 184 | dspi->tx = tx; |
53d454a1 | 185 | } |
358934a6 SP |
186 | return data; |
187 | } | |
188 | ||
189 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
190 | { | |
191 | u32 v = ioread32(addr); | |
192 | ||
193 | v |= bits; | |
194 | iowrite32(v, addr); | |
195 | } | |
196 | ||
197 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
198 | { | |
199 | u32 v = ioread32(addr); | |
200 | ||
201 | v &= ~bits; | |
202 | iowrite32(v, addr); | |
203 | } | |
204 | ||
358934a6 SP |
205 | /* |
206 | * Interface to control the chip select signal | |
207 | */ | |
208 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
209 | { | |
212d4b69 | 210 | struct davinci_spi *dspi; |
365a7bb3 | 211 | struct davinci_spi_config *spicfg = spi->controller_data; |
7978b8c3 | 212 | u8 chip_sel = spi->chip_select; |
212d4b69 | 213 | u16 spidat1 = CS_DEFAULT; |
358934a6 | 214 | |
212d4b69 | 215 | dspi = spi_master_get_devdata(spi->master); |
358934a6 | 216 | |
365a7bb3 | 217 | /* program delay transfers if tx_delay is non zero */ |
563a53f3 | 218 | if (spicfg && spicfg->wdelay) |
365a7bb3 MK |
219 | spidat1 |= SPIDAT1_WDEL; |
220 | ||
358934a6 SP |
221 | /* |
222 | * Board specific chip select logic decides the polarity and cs | |
223 | * line for the controller | |
224 | */ | |
8cae0424 | 225 | if (spi->cs_gpio >= 0) { |
23853973 | 226 | if (value == BITBANG_CS_ACTIVE) |
8cae0424 | 227 | gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH); |
23853973 | 228 | else |
8cae0424 LB |
229 | gpio_set_value(spi->cs_gpio, |
230 | !(spi->mode & SPI_CS_HIGH)); | |
23853973 BN |
231 | } else { |
232 | if (value == BITBANG_CS_ACTIVE) { | |
a3762b13 DL |
233 | if (!(spi->mode & SPI_CS_WORD)) |
234 | spidat1 |= SPIDAT1_CSHOLD_MASK; | |
212d4b69 | 235 | spidat1 &= ~(0x1 << chip_sel); |
23853973 | 236 | } |
23853973 | 237 | } |
365a7bb3 MK |
238 | |
239 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); | |
358934a6 SP |
240 | } |
241 | ||
7fe0092b BN |
242 | /** |
243 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
244 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
245 | * | |
246 | * This function calculates the prescale value that generates a clock rate | |
247 | * less than or equal to the specified maximum. | |
248 | * | |
bba732d8 | 249 | * Returns: calculated prescale value for easy programming into SPI registers |
7fe0092b BN |
250 | * or negative error number if valid prescalar cannot be updated. |
251 | */ | |
212d4b69 | 252 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
253 | u32 max_speed_hz) |
254 | { | |
255 | int ret; | |
256 | ||
bba732d8 FCJ |
257 | /* Subtract 1 to match what will be programmed into SPI register. */ |
258 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1; | |
7fe0092b | 259 | |
fa466c91 | 260 | if (ret < dspi->prescaler_limit || ret > 255) |
7fe0092b BN |
261 | return -EINVAL; |
262 | ||
bba732d8 | 263 | return ret; |
7fe0092b BN |
264 | } |
265 | ||
358934a6 SP |
266 | /** |
267 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
268 | * @spi: spi device on which data transfer to be done | |
269 | * @t: spi transfer in which transfer info is filled | |
270 | * | |
271 | * This function determines data transfer method (8/16/32 bit transfer). | |
272 | * It will also set the SPI Clock Control register according to | |
273 | * SPI slave device freq. | |
274 | */ | |
275 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
276 | struct spi_transfer *t) | |
277 | { | |
278 | ||
212d4b69 | 279 | struct davinci_spi *dspi; |
25f33512 | 280 | struct davinci_spi_config *spicfg; |
358934a6 | 281 | u8 bits_per_word = 0; |
32ea3944 SK |
282 | u32 hz = 0, spifmt = 0; |
283 | int prescale; | |
358934a6 | 284 | |
212d4b69 | 285 | dspi = spi_master_get_devdata(spi->master); |
365a7bb3 | 286 | spicfg = spi->controller_data; |
25f33512 BN |
287 | if (!spicfg) |
288 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
289 | |
290 | if (t) { | |
291 | bits_per_word = t->bits_per_word; | |
292 | hz = t->speed_hz; | |
293 | } | |
294 | ||
295 | /* if bits_per_word is not set then set it default */ | |
296 | if (!bits_per_word) | |
297 | bits_per_word = spi->bits_per_word; | |
298 | ||
299 | /* | |
300 | * Assign function pointer to appropriate transfer method | |
301 | * 8bit, 16bit or 32bit transfer | |
302 | */ | |
24778be2 | 303 | if (bits_per_word <= 8) { |
212d4b69 SN |
304 | dspi->get_rx = davinci_spi_rx_buf_u8; |
305 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
306 | dspi->bytes_per_word[spi->chip_select] = 1; | |
24778be2 | 307 | } else { |
212d4b69 SN |
308 | dspi->get_rx = davinci_spi_rx_buf_u16; |
309 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
310 | dspi->bytes_per_word[spi->chip_select] = 2; | |
24778be2 | 311 | } |
358934a6 SP |
312 | |
313 | if (!hz) | |
314 | hz = spi->max_speed_hz; | |
315 | ||
25f33512 BN |
316 | /* Set up SPIFMTn register, unique to this chipselect. */ |
317 | ||
212d4b69 | 318 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
319 | if (prescale < 0) |
320 | return prescale; | |
321 | ||
25f33512 BN |
322 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
323 | ||
324 | if (spi->mode & SPI_LSB_FIRST) | |
325 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
326 | ||
327 | if (spi->mode & SPI_CPOL) | |
328 | spifmt |= SPIFMT_POLARITY_MASK; | |
329 | ||
330 | if (!(spi->mode & SPI_CPHA)) | |
331 | spifmt |= SPIFMT_PHASE_MASK; | |
332 | ||
365a7bb3 MK |
333 | /* |
334 | * Assume wdelay is used only on SPI peripherals that has this field | |
335 | * in SPIFMTn register and when it's configured from board file or DT. | |
336 | */ | |
337 | if (spicfg->wdelay) | |
338 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) | |
339 | & SPIFMT_WDELAY_MASK); | |
340 | ||
25f33512 BN |
341 | /* |
342 | * Version 1 hardware supports two basic SPI modes: | |
343 | * - Standard SPI mode uses 4 pins, with chipselect | |
344 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
345 | * (distinct from SPI_3WIRE, with just one data wire; | |
346 | * or similar variants without MOSI or without MISO) | |
347 | * | |
348 | * Version 2 hardware supports an optional handshaking signal, | |
349 | * so it can support two more modes: | |
350 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
351 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
352 | */ | |
353 | ||
212d4b69 | 354 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 355 | |
7abbf23c BN |
356 | u32 delay = 0; |
357 | ||
25f33512 BN |
358 | if (spicfg->odd_parity) |
359 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
360 | ||
361 | if (spicfg->parity_enable) | |
362 | spifmt |= SPIFMT_PARITYENA_MASK; | |
363 | ||
7abbf23c | 364 | if (spicfg->timer_disable) { |
25f33512 | 365 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
366 | } else { |
367 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
368 | & SPIDELAY_C2TDELAY_MASK; | |
369 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
370 | & SPIDELAY_T2CDELAY_MASK; | |
371 | } | |
25f33512 | 372 | |
7abbf23c | 373 | if (spi->mode & SPI_READY) { |
25f33512 | 374 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
375 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
376 | & SPIDELAY_T2EDELAY_MASK; | |
377 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
378 | & SPIDELAY_C2EDELAY_MASK; | |
379 | } | |
380 | ||
212d4b69 | 381 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
382 | } |
383 | ||
212d4b69 | 384 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
385 | |
386 | return 0; | |
387 | } | |
388 | ||
365a7bb3 MK |
389 | static int davinci_spi_of_setup(struct spi_device *spi) |
390 | { | |
391 | struct davinci_spi_config *spicfg = spi->controller_data; | |
392 | struct device_node *np = spi->dev.of_node; | |
3e2e1258 | 393 | struct davinci_spi *dspi = spi_master_get_devdata(spi->master); |
365a7bb3 MK |
394 | u32 prop; |
395 | ||
396 | if (spicfg == NULL && np) { | |
397 | spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL); | |
398 | if (!spicfg) | |
399 | return -ENOMEM; | |
400 | *spicfg = davinci_spi_default_cfg; | |
401 | /* override with dt configured values */ | |
402 | if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) | |
403 | spicfg->wdelay = (u8)prop; | |
404 | spi->controller_data = spicfg; | |
3e2e1258 FP |
405 | |
406 | if (dspi->dma_rx && dspi->dma_tx) | |
407 | spicfg->io_type = SPI_IO_TYPE_DMA; | |
365a7bb3 MK |
408 | } |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
358934a6 SP |
413 | /** |
414 | * davinci_spi_setup - This functions will set default transfer method | |
415 | * @spi: spi device on which data transfer to be done | |
416 | * | |
417 | * This functions sets the default transfer method. | |
418 | */ | |
358934a6 SP |
419 | static int davinci_spi_setup(struct spi_device *spi) |
420 | { | |
b23a5d46 | 421 | int retval = 0; |
212d4b69 | 422 | struct davinci_spi *dspi; |
a88e34ea MK |
423 | struct spi_master *master = spi->master; |
424 | struct device_node *np = spi->dev.of_node; | |
425 | bool internal_cs = true; | |
358934a6 | 426 | |
212d4b69 | 427 | dspi = spi_master_get_devdata(spi->master); |
358934a6 | 428 | |
be88471b | 429 | if (!(spi->mode & SPI_NO_CS)) { |
a88e34ea | 430 | if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { |
8936decd GS |
431 | retval = gpio_direction_output( |
432 | spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
a88e34ea | 433 | internal_cs = false; |
a88e34ea | 434 | } |
be88471b | 435 | |
3f2dad99 GS |
436 | if (retval) { |
437 | dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", | |
438 | spi->cs_gpio, retval); | |
439 | return retval; | |
440 | } | |
c0600140 | 441 | |
a3762b13 | 442 | if (internal_cs) { |
3f2dad99 | 443 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
a3762b13 | 444 | } |
3f2dad99 | 445 | } |
a88e34ea | 446 | |
be88471b | 447 | if (spi->mode & SPI_READY) |
212d4b69 | 448 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
449 | |
450 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 451 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 452 | else |
212d4b69 | 453 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 454 | |
365a7bb3 MK |
455 | return davinci_spi_of_setup(spi); |
456 | } | |
457 | ||
458 | static void davinci_spi_cleanup(struct spi_device *spi) | |
459 | { | |
460 | struct davinci_spi_config *spicfg = spi->controller_data; | |
461 | ||
462 | spi->controller_data = NULL; | |
463 | if (spi->dev.of_node) | |
464 | kfree(spicfg); | |
358934a6 SP |
465 | } |
466 | ||
8aedbf58 FP |
467 | static bool davinci_spi_can_dma(struct spi_master *master, |
468 | struct spi_device *spi, | |
469 | struct spi_transfer *xfer) | |
470 | { | |
471 | struct davinci_spi_config *spicfg = spi->controller_data; | |
472 | bool can_dma = false; | |
473 | ||
474 | if (spicfg) | |
0718b764 | 475 | can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) && |
4dd9becb FI |
476 | (xfer->len >= DMA_MIN_BYTES) && |
477 | !is_vmalloc_addr(xfer->rx_buf) && | |
478 | !is_vmalloc_addr(xfer->tx_buf); | |
8aedbf58 FP |
479 | |
480 | return can_dma; | |
481 | } | |
482 | ||
212d4b69 | 483 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 484 | { |
212d4b69 | 485 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
486 | |
487 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
21c015b7 | 488 | dev_err(sdev, "SPI Time-out Error\n"); |
358934a6 SP |
489 | return -ETIMEDOUT; |
490 | } | |
491 | if (int_status & SPIFLG_DESYNC_MASK) { | |
21c015b7 | 492 | dev_err(sdev, "SPI Desynchronization Error\n"); |
358934a6 SP |
493 | return -EIO; |
494 | } | |
495 | if (int_status & SPIFLG_BITERR_MASK) { | |
21c015b7 | 496 | dev_err(sdev, "SPI Bit error\n"); |
358934a6 SP |
497 | return -EIO; |
498 | } | |
499 | ||
212d4b69 | 500 | if (dspi->version == SPI_VERSION_2) { |
358934a6 | 501 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
21c015b7 | 502 | dev_err(sdev, "SPI Data Length Error\n"); |
358934a6 SP |
503 | return -EIO; |
504 | } | |
505 | if (int_status & SPIFLG_PARERR_MASK) { | |
21c015b7 | 506 | dev_err(sdev, "SPI Parity Error\n"); |
358934a6 SP |
507 | return -EIO; |
508 | } | |
509 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
21c015b7 | 510 | dev_err(sdev, "SPI Data Overrun error\n"); |
358934a6 SP |
511 | return -EIO; |
512 | } | |
358934a6 | 513 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
21c015b7 | 514 | dev_err(sdev, "SPI Buffer Init Active\n"); |
358934a6 SP |
515 | return -EBUSY; |
516 | } | |
517 | } | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
e0d205e9 BN |
522 | /** |
523 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 524 | * @dspi: the controller data |
e0d205e9 BN |
525 | * |
526 | * This function will check the SPIFLG register and handle any events that are | |
527 | * detected there | |
528 | */ | |
212d4b69 | 529 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 530 | { |
212d4b69 | 531 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 532 | |
212d4b69 | 533 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 534 | |
212d4b69 SN |
535 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
536 | dspi->get_rx(buf & 0xFFFF, dspi); | |
537 | dspi->rcount--; | |
e0d205e9 BN |
538 | } |
539 | ||
212d4b69 | 540 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
541 | |
542 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
543 | errors = status & SPIFLG_ERROR_MASK; | |
544 | goto out; | |
545 | } | |
546 | ||
212d4b69 SN |
547 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
548 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
549 | dspi->wcount--; | |
550 | spidat1 &= ~0xFFFF; | |
551 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
552 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
553 | } |
554 | ||
555 | out: | |
556 | return errors; | |
557 | } | |
558 | ||
048177ce | 559 | static void davinci_spi_dma_rx_callback(void *data) |
87467bd9 | 560 | { |
048177ce | 561 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
87467bd9 | 562 | |
048177ce | 563 | dspi->rcount = 0; |
87467bd9 | 564 | |
048177ce MP |
565 | if (!dspi->wcount && !dspi->rcount) |
566 | complete(&dspi->done); | |
567 | } | |
87467bd9 | 568 | |
048177ce MP |
569 | static void davinci_spi_dma_tx_callback(void *data) |
570 | { | |
571 | struct davinci_spi *dspi = (struct davinci_spi *)data; | |
572 | ||
573 | dspi->wcount = 0; | |
574 | ||
575 | if (!dspi->wcount && !dspi->rcount) | |
212d4b69 | 576 | complete(&dspi->done); |
87467bd9 BN |
577 | } |
578 | ||
358934a6 SP |
579 | /** |
580 | * davinci_spi_bufs - functions which will handle transfer data | |
581 | * @spi: spi device on which data transfer to be done | |
582 | * @t: spi transfer in which transfer info is filled | |
583 | * | |
584 | * This function will put data to be transferred into data register | |
585 | * of SPI controller and then wait until the completion will be marked | |
586 | * by the IRQ Handler. | |
587 | */ | |
87467bd9 | 588 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 589 | { |
212d4b69 | 590 | struct davinci_spi *dspi; |
048177ce | 591 | int data_type, ret = -ENOMEM; |
212d4b69 | 592 | u32 tx_data, spidat1; |
839c996c | 593 | u32 errors = 0; |
e0d205e9 | 594 | struct davinci_spi_config *spicfg; |
358934a6 | 595 | struct davinci_spi_platform_data *pdata; |
87467bd9 | 596 | unsigned uninitialized_var(rx_buf_count); |
358934a6 | 597 | |
212d4b69 | 598 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 599 | pdata = &dspi->pdata; |
e0d205e9 BN |
600 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
601 | if (!spicfg) | |
602 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
603 | |
604 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 605 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 606 | |
212d4b69 SN |
607 | dspi->tx = t->tx_buf; |
608 | dspi->rx = t->rx_buf; | |
609 | dspi->wcount = t->len / data_type; | |
610 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 611 | |
212d4b69 | 612 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 613 | |
212d4b69 SN |
614 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
615 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 616 | |
16735d02 | 617 | reinit_completion(&dspi->done); |
87467bd9 | 618 | |
0718b764 FI |
619 | if (!davinci_spi_can_dma(spi->master, spi, t)) { |
620 | if (spicfg->io_type != SPI_IO_TYPE_POLL) | |
621 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); | |
87467bd9 | 622 | /* start the transfer */ |
212d4b69 SN |
623 | dspi->wcount--; |
624 | tx_data = dspi->get_tx(dspi); | |
625 | spidat1 &= 0xFFFF0000; | |
626 | spidat1 |= tx_data & 0xFFFF; | |
627 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 628 | } else { |
048177ce MP |
629 | struct dma_slave_config dma_rx_conf = { |
630 | .direction = DMA_DEV_TO_MEM, | |
631 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | |
632 | .src_addr_width = data_type, | |
633 | .src_maxburst = 1, | |
634 | }; | |
635 | struct dma_slave_config dma_tx_conf = { | |
636 | .direction = DMA_MEM_TO_DEV, | |
637 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | |
638 | .dst_addr_width = data_type, | |
639 | .dst_maxburst = 1, | |
640 | }; | |
641 | struct dma_async_tx_descriptor *rxdesc; | |
642 | struct dma_async_tx_descriptor *txdesc; | |
048177ce MP |
643 | |
644 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | |
645 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | |
646 | ||
048177ce | 647 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, |
8aedbf58 | 648 | t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM, |
048177ce MP |
649 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
650 | if (!rxdesc) | |
651 | goto err_desc; | |
652 | ||
6b3a631e | 653 | if (!t->tx_buf) { |
1234e839 FI |
654 | /* To avoid errors when doing rx-only transfers with |
655 | * many SG entries (> 20), use the rx buffer as the | |
656 | * dummy tx buffer so that dma reloads are done at the | |
657 | * same time for rx and tx. | |
658 | */ | |
6b3a631e FI |
659 | t->tx_sg.sgl = t->rx_sg.sgl; |
660 | t->tx_sg.nents = t->rx_sg.nents; | |
661 | } | |
662 | ||
048177ce | 663 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, |
8aedbf58 | 664 | t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, |
048177ce MP |
665 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
666 | if (!txdesc) | |
667 | goto err_desc; | |
668 | ||
669 | rxdesc->callback = davinci_spi_dma_rx_callback; | |
670 | rxdesc->callback_param = (void *)dspi; | |
671 | txdesc->callback = davinci_spi_dma_tx_callback; | |
672 | txdesc->callback_param = (void *)dspi; | |
87467bd9 BN |
673 | |
674 | if (pdata->cshold_bug) | |
212d4b69 | 675 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 676 | |
048177ce MP |
677 | dmaengine_submit(rxdesc); |
678 | dmaengine_submit(txdesc); | |
679 | ||
680 | dma_async_issue_pending(dspi->dma_rx); | |
681 | dma_async_issue_pending(dspi->dma_tx); | |
682 | ||
212d4b69 | 683 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 684 | } |
358934a6 | 685 | |
e0d205e9 | 686 | /* Wait for the transfer to complete */ |
87467bd9 | 687 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
7f3ac71a SN |
688 | if (wait_for_completion_timeout(&dspi->done, HZ) == 0) |
689 | errors = SPIFLG_TIMEOUT_MASK; | |
e0d205e9 | 690 | } else { |
212d4b69 SN |
691 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
692 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
693 | if (errors) |
694 | break; | |
695 | cpu_relax(); | |
358934a6 SP |
696 | } |
697 | } | |
698 | ||
212d4b69 | 699 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
0718b764 | 700 | if (davinci_spi_can_dma(spi->master, spi, t)) |
212d4b69 | 701 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
048177ce | 702 | |
212d4b69 SN |
703 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
704 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 705 | |
358934a6 SP |
706 | /* |
707 | * Check for bit error, desync error,parity error,timeout error and | |
708 | * receive overflow errors | |
709 | */ | |
839c996c | 710 | if (errors) { |
212d4b69 | 711 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
712 | WARN(!ret, "%s: error reported but no error found!\n", |
713 | dev_name(&spi->dev)); | |
358934a6 | 714 | return ret; |
839c996c | 715 | } |
358934a6 | 716 | |
212d4b69 | 717 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
048177ce | 718 | dev_err(&spi->dev, "SPI data transfer error\n"); |
87467bd9 BN |
719 | return -EIO; |
720 | } | |
721 | ||
358934a6 | 722 | return t->len; |
048177ce MP |
723 | |
724 | err_desc: | |
048177ce | 725 | return ret; |
358934a6 SP |
726 | } |
727 | ||
32310aaf MK |
728 | /** |
729 | * dummy_thread_fn - dummy thread function | |
730 | * @irq: IRQ number for this SPI Master | |
731 | * @context_data: structure for SPI Master controller davinci_spi | |
732 | * | |
733 | * This is to satisfy the request_threaded_irq() API so that the irq | |
734 | * handler is called in interrupt context. | |
735 | */ | |
736 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | |
737 | { | |
738 | return IRQ_HANDLED; | |
739 | } | |
740 | ||
e0d205e9 BN |
741 | /** |
742 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
743 | * @irq: IRQ number for this SPI Master | |
744 | * @context_data: structure for SPI Master controller davinci_spi | |
745 | * | |
746 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
747 | * According to command it will do the appropriate action. It will check | |
748 | * transfer length and if it is not zero then dispatch transfer command again. | |
749 | * If transfer length is zero then it will indicate the COMPLETION so that | |
750 | * davinci_spi_bufs function can go ahead. | |
751 | */ | |
212d4b69 | 752 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 753 | { |
212d4b69 | 754 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
755 | int status; |
756 | ||
212d4b69 | 757 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 758 | if (unlikely(status != 0)) |
212d4b69 | 759 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 760 | |
212d4b69 SN |
761 | if ((!dspi->rcount && !dspi->wcount) || status) |
762 | complete(&dspi->done); | |
e0d205e9 BN |
763 | |
764 | return IRQ_HANDLED; | |
765 | } | |
766 | ||
212d4b69 | 767 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b | 768 | { |
048177ce | 769 | struct device *sdev = dspi->bitbang.master->dev.parent; |
048177ce | 770 | |
fe5fd254 PU |
771 | dspi->dma_rx = dma_request_chan(sdev, "rx"); |
772 | if (IS_ERR(dspi->dma_rx)) | |
773 | return PTR_ERR(dspi->dma_rx); | |
903ca25b | 774 | |
fe5fd254 PU |
775 | dspi->dma_tx = dma_request_chan(sdev, "tx"); |
776 | if (IS_ERR(dspi->dma_tx)) { | |
777 | dma_release_channel(dspi->dma_rx); | |
778 | return PTR_ERR(dspi->dma_tx); | |
903ca25b SN |
779 | } |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
aae7147d | 784 | #if defined(CONFIG_OF) |
fa466c91 FCJ |
785 | |
786 | /* OF SPI data structure */ | |
787 | struct davinci_spi_of_data { | |
788 | u8 version; | |
789 | u8 prescaler_limit; | |
790 | }; | |
791 | ||
792 | static const struct davinci_spi_of_data dm6441_spi_data = { | |
793 | .version = SPI_VERSION_1, | |
794 | .prescaler_limit = 2, | |
795 | }; | |
796 | ||
797 | static const struct davinci_spi_of_data da830_spi_data = { | |
798 | .version = SPI_VERSION_2, | |
799 | .prescaler_limit = 2, | |
800 | }; | |
801 | ||
802 | static const struct davinci_spi_of_data keystone_spi_data = { | |
803 | .version = SPI_VERSION_1, | |
804 | .prescaler_limit = 0, | |
805 | }; | |
806 | ||
aae7147d MK |
807 | static const struct of_device_id davinci_spi_of_match[] = { |
808 | { | |
804413f2 | 809 | .compatible = "ti,dm6441-spi", |
fa466c91 | 810 | .data = &dm6441_spi_data, |
aae7147d MK |
811 | }, |
812 | { | |
804413f2 | 813 | .compatible = "ti,da830-spi", |
fa466c91 FCJ |
814 | .data = &da830_spi_data, |
815 | }, | |
816 | { | |
817 | .compatible = "ti,keystone-spi", | |
818 | .data = &keystone_spi_data, | |
aae7147d MK |
819 | }, |
820 | { }, | |
821 | }; | |
0d2d0cc5 | 822 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
aae7147d MK |
823 | |
824 | /** | |
825 | * spi_davinci_get_pdata - Get platform data from DTS binding | |
826 | * @pdev: ptr to platform data | |
827 | * @dspi: ptr to driver data | |
828 | * | |
829 | * Parses and populates pdata in dspi from device tree bindings. | |
830 | * | |
831 | * NOTE: Not all platform data params are supported currently. | |
832 | */ | |
833 | static int spi_davinci_get_pdata(struct platform_device *pdev, | |
834 | struct davinci_spi *dspi) | |
835 | { | |
836 | struct device_node *node = pdev->dev.of_node; | |
fa466c91 | 837 | struct davinci_spi_of_data *spi_data; |
aae7147d MK |
838 | struct davinci_spi_platform_data *pdata; |
839 | unsigned int num_cs, intr_line = 0; | |
840 | const struct of_device_id *match; | |
841 | ||
842 | pdata = &dspi->pdata; | |
843 | ||
b53b34f0 | 844 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
aae7147d MK |
845 | if (!match) |
846 | return -ENODEV; | |
847 | ||
fa466c91 | 848 | spi_data = (struct davinci_spi_of_data *)match->data; |
aae7147d | 849 | |
fa466c91 FCJ |
850 | pdata->version = spi_data->version; |
851 | pdata->prescaler_limit = spi_data->prescaler_limit; | |
aae7147d MK |
852 | /* |
853 | * default num_cs is 1 and all chipsel are internal to the chip | |
a88e34ea MK |
854 | * indicated by chip_sel being NULL or cs_gpios being NULL or |
855 | * set to -ENOENT. num-cs includes internal as well as gpios. | |
aae7147d MK |
856 | * indicated by chip_sel being NULL. GPIO based CS is not |
857 | * supported yet in DT bindings. | |
858 | */ | |
859 | num_cs = 1; | |
860 | of_property_read_u32(node, "num-cs", &num_cs); | |
861 | pdata->num_chipselect = num_cs; | |
862 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | |
863 | pdata->intr_line = intr_line; | |
864 | return 0; | |
865 | } | |
866 | #else | |
2b747a5f AY |
867 | static int spi_davinci_get_pdata(struct platform_device *pdev, |
868 | struct davinci_spi *dspi) | |
aae7147d MK |
869 | { |
870 | return -ENODEV; | |
871 | } | |
872 | #endif | |
873 | ||
358934a6 SP |
874 | /** |
875 | * davinci_spi_probe - probe function for SPI Master Controller | |
876 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
877 | * |
878 | * According to Linux Device Model this function will be invoked by Linux | |
879 | * with platform_device struct which contains the device specific info. | |
880 | * This function will map the SPI controller's memory, register IRQ, | |
881 | * Reset SPI controller and setting its registers to default value. | |
882 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
883 | * can register transfer method to work queue. | |
358934a6 | 884 | */ |
fd4a319b | 885 | static int davinci_spi_probe(struct platform_device *pdev) |
358934a6 SP |
886 | { |
887 | struct spi_master *master; | |
212d4b69 | 888 | struct davinci_spi *dspi; |
358934a6 | 889 | struct davinci_spi_platform_data *pdata; |
5b3bb596 | 890 | struct resource *r; |
c0600140 | 891 | int ret = 0; |
f34bd4cc | 892 | u32 spipc0; |
358934a6 | 893 | |
358934a6 SP |
894 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
895 | if (master == NULL) { | |
896 | ret = -ENOMEM; | |
897 | goto err; | |
898 | } | |
899 | ||
24b5a82c | 900 | platform_set_drvdata(pdev, master); |
358934a6 | 901 | |
212d4b69 | 902 | dspi = spi_master_get_devdata(master); |
358934a6 | 903 | |
8074cf06 JH |
904 | if (dev_get_platdata(&pdev->dev)) { |
905 | pdata = dev_get_platdata(&pdev->dev); | |
aae7147d MK |
906 | dspi->pdata = *pdata; |
907 | } else { | |
908 | /* update dspi pdata with that from the DT */ | |
909 | ret = spi_davinci_get_pdata(pdev, dspi); | |
910 | if (ret < 0) | |
911 | goto free_master; | |
912 | } | |
913 | ||
914 | /* pdata in dspi is now updated and point pdata to that */ | |
915 | pdata = &dspi->pdata; | |
916 | ||
a86854d0 KC |
917 | dspi->bytes_per_word = devm_kcalloc(&pdev->dev, |
918 | pdata->num_chipselect, | |
919 | sizeof(*dspi->bytes_per_word), | |
920 | GFP_KERNEL); | |
7480e755 MK |
921 | if (dspi->bytes_per_word == NULL) { |
922 | ret = -ENOMEM; | |
923 | goto free_master; | |
924 | } | |
925 | ||
358934a6 SP |
926 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
927 | if (r == NULL) { | |
928 | ret = -ENOENT; | |
929 | goto free_master; | |
930 | } | |
931 | ||
212d4b69 | 932 | dspi->pbase = r->start; |
358934a6 | 933 | |
5b3bb596 JH |
934 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
935 | if (IS_ERR(dspi->base)) { | |
936 | ret = PTR_ERR(dspi->base); | |
358934a6 SP |
937 | goto free_master; |
938 | } | |
939 | ||
87248dc7 MD |
940 | init_completion(&dspi->done); |
941 | ||
8494cdea AH |
942 | ret = platform_get_irq(pdev, 0); |
943 | if (ret == 0) | |
e0d205e9 | 944 | ret = -EINVAL; |
8494cdea | 945 | if (ret < 0) |
5b3bb596 | 946 | goto free_master; |
8494cdea | 947 | dspi->irq = ret; |
e0d205e9 | 948 | |
5b3bb596 JH |
949 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
950 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); | |
e0d205e9 | 951 | if (ret) |
5b3bb596 | 952 | goto free_master; |
e0d205e9 | 953 | |
94c69f76 | 954 | dspi->bitbang.master = master; |
358934a6 | 955 | |
5b3bb596 | 956 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
212d4b69 | 957 | if (IS_ERR(dspi->clk)) { |
358934a6 | 958 | ret = -ENODEV; |
5b3bb596 | 959 | goto free_master; |
358934a6 | 960 | } |
35fc3b9f AY |
961 | ret = clk_prepare_enable(dspi->clk); |
962 | if (ret) | |
963 | goto free_master; | |
358934a6 | 964 | |
aae7147d | 965 | master->dev.of_node = pdev->dev.of_node; |
358934a6 SP |
966 | master->bus_num = pdev->id; |
967 | master->num_chipselect = pdata->num_chipselect; | |
24778be2 | 968 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
6b3a631e | 969 | master->flags = SPI_MASTER_MUST_RX; |
358934a6 | 970 | master->setup = davinci_spi_setup; |
365a7bb3 | 971 | master->cleanup = davinci_spi_cleanup; |
8aedbf58 | 972 | master->can_dma = davinci_spi_can_dma; |
358934a6 | 973 | |
212d4b69 SN |
974 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
975 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
fa466c91 | 976 | dspi->prescaler_limit = pdata->prescaler_limit; |
212d4b69 | 977 | dspi->version = pdata->version; |
358934a6 | 978 | |
a3762b13 | 979 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD; |
212d4b69 SN |
980 | if (dspi->version == SPI_VERSION_2) |
981 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 982 | |
8936decd GS |
983 | if (pdev->dev.of_node) { |
984 | int i; | |
985 | ||
986 | for (i = 0; i < pdata->num_chipselect; i++) { | |
987 | int cs_gpio = of_get_named_gpio(pdev->dev.of_node, | |
988 | "cs-gpios", i); | |
989 | ||
990 | if (cs_gpio == -EPROBE_DEFER) { | |
991 | ret = cs_gpio; | |
992 | goto free_clk; | |
993 | } | |
994 | ||
995 | if (gpio_is_valid(cs_gpio)) { | |
996 | ret = devm_gpio_request(&pdev->dev, cs_gpio, | |
997 | dev_name(&pdev->dev)); | |
998 | if (ret) | |
999 | goto free_clk; | |
1000 | } | |
1001 | } | |
1002 | } | |
1003 | ||
212d4b69 | 1004 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
fe5fd254 PU |
1005 | |
1006 | ret = davinci_spi_request_dma(dspi); | |
1007 | if (ret == -EPROBE_DEFER) { | |
1008 | goto free_clk; | |
1009 | } else if (ret) { | |
1010 | dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret); | |
1011 | dspi->dma_rx = NULL; | |
1012 | dspi->dma_tx = NULL; | |
358934a6 SP |
1013 | } |
1014 | ||
212d4b69 SN |
1015 | dspi->get_rx = davinci_spi_rx_buf_u8; |
1016 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 1017 | |
358934a6 | 1018 | /* Reset In/OUT SPI module */ |
212d4b69 | 1019 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 1020 | udelay(100); |
212d4b69 | 1021 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 1022 | |
be88471b | 1023 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 1024 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 1025 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 1026 | |
e0d205e9 | 1027 | if (pdata->intr_line) |
212d4b69 | 1028 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 1029 | else |
212d4b69 | 1030 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 1031 | |
212d4b69 | 1032 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 1033 | |
358934a6 | 1034 | /* master mode default */ |
212d4b69 SN |
1035 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
1036 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1037 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 1038 | |
212d4b69 | 1039 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 1040 | if (ret) |
903ca25b | 1041 | goto free_dma; |
358934a6 | 1042 | |
212d4b69 | 1043 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 1044 | |
358934a6 SP |
1045 | return ret; |
1046 | ||
903ca25b | 1047 | free_dma: |
fe5fd254 PU |
1048 | if (dspi->dma_rx) { |
1049 | dma_release_channel(dspi->dma_rx); | |
1050 | dma_release_channel(dspi->dma_tx); | |
1051 | } | |
358934a6 | 1052 | free_clk: |
aae7147d | 1053 | clk_disable_unprepare(dspi->clk); |
358934a6 | 1054 | free_master: |
94c69f76 | 1055 | spi_master_put(master); |
358934a6 SP |
1056 | err: |
1057 | return ret; | |
1058 | } | |
1059 | ||
1060 | /** | |
1061 | * davinci_spi_remove - remove function for SPI Master Controller | |
1062 | * @pdev: platform_device structure which contains plateform specific data | |
1063 | * | |
1064 | * This function will do the reverse action of davinci_spi_probe function | |
1065 | * It will free the IRQ and SPI controller's memory region. | |
1066 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1067 | * created by spi_bitbang_start. | |
1068 | */ | |
fd4a319b | 1069 | static int davinci_spi_remove(struct platform_device *pdev) |
358934a6 | 1070 | { |
212d4b69 | 1071 | struct davinci_spi *dspi; |
358934a6 SP |
1072 | struct spi_master *master; |
1073 | ||
24b5a82c | 1074 | master = platform_get_drvdata(pdev); |
212d4b69 | 1075 | dspi = spi_master_get_devdata(master); |
358934a6 | 1076 | |
212d4b69 | 1077 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 1078 | |
aae7147d | 1079 | clk_disable_unprepare(dspi->clk); |
94c69f76 | 1080 | spi_master_put(master); |
358934a6 | 1081 | |
fe5fd254 PU |
1082 | if (dspi->dma_rx) { |
1083 | dma_release_channel(dspi->dma_rx); | |
1084 | dma_release_channel(dspi->dma_tx); | |
1085 | } | |
1086 | ||
358934a6 SP |
1087 | return 0; |
1088 | } | |
1089 | ||
1090 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1091 | .driver = { |
1092 | .name = "spi_davinci", | |
b53b34f0 | 1093 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
d8c174cd | 1094 | }, |
940ab889 | 1095 | .probe = davinci_spi_probe, |
fd4a319b | 1096 | .remove = davinci_spi_remove, |
358934a6 | 1097 | }; |
940ab889 | 1098 | module_platform_driver(davinci_spi_driver); |
358934a6 SP |
1099 | |
1100 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1101 | MODULE_LICENSE("GPL"); |