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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 3 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
358934a6 SP |
14 | */ |
15 | ||
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
101a68e7 | 18 | #include <linux/gpio/consumer.h> |
358934a6 SP |
19 | #include <linux/module.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/clk.h> | |
048177ce | 24 | #include <linux/dmaengine.h> |
358934a6 | 25 | #include <linux/dma-mapping.h> |
aae7147d MK |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
358934a6 SP |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 | 31 | |
ec2a0833 | 32 | #include <linux/platform_data/spi-davinci.h> |
358934a6 | 33 | |
358934a6 SP |
34 | #define CS_DEFAULT 0xFF |
35 | ||
358934a6 SP |
36 | #define SPIFMT_PHASE_MASK BIT(16) |
37 | #define SPIFMT_POLARITY_MASK BIT(17) | |
38 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
39 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
40 | #define SPIFMT_WAITENA_MASK BIT(21) | |
41 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
42 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
43 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
44 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 45 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 46 | |
358934a6 SP |
47 | /* SPIPC0 */ |
48 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
49 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
50 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
51 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
52 | |
53 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
54 | #define SPIINT_MASKINT 0x0000015F |
55 | #define SPI_INTLVL_1 0x000001FF | |
56 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 57 | |
cfbc5d1d BN |
58 | /* SPIDAT1 (upper 16 bit defines) */ |
59 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
365a7bb3 | 60 | #define SPIDAT1_WDEL BIT(10) |
cfbc5d1d BN |
61 | |
62 | /* SPIGCR1 */ | |
358934a6 SP |
63 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
64 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 65 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 66 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 67 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
68 | |
69 | /* SPIBUF */ | |
70 | #define SPIBUF_TXFULL_MASK BIT(29) | |
71 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
72 | ||
7abbf23c BN |
73 | /* SPIDELAY */ |
74 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
75 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
76 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
77 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
78 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
79 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
80 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
81 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
82 | ||
358934a6 SP |
83 | /* Error Masks */ |
84 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
85 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
86 | #define SPIFLG_PARERR_MASK BIT(2) | |
87 | #define SPIFLG_DESYNC_MASK BIT(3) | |
88 | #define SPIFLG_BITERR_MASK BIT(4) | |
89 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 90 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
91 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
92 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
93 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
94 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 95 | |
358934a6 | 96 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 97 | |
358934a6 SP |
98 | /* SPI Controller registers */ |
99 | #define SPIGCR0 0x00 | |
100 | #define SPIGCR1 0x04 | |
101 | #define SPIINT 0x08 | |
102 | #define SPILVL 0x0c | |
103 | #define SPIFLG 0x10 | |
104 | #define SPIPC0 0x14 | |
358934a6 SP |
105 | #define SPIDAT1 0x3c |
106 | #define SPIBUF 0x40 | |
358934a6 SP |
107 | #define SPIDELAY 0x48 |
108 | #define SPIDEF 0x4c | |
109 | #define SPIFMT0 0x50 | |
358934a6 | 110 | |
0718b764 FI |
111 | #define DMA_MIN_BYTES 16 |
112 | ||
358934a6 SP |
113 | /* SPI Controller driver's private data. */ |
114 | struct davinci_spi { | |
115 | struct spi_bitbang bitbang; | |
116 | struct clk *clk; | |
117 | ||
118 | u8 version; | |
119 | resource_size_t pbase; | |
120 | void __iomem *base; | |
e0d205e9 BN |
121 | u32 irq; |
122 | struct completion done; | |
358934a6 SP |
123 | |
124 | const void *tx; | |
125 | void *rx; | |
e0d205e9 BN |
126 | int rcount; |
127 | int wcount; | |
048177ce MP |
128 | |
129 | struct dma_chan *dma_rx; | |
130 | struct dma_chan *dma_tx; | |
048177ce | 131 | |
aae7147d | 132 | struct davinci_spi_platform_data pdata; |
358934a6 SP |
133 | |
134 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
135 | u32 (*get_tx)(struct davinci_spi *); | |
136 | ||
7480e755 | 137 | u8 *bytes_per_word; |
fa466c91 FCJ |
138 | |
139 | u8 prescaler_limit; | |
358934a6 SP |
140 | }; |
141 | ||
53a31b07 BN |
142 | static struct davinci_spi_config davinci_spi_default_cfg; |
143 | ||
212d4b69 | 144 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 145 | { |
212d4b69 SN |
146 | if (dspi->rx) { |
147 | u8 *rx = dspi->rx; | |
53d454a1 | 148 | *rx++ = (u8)data; |
212d4b69 | 149 | dspi->rx = rx; |
53d454a1 | 150 | } |
358934a6 SP |
151 | } |
152 | ||
212d4b69 | 153 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 154 | { |
212d4b69 SN |
155 | if (dspi->rx) { |
156 | u16 *rx = dspi->rx; | |
53d454a1 | 157 | *rx++ = (u16)data; |
212d4b69 | 158 | dspi->rx = rx; |
53d454a1 | 159 | } |
358934a6 SP |
160 | } |
161 | ||
212d4b69 | 162 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 163 | { |
53d454a1 | 164 | u32 data = 0; |
859c3377 | 165 | |
212d4b69 SN |
166 | if (dspi->tx) { |
167 | const u8 *tx = dspi->tx; | |
859c3377 | 168 | |
53d454a1 | 169 | data = *tx++; |
212d4b69 | 170 | dspi->tx = tx; |
53d454a1 | 171 | } |
358934a6 SP |
172 | return data; |
173 | } | |
174 | ||
212d4b69 | 175 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 176 | { |
53d454a1 | 177 | u32 data = 0; |
859c3377 | 178 | |
212d4b69 SN |
179 | if (dspi->tx) { |
180 | const u16 *tx = dspi->tx; | |
859c3377 | 181 | |
53d454a1 | 182 | data = *tx++; |
212d4b69 | 183 | dspi->tx = tx; |
53d454a1 | 184 | } |
358934a6 SP |
185 | return data; |
186 | } | |
187 | ||
188 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
189 | { | |
190 | u32 v = ioread32(addr); | |
191 | ||
192 | v |= bits; | |
193 | iowrite32(v, addr); | |
194 | } | |
195 | ||
196 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
197 | { | |
198 | u32 v = ioread32(addr); | |
199 | ||
200 | v &= ~bits; | |
201 | iowrite32(v, addr); | |
202 | } | |
203 | ||
358934a6 SP |
204 | /* |
205 | * Interface to control the chip select signal | |
206 | */ | |
207 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
208 | { | |
212d4b69 | 209 | struct davinci_spi *dspi; |
365a7bb3 | 210 | struct davinci_spi_config *spicfg = spi->controller_data; |
7978b8c3 | 211 | u8 chip_sel = spi->chip_select; |
212d4b69 | 212 | u16 spidat1 = CS_DEFAULT; |
358934a6 | 213 | |
212d4b69 | 214 | dspi = spi_master_get_devdata(spi->master); |
358934a6 | 215 | |
365a7bb3 | 216 | /* program delay transfers if tx_delay is non zero */ |
563a53f3 | 217 | if (spicfg && spicfg->wdelay) |
365a7bb3 MK |
218 | spidat1 |= SPIDAT1_WDEL; |
219 | ||
358934a6 SP |
220 | /* |
221 | * Board specific chip select logic decides the polarity and cs | |
222 | * line for the controller | |
223 | */ | |
101a68e7 LW |
224 | if (spi->cs_gpiod) { |
225 | /* | |
226 | * FIXME: is this code ever executed? This host does not | |
227 | * set SPI_MASTER_GPIO_SS so this chipselect callback should | |
228 | * not get called from the SPI core when we are using | |
229 | * GPIOs for chip select. | |
230 | */ | |
23853973 | 231 | if (value == BITBANG_CS_ACTIVE) |
101a68e7 | 232 | gpiod_set_value(spi->cs_gpiod, 1); |
23853973 | 233 | else |
101a68e7 | 234 | gpiod_set_value(spi->cs_gpiod, 0); |
23853973 BN |
235 | } else { |
236 | if (value == BITBANG_CS_ACTIVE) { | |
a3762b13 DL |
237 | if (!(spi->mode & SPI_CS_WORD)) |
238 | spidat1 |= SPIDAT1_CSHOLD_MASK; | |
212d4b69 | 239 | spidat1 &= ~(0x1 << chip_sel); |
23853973 | 240 | } |
23853973 | 241 | } |
365a7bb3 MK |
242 | |
243 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); | |
358934a6 SP |
244 | } |
245 | ||
7fe0092b BN |
246 | /** |
247 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
248 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
249 | * | |
250 | * This function calculates the prescale value that generates a clock rate | |
251 | * less than or equal to the specified maximum. | |
252 | * | |
bba732d8 | 253 | * Returns: calculated prescale value for easy programming into SPI registers |
7fe0092b BN |
254 | * or negative error number if valid prescalar cannot be updated. |
255 | */ | |
212d4b69 | 256 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
257 | u32 max_speed_hz) |
258 | { | |
259 | int ret; | |
260 | ||
bba732d8 FCJ |
261 | /* Subtract 1 to match what will be programmed into SPI register. */ |
262 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1; | |
7fe0092b | 263 | |
fa466c91 | 264 | if (ret < dspi->prescaler_limit || ret > 255) |
7fe0092b BN |
265 | return -EINVAL; |
266 | ||
bba732d8 | 267 | return ret; |
7fe0092b BN |
268 | } |
269 | ||
358934a6 SP |
270 | /** |
271 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
272 | * @spi: spi device on which data transfer to be done | |
273 | * @t: spi transfer in which transfer info is filled | |
274 | * | |
275 | * This function determines data transfer method (8/16/32 bit transfer). | |
276 | * It will also set the SPI Clock Control register according to | |
277 | * SPI slave device freq. | |
278 | */ | |
279 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
280 | struct spi_transfer *t) | |
281 | { | |
282 | ||
212d4b69 | 283 | struct davinci_spi *dspi; |
25f33512 | 284 | struct davinci_spi_config *spicfg; |
358934a6 | 285 | u8 bits_per_word = 0; |
32ea3944 SK |
286 | u32 hz = 0, spifmt = 0; |
287 | int prescale; | |
358934a6 | 288 | |
212d4b69 | 289 | dspi = spi_master_get_devdata(spi->master); |
365a7bb3 | 290 | spicfg = spi->controller_data; |
25f33512 BN |
291 | if (!spicfg) |
292 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
293 | |
294 | if (t) { | |
295 | bits_per_word = t->bits_per_word; | |
296 | hz = t->speed_hz; | |
297 | } | |
298 | ||
299 | /* if bits_per_word is not set then set it default */ | |
300 | if (!bits_per_word) | |
301 | bits_per_word = spi->bits_per_word; | |
302 | ||
303 | /* | |
304 | * Assign function pointer to appropriate transfer method | |
305 | * 8bit, 16bit or 32bit transfer | |
306 | */ | |
24778be2 | 307 | if (bits_per_word <= 8) { |
212d4b69 SN |
308 | dspi->get_rx = davinci_spi_rx_buf_u8; |
309 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
310 | dspi->bytes_per_word[spi->chip_select] = 1; | |
24778be2 | 311 | } else { |
212d4b69 SN |
312 | dspi->get_rx = davinci_spi_rx_buf_u16; |
313 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
314 | dspi->bytes_per_word[spi->chip_select] = 2; | |
24778be2 | 315 | } |
358934a6 SP |
316 | |
317 | if (!hz) | |
318 | hz = spi->max_speed_hz; | |
319 | ||
25f33512 BN |
320 | /* Set up SPIFMTn register, unique to this chipselect. */ |
321 | ||
212d4b69 | 322 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
323 | if (prescale < 0) |
324 | return prescale; | |
325 | ||
25f33512 BN |
326 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
327 | ||
328 | if (spi->mode & SPI_LSB_FIRST) | |
329 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
330 | ||
331 | if (spi->mode & SPI_CPOL) | |
332 | spifmt |= SPIFMT_POLARITY_MASK; | |
333 | ||
334 | if (!(spi->mode & SPI_CPHA)) | |
335 | spifmt |= SPIFMT_PHASE_MASK; | |
336 | ||
365a7bb3 MK |
337 | /* |
338 | * Assume wdelay is used only on SPI peripherals that has this field | |
339 | * in SPIFMTn register and when it's configured from board file or DT. | |
340 | */ | |
341 | if (spicfg->wdelay) | |
342 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) | |
343 | & SPIFMT_WDELAY_MASK); | |
344 | ||
25f33512 BN |
345 | /* |
346 | * Version 1 hardware supports two basic SPI modes: | |
347 | * - Standard SPI mode uses 4 pins, with chipselect | |
348 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
349 | * (distinct from SPI_3WIRE, with just one data wire; | |
350 | * or similar variants without MOSI or without MISO) | |
351 | * | |
352 | * Version 2 hardware supports an optional handshaking signal, | |
353 | * so it can support two more modes: | |
354 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
355 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
356 | */ | |
357 | ||
212d4b69 | 358 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 359 | |
7abbf23c BN |
360 | u32 delay = 0; |
361 | ||
25f33512 BN |
362 | if (spicfg->odd_parity) |
363 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
364 | ||
365 | if (spicfg->parity_enable) | |
366 | spifmt |= SPIFMT_PARITYENA_MASK; | |
367 | ||
7abbf23c | 368 | if (spicfg->timer_disable) { |
25f33512 | 369 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
370 | } else { |
371 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
372 | & SPIDELAY_C2TDELAY_MASK; | |
373 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
374 | & SPIDELAY_T2CDELAY_MASK; | |
375 | } | |
25f33512 | 376 | |
7abbf23c | 377 | if (spi->mode & SPI_READY) { |
25f33512 | 378 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
379 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
380 | & SPIDELAY_T2EDELAY_MASK; | |
381 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
382 | & SPIDELAY_C2EDELAY_MASK; | |
383 | } | |
384 | ||
212d4b69 | 385 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
386 | } |
387 | ||
212d4b69 | 388 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
365a7bb3 MK |
393 | static int davinci_spi_of_setup(struct spi_device *spi) |
394 | { | |
395 | struct davinci_spi_config *spicfg = spi->controller_data; | |
396 | struct device_node *np = spi->dev.of_node; | |
3e2e1258 | 397 | struct davinci_spi *dspi = spi_master_get_devdata(spi->master); |
365a7bb3 MK |
398 | u32 prop; |
399 | ||
400 | if (spicfg == NULL && np) { | |
401 | spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL); | |
402 | if (!spicfg) | |
403 | return -ENOMEM; | |
404 | *spicfg = davinci_spi_default_cfg; | |
405 | /* override with dt configured values */ | |
406 | if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) | |
407 | spicfg->wdelay = (u8)prop; | |
408 | spi->controller_data = spicfg; | |
3e2e1258 FP |
409 | |
410 | if (dspi->dma_rx && dspi->dma_tx) | |
411 | spicfg->io_type = SPI_IO_TYPE_DMA; | |
365a7bb3 MK |
412 | } |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
358934a6 SP |
417 | /** |
418 | * davinci_spi_setup - This functions will set default transfer method | |
419 | * @spi: spi device on which data transfer to be done | |
420 | * | |
421 | * This functions sets the default transfer method. | |
422 | */ | |
358934a6 SP |
423 | static int davinci_spi_setup(struct spi_device *spi) |
424 | { | |
212d4b69 | 425 | struct davinci_spi *dspi; |
a88e34ea MK |
426 | struct device_node *np = spi->dev.of_node; |
427 | bool internal_cs = true; | |
358934a6 | 428 | |
212d4b69 | 429 | dspi = spi_master_get_devdata(spi->master); |
358934a6 | 430 | |
be88471b | 431 | if (!(spi->mode & SPI_NO_CS)) { |
101a68e7 | 432 | if (np && spi->cs_gpiod) |
a88e34ea | 433 | internal_cs = false; |
c0600140 | 434 | |
101a68e7 | 435 | if (internal_cs) |
3f2dad99 GS |
436 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
437 | } | |
a88e34ea | 438 | |
be88471b | 439 | if (spi->mode & SPI_READY) |
212d4b69 | 440 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
441 | |
442 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 443 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 444 | else |
212d4b69 | 445 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 446 | |
365a7bb3 MK |
447 | return davinci_spi_of_setup(spi); |
448 | } | |
449 | ||
450 | static void davinci_spi_cleanup(struct spi_device *spi) | |
451 | { | |
452 | struct davinci_spi_config *spicfg = spi->controller_data; | |
453 | ||
454 | spi->controller_data = NULL; | |
455 | if (spi->dev.of_node) | |
456 | kfree(spicfg); | |
358934a6 SP |
457 | } |
458 | ||
8aedbf58 FP |
459 | static bool davinci_spi_can_dma(struct spi_master *master, |
460 | struct spi_device *spi, | |
461 | struct spi_transfer *xfer) | |
462 | { | |
463 | struct davinci_spi_config *spicfg = spi->controller_data; | |
464 | bool can_dma = false; | |
465 | ||
466 | if (spicfg) | |
0718b764 | 467 | can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) && |
4dd9becb FI |
468 | (xfer->len >= DMA_MIN_BYTES) && |
469 | !is_vmalloc_addr(xfer->rx_buf) && | |
470 | !is_vmalloc_addr(xfer->tx_buf); | |
8aedbf58 FP |
471 | |
472 | return can_dma; | |
473 | } | |
474 | ||
212d4b69 | 475 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 476 | { |
212d4b69 | 477 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
478 | |
479 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
21c015b7 | 480 | dev_err(sdev, "SPI Time-out Error\n"); |
358934a6 SP |
481 | return -ETIMEDOUT; |
482 | } | |
483 | if (int_status & SPIFLG_DESYNC_MASK) { | |
21c015b7 | 484 | dev_err(sdev, "SPI Desynchronization Error\n"); |
358934a6 SP |
485 | return -EIO; |
486 | } | |
487 | if (int_status & SPIFLG_BITERR_MASK) { | |
21c015b7 | 488 | dev_err(sdev, "SPI Bit error\n"); |
358934a6 SP |
489 | return -EIO; |
490 | } | |
491 | ||
212d4b69 | 492 | if (dspi->version == SPI_VERSION_2) { |
358934a6 | 493 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
21c015b7 | 494 | dev_err(sdev, "SPI Data Length Error\n"); |
358934a6 SP |
495 | return -EIO; |
496 | } | |
497 | if (int_status & SPIFLG_PARERR_MASK) { | |
21c015b7 | 498 | dev_err(sdev, "SPI Parity Error\n"); |
358934a6 SP |
499 | return -EIO; |
500 | } | |
501 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
21c015b7 | 502 | dev_err(sdev, "SPI Data Overrun error\n"); |
358934a6 SP |
503 | return -EIO; |
504 | } | |
358934a6 | 505 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
21c015b7 | 506 | dev_err(sdev, "SPI Buffer Init Active\n"); |
358934a6 SP |
507 | return -EBUSY; |
508 | } | |
509 | } | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
e0d205e9 BN |
514 | /** |
515 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 516 | * @dspi: the controller data |
e0d205e9 BN |
517 | * |
518 | * This function will check the SPIFLG register and handle any events that are | |
519 | * detected there | |
520 | */ | |
212d4b69 | 521 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 522 | { |
212d4b69 | 523 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 524 | |
212d4b69 | 525 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 526 | |
212d4b69 SN |
527 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
528 | dspi->get_rx(buf & 0xFFFF, dspi); | |
529 | dspi->rcount--; | |
e0d205e9 BN |
530 | } |
531 | ||
212d4b69 | 532 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
533 | |
534 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
535 | errors = status & SPIFLG_ERROR_MASK; | |
536 | goto out; | |
537 | } | |
538 | ||
212d4b69 SN |
539 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
540 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
541 | dspi->wcount--; | |
542 | spidat1 &= ~0xFFFF; | |
543 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
544 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
545 | } |
546 | ||
547 | out: | |
548 | return errors; | |
549 | } | |
550 | ||
048177ce | 551 | static void davinci_spi_dma_rx_callback(void *data) |
87467bd9 | 552 | { |
048177ce | 553 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
87467bd9 | 554 | |
048177ce | 555 | dspi->rcount = 0; |
87467bd9 | 556 | |
048177ce MP |
557 | if (!dspi->wcount && !dspi->rcount) |
558 | complete(&dspi->done); | |
559 | } | |
87467bd9 | 560 | |
048177ce MP |
561 | static void davinci_spi_dma_tx_callback(void *data) |
562 | { | |
563 | struct davinci_spi *dspi = (struct davinci_spi *)data; | |
564 | ||
565 | dspi->wcount = 0; | |
566 | ||
567 | if (!dspi->wcount && !dspi->rcount) | |
212d4b69 | 568 | complete(&dspi->done); |
87467bd9 BN |
569 | } |
570 | ||
358934a6 SP |
571 | /** |
572 | * davinci_spi_bufs - functions which will handle transfer data | |
573 | * @spi: spi device on which data transfer to be done | |
574 | * @t: spi transfer in which transfer info is filled | |
575 | * | |
576 | * This function will put data to be transferred into data register | |
577 | * of SPI controller and then wait until the completion will be marked | |
578 | * by the IRQ Handler. | |
579 | */ | |
87467bd9 | 580 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 581 | { |
212d4b69 | 582 | struct davinci_spi *dspi; |
048177ce | 583 | int data_type, ret = -ENOMEM; |
212d4b69 | 584 | u32 tx_data, spidat1; |
839c996c | 585 | u32 errors = 0; |
e0d205e9 | 586 | struct davinci_spi_config *spicfg; |
358934a6 | 587 | struct davinci_spi_platform_data *pdata; |
87467bd9 | 588 | unsigned uninitialized_var(rx_buf_count); |
358934a6 | 589 | |
212d4b69 | 590 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 591 | pdata = &dspi->pdata; |
e0d205e9 BN |
592 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
593 | if (!spicfg) | |
594 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
595 | |
596 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 597 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 598 | |
212d4b69 SN |
599 | dspi->tx = t->tx_buf; |
600 | dspi->rx = t->rx_buf; | |
601 | dspi->wcount = t->len / data_type; | |
602 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 603 | |
212d4b69 | 604 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 605 | |
212d4b69 SN |
606 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
607 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 608 | |
16735d02 | 609 | reinit_completion(&dspi->done); |
87467bd9 | 610 | |
0718b764 FI |
611 | if (!davinci_spi_can_dma(spi->master, spi, t)) { |
612 | if (spicfg->io_type != SPI_IO_TYPE_POLL) | |
613 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); | |
87467bd9 | 614 | /* start the transfer */ |
212d4b69 SN |
615 | dspi->wcount--; |
616 | tx_data = dspi->get_tx(dspi); | |
617 | spidat1 &= 0xFFFF0000; | |
618 | spidat1 |= tx_data & 0xFFFF; | |
619 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 620 | } else { |
048177ce MP |
621 | struct dma_slave_config dma_rx_conf = { |
622 | .direction = DMA_DEV_TO_MEM, | |
623 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | |
624 | .src_addr_width = data_type, | |
625 | .src_maxburst = 1, | |
626 | }; | |
627 | struct dma_slave_config dma_tx_conf = { | |
628 | .direction = DMA_MEM_TO_DEV, | |
629 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | |
630 | .dst_addr_width = data_type, | |
631 | .dst_maxburst = 1, | |
632 | }; | |
633 | struct dma_async_tx_descriptor *rxdesc; | |
634 | struct dma_async_tx_descriptor *txdesc; | |
048177ce MP |
635 | |
636 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | |
637 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | |
638 | ||
048177ce | 639 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, |
8aedbf58 | 640 | t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM, |
048177ce MP |
641 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
642 | if (!rxdesc) | |
643 | goto err_desc; | |
644 | ||
6b3a631e | 645 | if (!t->tx_buf) { |
1234e839 FI |
646 | /* To avoid errors when doing rx-only transfers with |
647 | * many SG entries (> 20), use the rx buffer as the | |
648 | * dummy tx buffer so that dma reloads are done at the | |
649 | * same time for rx and tx. | |
650 | */ | |
6b3a631e FI |
651 | t->tx_sg.sgl = t->rx_sg.sgl; |
652 | t->tx_sg.nents = t->rx_sg.nents; | |
653 | } | |
654 | ||
048177ce | 655 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, |
8aedbf58 | 656 | t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, |
048177ce MP |
657 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
658 | if (!txdesc) | |
659 | goto err_desc; | |
660 | ||
661 | rxdesc->callback = davinci_spi_dma_rx_callback; | |
662 | rxdesc->callback_param = (void *)dspi; | |
663 | txdesc->callback = davinci_spi_dma_tx_callback; | |
664 | txdesc->callback_param = (void *)dspi; | |
87467bd9 BN |
665 | |
666 | if (pdata->cshold_bug) | |
212d4b69 | 667 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 668 | |
048177ce MP |
669 | dmaengine_submit(rxdesc); |
670 | dmaengine_submit(txdesc); | |
671 | ||
672 | dma_async_issue_pending(dspi->dma_rx); | |
673 | dma_async_issue_pending(dspi->dma_tx); | |
674 | ||
212d4b69 | 675 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 676 | } |
358934a6 | 677 | |
e0d205e9 | 678 | /* Wait for the transfer to complete */ |
87467bd9 | 679 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
7f3ac71a SN |
680 | if (wait_for_completion_timeout(&dspi->done, HZ) == 0) |
681 | errors = SPIFLG_TIMEOUT_MASK; | |
e0d205e9 | 682 | } else { |
212d4b69 SN |
683 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
684 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
685 | if (errors) |
686 | break; | |
687 | cpu_relax(); | |
358934a6 SP |
688 | } |
689 | } | |
690 | ||
212d4b69 | 691 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
0718b764 | 692 | if (davinci_spi_can_dma(spi->master, spi, t)) |
212d4b69 | 693 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
048177ce | 694 | |
212d4b69 SN |
695 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
696 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 697 | |
358934a6 SP |
698 | /* |
699 | * Check for bit error, desync error,parity error,timeout error and | |
700 | * receive overflow errors | |
701 | */ | |
839c996c | 702 | if (errors) { |
212d4b69 | 703 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
704 | WARN(!ret, "%s: error reported but no error found!\n", |
705 | dev_name(&spi->dev)); | |
358934a6 | 706 | return ret; |
839c996c | 707 | } |
358934a6 | 708 | |
212d4b69 | 709 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
048177ce | 710 | dev_err(&spi->dev, "SPI data transfer error\n"); |
87467bd9 BN |
711 | return -EIO; |
712 | } | |
713 | ||
358934a6 | 714 | return t->len; |
048177ce MP |
715 | |
716 | err_desc: | |
048177ce | 717 | return ret; |
358934a6 SP |
718 | } |
719 | ||
32310aaf MK |
720 | /** |
721 | * dummy_thread_fn - dummy thread function | |
722 | * @irq: IRQ number for this SPI Master | |
723 | * @context_data: structure for SPI Master controller davinci_spi | |
724 | * | |
725 | * This is to satisfy the request_threaded_irq() API so that the irq | |
726 | * handler is called in interrupt context. | |
727 | */ | |
728 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | |
729 | { | |
730 | return IRQ_HANDLED; | |
731 | } | |
732 | ||
e0d205e9 BN |
733 | /** |
734 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
735 | * @irq: IRQ number for this SPI Master | |
736 | * @context_data: structure for SPI Master controller davinci_spi | |
737 | * | |
738 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
739 | * According to command it will do the appropriate action. It will check | |
740 | * transfer length and if it is not zero then dispatch transfer command again. | |
741 | * If transfer length is zero then it will indicate the COMPLETION so that | |
742 | * davinci_spi_bufs function can go ahead. | |
743 | */ | |
212d4b69 | 744 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 745 | { |
212d4b69 | 746 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
747 | int status; |
748 | ||
212d4b69 | 749 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 750 | if (unlikely(status != 0)) |
212d4b69 | 751 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 752 | |
212d4b69 SN |
753 | if ((!dspi->rcount && !dspi->wcount) || status) |
754 | complete(&dspi->done); | |
e0d205e9 BN |
755 | |
756 | return IRQ_HANDLED; | |
757 | } | |
758 | ||
212d4b69 | 759 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b | 760 | { |
048177ce | 761 | struct device *sdev = dspi->bitbang.master->dev.parent; |
048177ce | 762 | |
fe5fd254 PU |
763 | dspi->dma_rx = dma_request_chan(sdev, "rx"); |
764 | if (IS_ERR(dspi->dma_rx)) | |
765 | return PTR_ERR(dspi->dma_rx); | |
903ca25b | 766 | |
fe5fd254 PU |
767 | dspi->dma_tx = dma_request_chan(sdev, "tx"); |
768 | if (IS_ERR(dspi->dma_tx)) { | |
769 | dma_release_channel(dspi->dma_rx); | |
770 | return PTR_ERR(dspi->dma_tx); | |
903ca25b SN |
771 | } |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
aae7147d | 776 | #if defined(CONFIG_OF) |
fa466c91 FCJ |
777 | |
778 | /* OF SPI data structure */ | |
779 | struct davinci_spi_of_data { | |
780 | u8 version; | |
781 | u8 prescaler_limit; | |
782 | }; | |
783 | ||
784 | static const struct davinci_spi_of_data dm6441_spi_data = { | |
785 | .version = SPI_VERSION_1, | |
786 | .prescaler_limit = 2, | |
787 | }; | |
788 | ||
789 | static const struct davinci_spi_of_data da830_spi_data = { | |
790 | .version = SPI_VERSION_2, | |
791 | .prescaler_limit = 2, | |
792 | }; | |
793 | ||
794 | static const struct davinci_spi_of_data keystone_spi_data = { | |
795 | .version = SPI_VERSION_1, | |
796 | .prescaler_limit = 0, | |
797 | }; | |
798 | ||
aae7147d MK |
799 | static const struct of_device_id davinci_spi_of_match[] = { |
800 | { | |
804413f2 | 801 | .compatible = "ti,dm6441-spi", |
fa466c91 | 802 | .data = &dm6441_spi_data, |
aae7147d MK |
803 | }, |
804 | { | |
804413f2 | 805 | .compatible = "ti,da830-spi", |
fa466c91 FCJ |
806 | .data = &da830_spi_data, |
807 | }, | |
808 | { | |
809 | .compatible = "ti,keystone-spi", | |
810 | .data = &keystone_spi_data, | |
aae7147d MK |
811 | }, |
812 | { }, | |
813 | }; | |
0d2d0cc5 | 814 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
aae7147d MK |
815 | |
816 | /** | |
817 | * spi_davinci_get_pdata - Get platform data from DTS binding | |
818 | * @pdev: ptr to platform data | |
819 | * @dspi: ptr to driver data | |
820 | * | |
821 | * Parses and populates pdata in dspi from device tree bindings. | |
822 | * | |
823 | * NOTE: Not all platform data params are supported currently. | |
824 | */ | |
825 | static int spi_davinci_get_pdata(struct platform_device *pdev, | |
826 | struct davinci_spi *dspi) | |
827 | { | |
828 | struct device_node *node = pdev->dev.of_node; | |
fa466c91 | 829 | struct davinci_spi_of_data *spi_data; |
aae7147d MK |
830 | struct davinci_spi_platform_data *pdata; |
831 | unsigned int num_cs, intr_line = 0; | |
832 | const struct of_device_id *match; | |
833 | ||
834 | pdata = &dspi->pdata; | |
835 | ||
b53b34f0 | 836 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
aae7147d MK |
837 | if (!match) |
838 | return -ENODEV; | |
839 | ||
fa466c91 | 840 | spi_data = (struct davinci_spi_of_data *)match->data; |
aae7147d | 841 | |
fa466c91 FCJ |
842 | pdata->version = spi_data->version; |
843 | pdata->prescaler_limit = spi_data->prescaler_limit; | |
aae7147d MK |
844 | /* |
845 | * default num_cs is 1 and all chipsel are internal to the chip | |
a88e34ea MK |
846 | * indicated by chip_sel being NULL or cs_gpios being NULL or |
847 | * set to -ENOENT. num-cs includes internal as well as gpios. | |
aae7147d MK |
848 | * indicated by chip_sel being NULL. GPIO based CS is not |
849 | * supported yet in DT bindings. | |
850 | */ | |
851 | num_cs = 1; | |
852 | of_property_read_u32(node, "num-cs", &num_cs); | |
853 | pdata->num_chipselect = num_cs; | |
854 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | |
855 | pdata->intr_line = intr_line; | |
856 | return 0; | |
857 | } | |
858 | #else | |
2b747a5f AY |
859 | static int spi_davinci_get_pdata(struct platform_device *pdev, |
860 | struct davinci_spi *dspi) | |
aae7147d MK |
861 | { |
862 | return -ENODEV; | |
863 | } | |
864 | #endif | |
865 | ||
358934a6 SP |
866 | /** |
867 | * davinci_spi_probe - probe function for SPI Master Controller | |
868 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
869 | * |
870 | * According to Linux Device Model this function will be invoked by Linux | |
871 | * with platform_device struct which contains the device specific info. | |
872 | * This function will map the SPI controller's memory, register IRQ, | |
873 | * Reset SPI controller and setting its registers to default value. | |
874 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
875 | * can register transfer method to work queue. | |
358934a6 | 876 | */ |
fd4a319b | 877 | static int davinci_spi_probe(struct platform_device *pdev) |
358934a6 SP |
878 | { |
879 | struct spi_master *master; | |
212d4b69 | 880 | struct davinci_spi *dspi; |
358934a6 | 881 | struct davinci_spi_platform_data *pdata; |
5b3bb596 | 882 | struct resource *r; |
c0600140 | 883 | int ret = 0; |
f34bd4cc | 884 | u32 spipc0; |
358934a6 | 885 | |
358934a6 SP |
886 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
887 | if (master == NULL) { | |
888 | ret = -ENOMEM; | |
889 | goto err; | |
890 | } | |
891 | ||
24b5a82c | 892 | platform_set_drvdata(pdev, master); |
358934a6 | 893 | |
212d4b69 | 894 | dspi = spi_master_get_devdata(master); |
358934a6 | 895 | |
8074cf06 JH |
896 | if (dev_get_platdata(&pdev->dev)) { |
897 | pdata = dev_get_platdata(&pdev->dev); | |
aae7147d MK |
898 | dspi->pdata = *pdata; |
899 | } else { | |
900 | /* update dspi pdata with that from the DT */ | |
901 | ret = spi_davinci_get_pdata(pdev, dspi); | |
902 | if (ret < 0) | |
903 | goto free_master; | |
904 | } | |
905 | ||
906 | /* pdata in dspi is now updated and point pdata to that */ | |
907 | pdata = &dspi->pdata; | |
908 | ||
a86854d0 KC |
909 | dspi->bytes_per_word = devm_kcalloc(&pdev->dev, |
910 | pdata->num_chipselect, | |
911 | sizeof(*dspi->bytes_per_word), | |
912 | GFP_KERNEL); | |
7480e755 MK |
913 | if (dspi->bytes_per_word == NULL) { |
914 | ret = -ENOMEM; | |
915 | goto free_master; | |
916 | } | |
917 | ||
358934a6 SP |
918 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
919 | if (r == NULL) { | |
920 | ret = -ENOENT; | |
921 | goto free_master; | |
922 | } | |
923 | ||
212d4b69 | 924 | dspi->pbase = r->start; |
358934a6 | 925 | |
5b3bb596 JH |
926 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
927 | if (IS_ERR(dspi->base)) { | |
928 | ret = PTR_ERR(dspi->base); | |
358934a6 SP |
929 | goto free_master; |
930 | } | |
931 | ||
87248dc7 MD |
932 | init_completion(&dspi->done); |
933 | ||
8494cdea AH |
934 | ret = platform_get_irq(pdev, 0); |
935 | if (ret == 0) | |
e0d205e9 | 936 | ret = -EINVAL; |
8494cdea | 937 | if (ret < 0) |
5b3bb596 | 938 | goto free_master; |
8494cdea | 939 | dspi->irq = ret; |
e0d205e9 | 940 | |
5b3bb596 JH |
941 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
942 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); | |
e0d205e9 | 943 | if (ret) |
5b3bb596 | 944 | goto free_master; |
e0d205e9 | 945 | |
94c69f76 | 946 | dspi->bitbang.master = master; |
358934a6 | 947 | |
5b3bb596 | 948 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
212d4b69 | 949 | if (IS_ERR(dspi->clk)) { |
358934a6 | 950 | ret = -ENODEV; |
5b3bb596 | 951 | goto free_master; |
358934a6 | 952 | } |
35fc3b9f AY |
953 | ret = clk_prepare_enable(dspi->clk); |
954 | if (ret) | |
955 | goto free_master; | |
358934a6 | 956 | |
101a68e7 | 957 | master->use_gpio_descriptors = true; |
aae7147d | 958 | master->dev.of_node = pdev->dev.of_node; |
358934a6 SP |
959 | master->bus_num = pdev->id; |
960 | master->num_chipselect = pdata->num_chipselect; | |
24778be2 | 961 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
6b3a631e | 962 | master->flags = SPI_MASTER_MUST_RX; |
358934a6 | 963 | master->setup = davinci_spi_setup; |
365a7bb3 | 964 | master->cleanup = davinci_spi_cleanup; |
8aedbf58 | 965 | master->can_dma = davinci_spi_can_dma; |
358934a6 | 966 | |
212d4b69 SN |
967 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
968 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
fa466c91 | 969 | dspi->prescaler_limit = pdata->prescaler_limit; |
212d4b69 | 970 | dspi->version = pdata->version; |
358934a6 | 971 | |
a3762b13 | 972 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD; |
212d4b69 SN |
973 | if (dspi->version == SPI_VERSION_2) |
974 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 975 | |
212d4b69 | 976 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
fe5fd254 PU |
977 | |
978 | ret = davinci_spi_request_dma(dspi); | |
979 | if (ret == -EPROBE_DEFER) { | |
980 | goto free_clk; | |
981 | } else if (ret) { | |
982 | dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret); | |
983 | dspi->dma_rx = NULL; | |
984 | dspi->dma_tx = NULL; | |
358934a6 SP |
985 | } |
986 | ||
212d4b69 SN |
987 | dspi->get_rx = davinci_spi_rx_buf_u8; |
988 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 989 | |
358934a6 | 990 | /* Reset In/OUT SPI module */ |
212d4b69 | 991 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 992 | udelay(100); |
212d4b69 | 993 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 994 | |
be88471b | 995 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 996 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 997 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 998 | |
e0d205e9 | 999 | if (pdata->intr_line) |
212d4b69 | 1000 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 1001 | else |
212d4b69 | 1002 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 1003 | |
212d4b69 | 1004 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 1005 | |
358934a6 | 1006 | /* master mode default */ |
212d4b69 SN |
1007 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
1008 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1009 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 1010 | |
212d4b69 | 1011 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 1012 | if (ret) |
903ca25b | 1013 | goto free_dma; |
358934a6 | 1014 | |
212d4b69 | 1015 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 1016 | |
358934a6 SP |
1017 | return ret; |
1018 | ||
903ca25b | 1019 | free_dma: |
fe5fd254 PU |
1020 | if (dspi->dma_rx) { |
1021 | dma_release_channel(dspi->dma_rx); | |
1022 | dma_release_channel(dspi->dma_tx); | |
1023 | } | |
358934a6 | 1024 | free_clk: |
aae7147d | 1025 | clk_disable_unprepare(dspi->clk); |
358934a6 | 1026 | free_master: |
94c69f76 | 1027 | spi_master_put(master); |
358934a6 SP |
1028 | err: |
1029 | return ret; | |
1030 | } | |
1031 | ||
1032 | /** | |
1033 | * davinci_spi_remove - remove function for SPI Master Controller | |
1034 | * @pdev: platform_device structure which contains plateform specific data | |
1035 | * | |
1036 | * This function will do the reverse action of davinci_spi_probe function | |
1037 | * It will free the IRQ and SPI controller's memory region. | |
1038 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1039 | * created by spi_bitbang_start. | |
1040 | */ | |
fd4a319b | 1041 | static int davinci_spi_remove(struct platform_device *pdev) |
358934a6 | 1042 | { |
212d4b69 | 1043 | struct davinci_spi *dspi; |
358934a6 SP |
1044 | struct spi_master *master; |
1045 | ||
24b5a82c | 1046 | master = platform_get_drvdata(pdev); |
212d4b69 | 1047 | dspi = spi_master_get_devdata(master); |
358934a6 | 1048 | |
212d4b69 | 1049 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 1050 | |
aae7147d | 1051 | clk_disable_unprepare(dspi->clk); |
94c69f76 | 1052 | spi_master_put(master); |
358934a6 | 1053 | |
fe5fd254 PU |
1054 | if (dspi->dma_rx) { |
1055 | dma_release_channel(dspi->dma_rx); | |
1056 | dma_release_channel(dspi->dma_tx); | |
1057 | } | |
1058 | ||
358934a6 SP |
1059 | return 0; |
1060 | } | |
1061 | ||
1062 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1063 | .driver = { |
1064 | .name = "spi_davinci", | |
b53b34f0 | 1065 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
d8c174cd | 1066 | }, |
940ab889 | 1067 | .probe = davinci_spi_probe, |
fd4a319b | 1068 | .remove = davinci_spi_remove, |
358934a6 | 1069 | }; |
940ab889 | 1070 | module_platform_driver(davinci_spi_driver); |
358934a6 SP |
1071 | |
1072 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1073 | MODULE_LICENSE("GPL"); |