Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
358934a6 SP |
2 | /* |
3 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 4 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
5 | */ |
6 | ||
7 | #include <linux/interrupt.h> | |
8 | #include <linux/io.h> | |
101a68e7 | 9 | #include <linux/gpio/consumer.h> |
358934a6 SP |
10 | #include <linux/module.h> |
11 | #include <linux/delay.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/clk.h> | |
048177ce | 15 | #include <linux/dmaengine.h> |
358934a6 | 16 | #include <linux/dma-mapping.h> |
aae7147d MK |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
358934a6 SP |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
358934a6 | 22 | |
ec2a0833 | 23 | #include <linux/platform_data/spi-davinci.h> |
358934a6 | 24 | |
358934a6 SP |
25 | #define CS_DEFAULT 0xFF |
26 | ||
358934a6 SP |
27 | #define SPIFMT_PHASE_MASK BIT(16) |
28 | #define SPIFMT_POLARITY_MASK BIT(17) | |
29 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
30 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
31 | #define SPIFMT_WAITENA_MASK BIT(21) | |
32 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
33 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
34 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
35 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 36 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 37 | |
358934a6 SP |
38 | /* SPIPC0 */ |
39 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
40 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
41 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
42 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
43 | |
44 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
45 | #define SPIINT_MASKINT 0x0000015F |
46 | #define SPI_INTLVL_1 0x000001FF | |
47 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 48 | |
cfbc5d1d BN |
49 | /* SPIDAT1 (upper 16 bit defines) */ |
50 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
365a7bb3 | 51 | #define SPIDAT1_WDEL BIT(10) |
cfbc5d1d BN |
52 | |
53 | /* SPIGCR1 */ | |
358934a6 SP |
54 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
55 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 56 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 57 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 58 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
59 | |
60 | /* SPIBUF */ | |
61 | #define SPIBUF_TXFULL_MASK BIT(29) | |
62 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
63 | ||
7abbf23c BN |
64 | /* SPIDELAY */ |
65 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
66 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
67 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
68 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
69 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
70 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
71 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
72 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
73 | ||
358934a6 SP |
74 | /* Error Masks */ |
75 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
76 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
77 | #define SPIFLG_PARERR_MASK BIT(2) | |
78 | #define SPIFLG_DESYNC_MASK BIT(3) | |
79 | #define SPIFLG_BITERR_MASK BIT(4) | |
80 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 81 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
82 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
83 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
84 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
85 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 86 | |
358934a6 | 87 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 88 | |
358934a6 SP |
89 | /* SPI Controller registers */ |
90 | #define SPIGCR0 0x00 | |
91 | #define SPIGCR1 0x04 | |
92 | #define SPIINT 0x08 | |
93 | #define SPILVL 0x0c | |
94 | #define SPIFLG 0x10 | |
95 | #define SPIPC0 0x14 | |
358934a6 SP |
96 | #define SPIDAT1 0x3c |
97 | #define SPIBUF 0x40 | |
358934a6 SP |
98 | #define SPIDELAY 0x48 |
99 | #define SPIDEF 0x4c | |
100 | #define SPIFMT0 0x50 | |
358934a6 | 101 | |
0718b764 FI |
102 | #define DMA_MIN_BYTES 16 |
103 | ||
358934a6 SP |
104 | /* SPI Controller driver's private data. */ |
105 | struct davinci_spi { | |
106 | struct spi_bitbang bitbang; | |
107 | struct clk *clk; | |
108 | ||
109 | u8 version; | |
110 | resource_size_t pbase; | |
111 | void __iomem *base; | |
e0d205e9 BN |
112 | u32 irq; |
113 | struct completion done; | |
358934a6 SP |
114 | |
115 | const void *tx; | |
116 | void *rx; | |
e0d205e9 BN |
117 | int rcount; |
118 | int wcount; | |
048177ce MP |
119 | |
120 | struct dma_chan *dma_rx; | |
121 | struct dma_chan *dma_tx; | |
048177ce | 122 | |
aae7147d | 123 | struct davinci_spi_platform_data pdata; |
358934a6 SP |
124 | |
125 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
126 | u32 (*get_tx)(struct davinci_spi *); | |
127 | ||
7480e755 | 128 | u8 *bytes_per_word; |
fa466c91 FCJ |
129 | |
130 | u8 prescaler_limit; | |
358934a6 SP |
131 | }; |
132 | ||
53a31b07 BN |
133 | static struct davinci_spi_config davinci_spi_default_cfg; |
134 | ||
212d4b69 | 135 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 136 | { |
212d4b69 SN |
137 | if (dspi->rx) { |
138 | u8 *rx = dspi->rx; | |
53d454a1 | 139 | *rx++ = (u8)data; |
212d4b69 | 140 | dspi->rx = rx; |
53d454a1 | 141 | } |
358934a6 SP |
142 | } |
143 | ||
212d4b69 | 144 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 145 | { |
212d4b69 SN |
146 | if (dspi->rx) { |
147 | u16 *rx = dspi->rx; | |
53d454a1 | 148 | *rx++ = (u16)data; |
212d4b69 | 149 | dspi->rx = rx; |
53d454a1 | 150 | } |
358934a6 SP |
151 | } |
152 | ||
212d4b69 | 153 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 154 | { |
53d454a1 | 155 | u32 data = 0; |
859c3377 | 156 | |
212d4b69 SN |
157 | if (dspi->tx) { |
158 | const u8 *tx = dspi->tx; | |
859c3377 | 159 | |
53d454a1 | 160 | data = *tx++; |
212d4b69 | 161 | dspi->tx = tx; |
53d454a1 | 162 | } |
358934a6 SP |
163 | return data; |
164 | } | |
165 | ||
212d4b69 | 166 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 167 | { |
53d454a1 | 168 | u32 data = 0; |
859c3377 | 169 | |
212d4b69 SN |
170 | if (dspi->tx) { |
171 | const u16 *tx = dspi->tx; | |
859c3377 | 172 | |
53d454a1 | 173 | data = *tx++; |
212d4b69 | 174 | dspi->tx = tx; |
53d454a1 | 175 | } |
358934a6 SP |
176 | return data; |
177 | } | |
178 | ||
179 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
180 | { | |
181 | u32 v = ioread32(addr); | |
182 | ||
183 | v |= bits; | |
184 | iowrite32(v, addr); | |
185 | } | |
186 | ||
187 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
188 | { | |
189 | u32 v = ioread32(addr); | |
190 | ||
191 | v &= ~bits; | |
192 | iowrite32(v, addr); | |
193 | } | |
194 | ||
358934a6 SP |
195 | /* |
196 | * Interface to control the chip select signal | |
197 | */ | |
198 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
199 | { | |
212d4b69 | 200 | struct davinci_spi *dspi; |
365a7bb3 | 201 | struct davinci_spi_config *spicfg = spi->controller_data; |
7978b8c3 | 202 | u8 chip_sel = spi->chip_select; |
212d4b69 | 203 | u16 spidat1 = CS_DEFAULT; |
358934a6 | 204 | |
212d4b69 | 205 | dspi = spi_master_get_devdata(spi->master); |
358934a6 | 206 | |
365a7bb3 | 207 | /* program delay transfers if tx_delay is non zero */ |
563a53f3 | 208 | if (spicfg && spicfg->wdelay) |
365a7bb3 MK |
209 | spidat1 |= SPIDAT1_WDEL; |
210 | ||
358934a6 SP |
211 | /* |
212 | * Board specific chip select logic decides the polarity and cs | |
213 | * line for the controller | |
214 | */ | |
101a68e7 LW |
215 | if (spi->cs_gpiod) { |
216 | /* | |
217 | * FIXME: is this code ever executed? This host does not | |
218 | * set SPI_MASTER_GPIO_SS so this chipselect callback should | |
219 | * not get called from the SPI core when we are using | |
220 | * GPIOs for chip select. | |
221 | */ | |
23853973 | 222 | if (value == BITBANG_CS_ACTIVE) |
101a68e7 | 223 | gpiod_set_value(spi->cs_gpiod, 1); |
23853973 | 224 | else |
101a68e7 | 225 | gpiod_set_value(spi->cs_gpiod, 0); |
23853973 BN |
226 | } else { |
227 | if (value == BITBANG_CS_ACTIVE) { | |
a3762b13 DL |
228 | if (!(spi->mode & SPI_CS_WORD)) |
229 | spidat1 |= SPIDAT1_CSHOLD_MASK; | |
212d4b69 | 230 | spidat1 &= ~(0x1 << chip_sel); |
23853973 | 231 | } |
23853973 | 232 | } |
365a7bb3 MK |
233 | |
234 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); | |
358934a6 SP |
235 | } |
236 | ||
7fe0092b BN |
237 | /** |
238 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
f6305d27 LJ |
239 | * @dspi: the controller data |
240 | * @max_speed_hz: the maximum rate the SPI clock can run at | |
7fe0092b BN |
241 | * |
242 | * This function calculates the prescale value that generates a clock rate | |
243 | * less than or equal to the specified maximum. | |
244 | * | |
bba732d8 | 245 | * Returns: calculated prescale value for easy programming into SPI registers |
7fe0092b BN |
246 | * or negative error number if valid prescalar cannot be updated. |
247 | */ | |
212d4b69 | 248 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
249 | u32 max_speed_hz) |
250 | { | |
251 | int ret; | |
252 | ||
bba732d8 FCJ |
253 | /* Subtract 1 to match what will be programmed into SPI register. */ |
254 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1; | |
7fe0092b | 255 | |
fa466c91 | 256 | if (ret < dspi->prescaler_limit || ret > 255) |
7fe0092b BN |
257 | return -EINVAL; |
258 | ||
bba732d8 | 259 | return ret; |
7fe0092b BN |
260 | } |
261 | ||
358934a6 SP |
262 | /** |
263 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
264 | * @spi: spi device on which data transfer to be done | |
265 | * @t: spi transfer in which transfer info is filled | |
266 | * | |
267 | * This function determines data transfer method (8/16/32 bit transfer). | |
268 | * It will also set the SPI Clock Control register according to | |
269 | * SPI slave device freq. | |
270 | */ | |
271 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
272 | struct spi_transfer *t) | |
273 | { | |
274 | ||
212d4b69 | 275 | struct davinci_spi *dspi; |
25f33512 | 276 | struct davinci_spi_config *spicfg; |
358934a6 | 277 | u8 bits_per_word = 0; |
32ea3944 SK |
278 | u32 hz = 0, spifmt = 0; |
279 | int prescale; | |
358934a6 | 280 | |
212d4b69 | 281 | dspi = spi_master_get_devdata(spi->master); |
365a7bb3 | 282 | spicfg = spi->controller_data; |
25f33512 BN |
283 | if (!spicfg) |
284 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
285 | |
286 | if (t) { | |
287 | bits_per_word = t->bits_per_word; | |
288 | hz = t->speed_hz; | |
289 | } | |
290 | ||
291 | /* if bits_per_word is not set then set it default */ | |
292 | if (!bits_per_word) | |
293 | bits_per_word = spi->bits_per_word; | |
294 | ||
295 | /* | |
296 | * Assign function pointer to appropriate transfer method | |
297 | * 8bit, 16bit or 32bit transfer | |
298 | */ | |
24778be2 | 299 | if (bits_per_word <= 8) { |
212d4b69 SN |
300 | dspi->get_rx = davinci_spi_rx_buf_u8; |
301 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
302 | dspi->bytes_per_word[spi->chip_select] = 1; | |
24778be2 | 303 | } else { |
212d4b69 SN |
304 | dspi->get_rx = davinci_spi_rx_buf_u16; |
305 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
306 | dspi->bytes_per_word[spi->chip_select] = 2; | |
24778be2 | 307 | } |
358934a6 SP |
308 | |
309 | if (!hz) | |
310 | hz = spi->max_speed_hz; | |
311 | ||
25f33512 BN |
312 | /* Set up SPIFMTn register, unique to this chipselect. */ |
313 | ||
212d4b69 | 314 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
315 | if (prescale < 0) |
316 | return prescale; | |
317 | ||
25f33512 BN |
318 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
319 | ||
320 | if (spi->mode & SPI_LSB_FIRST) | |
321 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
322 | ||
323 | if (spi->mode & SPI_CPOL) | |
324 | spifmt |= SPIFMT_POLARITY_MASK; | |
325 | ||
326 | if (!(spi->mode & SPI_CPHA)) | |
327 | spifmt |= SPIFMT_PHASE_MASK; | |
328 | ||
365a7bb3 MK |
329 | /* |
330 | * Assume wdelay is used only on SPI peripherals that has this field | |
331 | * in SPIFMTn register and when it's configured from board file or DT. | |
332 | */ | |
333 | if (spicfg->wdelay) | |
334 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) | |
335 | & SPIFMT_WDELAY_MASK); | |
336 | ||
25f33512 BN |
337 | /* |
338 | * Version 1 hardware supports two basic SPI modes: | |
339 | * - Standard SPI mode uses 4 pins, with chipselect | |
340 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
341 | * (distinct from SPI_3WIRE, with just one data wire; | |
342 | * or similar variants without MOSI or without MISO) | |
343 | * | |
344 | * Version 2 hardware supports an optional handshaking signal, | |
345 | * so it can support two more modes: | |
346 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
347 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
348 | */ | |
349 | ||
212d4b69 | 350 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 351 | |
7abbf23c BN |
352 | u32 delay = 0; |
353 | ||
25f33512 BN |
354 | if (spicfg->odd_parity) |
355 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
356 | ||
357 | if (spicfg->parity_enable) | |
358 | spifmt |= SPIFMT_PARITYENA_MASK; | |
359 | ||
7abbf23c | 360 | if (spicfg->timer_disable) { |
25f33512 | 361 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
362 | } else { |
363 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
364 | & SPIDELAY_C2TDELAY_MASK; | |
365 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
366 | & SPIDELAY_T2CDELAY_MASK; | |
367 | } | |
25f33512 | 368 | |
7abbf23c | 369 | if (spi->mode & SPI_READY) { |
25f33512 | 370 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
371 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
372 | & SPIDELAY_T2EDELAY_MASK; | |
373 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
374 | & SPIDELAY_C2EDELAY_MASK; | |
375 | } | |
376 | ||
212d4b69 | 377 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
378 | } |
379 | ||
212d4b69 | 380 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
381 | |
382 | return 0; | |
383 | } | |
384 | ||
365a7bb3 MK |
385 | static int davinci_spi_of_setup(struct spi_device *spi) |
386 | { | |
387 | struct davinci_spi_config *spicfg = spi->controller_data; | |
388 | struct device_node *np = spi->dev.of_node; | |
3e2e1258 | 389 | struct davinci_spi *dspi = spi_master_get_devdata(spi->master); |
365a7bb3 MK |
390 | u32 prop; |
391 | ||
392 | if (spicfg == NULL && np) { | |
393 | spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL); | |
394 | if (!spicfg) | |
395 | return -ENOMEM; | |
396 | *spicfg = davinci_spi_default_cfg; | |
397 | /* override with dt configured values */ | |
398 | if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) | |
399 | spicfg->wdelay = (u8)prop; | |
400 | spi->controller_data = spicfg; | |
3e2e1258 FP |
401 | |
402 | if (dspi->dma_rx && dspi->dma_tx) | |
403 | spicfg->io_type = SPI_IO_TYPE_DMA; | |
365a7bb3 MK |
404 | } |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
358934a6 SP |
409 | /** |
410 | * davinci_spi_setup - This functions will set default transfer method | |
411 | * @spi: spi device on which data transfer to be done | |
412 | * | |
413 | * This functions sets the default transfer method. | |
414 | */ | |
358934a6 SP |
415 | static int davinci_spi_setup(struct spi_device *spi) |
416 | { | |
212d4b69 | 417 | struct davinci_spi *dspi; |
a88e34ea MK |
418 | struct device_node *np = spi->dev.of_node; |
419 | bool internal_cs = true; | |
358934a6 | 420 | |
212d4b69 | 421 | dspi = spi_master_get_devdata(spi->master); |
358934a6 | 422 | |
be88471b | 423 | if (!(spi->mode & SPI_NO_CS)) { |
101a68e7 | 424 | if (np && spi->cs_gpiod) |
a88e34ea | 425 | internal_cs = false; |
c0600140 | 426 | |
101a68e7 | 427 | if (internal_cs) |
3f2dad99 GS |
428 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
429 | } | |
a88e34ea | 430 | |
be88471b | 431 | if (spi->mode & SPI_READY) |
212d4b69 | 432 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
433 | |
434 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 435 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 436 | else |
212d4b69 | 437 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 438 | |
365a7bb3 MK |
439 | return davinci_spi_of_setup(spi); |
440 | } | |
441 | ||
442 | static void davinci_spi_cleanup(struct spi_device *spi) | |
443 | { | |
444 | struct davinci_spi_config *spicfg = spi->controller_data; | |
445 | ||
446 | spi->controller_data = NULL; | |
447 | if (spi->dev.of_node) | |
448 | kfree(spicfg); | |
358934a6 SP |
449 | } |
450 | ||
8aedbf58 FP |
451 | static bool davinci_spi_can_dma(struct spi_master *master, |
452 | struct spi_device *spi, | |
453 | struct spi_transfer *xfer) | |
454 | { | |
455 | struct davinci_spi_config *spicfg = spi->controller_data; | |
456 | bool can_dma = false; | |
457 | ||
458 | if (spicfg) | |
0718b764 | 459 | can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) && |
4dd9becb FI |
460 | (xfer->len >= DMA_MIN_BYTES) && |
461 | !is_vmalloc_addr(xfer->rx_buf) && | |
462 | !is_vmalloc_addr(xfer->tx_buf); | |
8aedbf58 FP |
463 | |
464 | return can_dma; | |
465 | } | |
466 | ||
212d4b69 | 467 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 468 | { |
212d4b69 | 469 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
470 | |
471 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
21c015b7 | 472 | dev_err(sdev, "SPI Time-out Error\n"); |
358934a6 SP |
473 | return -ETIMEDOUT; |
474 | } | |
475 | if (int_status & SPIFLG_DESYNC_MASK) { | |
21c015b7 | 476 | dev_err(sdev, "SPI Desynchronization Error\n"); |
358934a6 SP |
477 | return -EIO; |
478 | } | |
479 | if (int_status & SPIFLG_BITERR_MASK) { | |
21c015b7 | 480 | dev_err(sdev, "SPI Bit error\n"); |
358934a6 SP |
481 | return -EIO; |
482 | } | |
483 | ||
212d4b69 | 484 | if (dspi->version == SPI_VERSION_2) { |
358934a6 | 485 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
21c015b7 | 486 | dev_err(sdev, "SPI Data Length Error\n"); |
358934a6 SP |
487 | return -EIO; |
488 | } | |
489 | if (int_status & SPIFLG_PARERR_MASK) { | |
21c015b7 | 490 | dev_err(sdev, "SPI Parity Error\n"); |
358934a6 SP |
491 | return -EIO; |
492 | } | |
493 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
21c015b7 | 494 | dev_err(sdev, "SPI Data Overrun error\n"); |
358934a6 SP |
495 | return -EIO; |
496 | } | |
358934a6 | 497 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
21c015b7 | 498 | dev_err(sdev, "SPI Buffer Init Active\n"); |
358934a6 SP |
499 | return -EBUSY; |
500 | } | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
e0d205e9 BN |
506 | /** |
507 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 508 | * @dspi: the controller data |
e0d205e9 BN |
509 | * |
510 | * This function will check the SPIFLG register and handle any events that are | |
511 | * detected there | |
512 | */ | |
212d4b69 | 513 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 514 | { |
212d4b69 | 515 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 516 | |
212d4b69 | 517 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 518 | |
212d4b69 SN |
519 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
520 | dspi->get_rx(buf & 0xFFFF, dspi); | |
521 | dspi->rcount--; | |
e0d205e9 BN |
522 | } |
523 | ||
212d4b69 | 524 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
525 | |
526 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
527 | errors = status & SPIFLG_ERROR_MASK; | |
528 | goto out; | |
529 | } | |
530 | ||
212d4b69 SN |
531 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
532 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
533 | dspi->wcount--; | |
534 | spidat1 &= ~0xFFFF; | |
535 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
536 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
537 | } |
538 | ||
539 | out: | |
540 | return errors; | |
541 | } | |
542 | ||
048177ce | 543 | static void davinci_spi_dma_rx_callback(void *data) |
87467bd9 | 544 | { |
048177ce | 545 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
87467bd9 | 546 | |
048177ce | 547 | dspi->rcount = 0; |
87467bd9 | 548 | |
048177ce MP |
549 | if (!dspi->wcount && !dspi->rcount) |
550 | complete(&dspi->done); | |
551 | } | |
87467bd9 | 552 | |
048177ce MP |
553 | static void davinci_spi_dma_tx_callback(void *data) |
554 | { | |
555 | struct davinci_spi *dspi = (struct davinci_spi *)data; | |
556 | ||
557 | dspi->wcount = 0; | |
558 | ||
559 | if (!dspi->wcount && !dspi->rcount) | |
212d4b69 | 560 | complete(&dspi->done); |
87467bd9 BN |
561 | } |
562 | ||
358934a6 SP |
563 | /** |
564 | * davinci_spi_bufs - functions which will handle transfer data | |
565 | * @spi: spi device on which data transfer to be done | |
566 | * @t: spi transfer in which transfer info is filled | |
567 | * | |
568 | * This function will put data to be transferred into data register | |
569 | * of SPI controller and then wait until the completion will be marked | |
570 | * by the IRQ Handler. | |
571 | */ | |
87467bd9 | 572 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 573 | { |
212d4b69 | 574 | struct davinci_spi *dspi; |
048177ce | 575 | int data_type, ret = -ENOMEM; |
212d4b69 | 576 | u32 tx_data, spidat1; |
839c996c | 577 | u32 errors = 0; |
e0d205e9 | 578 | struct davinci_spi_config *spicfg; |
358934a6 SP |
579 | struct davinci_spi_platform_data *pdata; |
580 | ||
212d4b69 | 581 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 582 | pdata = &dspi->pdata; |
e0d205e9 BN |
583 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
584 | if (!spicfg) | |
585 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
586 | |
587 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 588 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 589 | |
212d4b69 SN |
590 | dspi->tx = t->tx_buf; |
591 | dspi->rx = t->rx_buf; | |
592 | dspi->wcount = t->len / data_type; | |
593 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 594 | |
212d4b69 | 595 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 596 | |
212d4b69 SN |
597 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
598 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 599 | |
16735d02 | 600 | reinit_completion(&dspi->done); |
87467bd9 | 601 | |
0718b764 FI |
602 | if (!davinci_spi_can_dma(spi->master, spi, t)) { |
603 | if (spicfg->io_type != SPI_IO_TYPE_POLL) | |
604 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); | |
87467bd9 | 605 | /* start the transfer */ |
212d4b69 SN |
606 | dspi->wcount--; |
607 | tx_data = dspi->get_tx(dspi); | |
608 | spidat1 &= 0xFFFF0000; | |
609 | spidat1 |= tx_data & 0xFFFF; | |
610 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 611 | } else { |
048177ce MP |
612 | struct dma_slave_config dma_rx_conf = { |
613 | .direction = DMA_DEV_TO_MEM, | |
614 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | |
615 | .src_addr_width = data_type, | |
616 | .src_maxburst = 1, | |
617 | }; | |
618 | struct dma_slave_config dma_tx_conf = { | |
619 | .direction = DMA_MEM_TO_DEV, | |
620 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | |
621 | .dst_addr_width = data_type, | |
622 | .dst_maxburst = 1, | |
623 | }; | |
624 | struct dma_async_tx_descriptor *rxdesc; | |
625 | struct dma_async_tx_descriptor *txdesc; | |
048177ce MP |
626 | |
627 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | |
628 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | |
629 | ||
048177ce | 630 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, |
8aedbf58 | 631 | t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM, |
048177ce MP |
632 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
633 | if (!rxdesc) | |
634 | goto err_desc; | |
635 | ||
6b3a631e | 636 | if (!t->tx_buf) { |
1234e839 FI |
637 | /* To avoid errors when doing rx-only transfers with |
638 | * many SG entries (> 20), use the rx buffer as the | |
639 | * dummy tx buffer so that dma reloads are done at the | |
640 | * same time for rx and tx. | |
641 | */ | |
6b3a631e FI |
642 | t->tx_sg.sgl = t->rx_sg.sgl; |
643 | t->tx_sg.nents = t->rx_sg.nents; | |
644 | } | |
645 | ||
048177ce | 646 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, |
8aedbf58 | 647 | t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, |
048177ce MP |
648 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
649 | if (!txdesc) | |
650 | goto err_desc; | |
651 | ||
652 | rxdesc->callback = davinci_spi_dma_rx_callback; | |
653 | rxdesc->callback_param = (void *)dspi; | |
654 | txdesc->callback = davinci_spi_dma_tx_callback; | |
655 | txdesc->callback_param = (void *)dspi; | |
87467bd9 BN |
656 | |
657 | if (pdata->cshold_bug) | |
212d4b69 | 658 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 659 | |
048177ce MP |
660 | dmaengine_submit(rxdesc); |
661 | dmaengine_submit(txdesc); | |
662 | ||
663 | dma_async_issue_pending(dspi->dma_rx); | |
664 | dma_async_issue_pending(dspi->dma_tx); | |
665 | ||
212d4b69 | 666 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 667 | } |
358934a6 | 668 | |
e0d205e9 | 669 | /* Wait for the transfer to complete */ |
87467bd9 | 670 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
7f3ac71a SN |
671 | if (wait_for_completion_timeout(&dspi->done, HZ) == 0) |
672 | errors = SPIFLG_TIMEOUT_MASK; | |
e0d205e9 | 673 | } else { |
212d4b69 SN |
674 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
675 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
676 | if (errors) |
677 | break; | |
678 | cpu_relax(); | |
358934a6 SP |
679 | } |
680 | } | |
681 | ||
212d4b69 | 682 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
0718b764 | 683 | if (davinci_spi_can_dma(spi->master, spi, t)) |
212d4b69 | 684 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
048177ce | 685 | |
212d4b69 SN |
686 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
687 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 688 | |
358934a6 SP |
689 | /* |
690 | * Check for bit error, desync error,parity error,timeout error and | |
691 | * receive overflow errors | |
692 | */ | |
839c996c | 693 | if (errors) { |
212d4b69 | 694 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
695 | WARN(!ret, "%s: error reported but no error found!\n", |
696 | dev_name(&spi->dev)); | |
358934a6 | 697 | return ret; |
839c996c | 698 | } |
358934a6 | 699 | |
212d4b69 | 700 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
048177ce | 701 | dev_err(&spi->dev, "SPI data transfer error\n"); |
87467bd9 BN |
702 | return -EIO; |
703 | } | |
704 | ||
358934a6 | 705 | return t->len; |
048177ce MP |
706 | |
707 | err_desc: | |
048177ce | 708 | return ret; |
358934a6 SP |
709 | } |
710 | ||
32310aaf MK |
711 | /** |
712 | * dummy_thread_fn - dummy thread function | |
713 | * @irq: IRQ number for this SPI Master | |
f6305d27 | 714 | * @data: structure for SPI Master controller davinci_spi |
32310aaf MK |
715 | * |
716 | * This is to satisfy the request_threaded_irq() API so that the irq | |
717 | * handler is called in interrupt context. | |
718 | */ | |
719 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | |
720 | { | |
721 | return IRQ_HANDLED; | |
722 | } | |
723 | ||
e0d205e9 BN |
724 | /** |
725 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
726 | * @irq: IRQ number for this SPI Master | |
f6305d27 | 727 | * @data: structure for SPI Master controller davinci_spi |
e0d205e9 BN |
728 | * |
729 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
730 | * According to command it will do the appropriate action. It will check | |
731 | * transfer length and if it is not zero then dispatch transfer command again. | |
732 | * If transfer length is zero then it will indicate the COMPLETION so that | |
733 | * davinci_spi_bufs function can go ahead. | |
734 | */ | |
212d4b69 | 735 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 736 | { |
212d4b69 | 737 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
738 | int status; |
739 | ||
212d4b69 | 740 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 741 | if (unlikely(status != 0)) |
212d4b69 | 742 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 743 | |
212d4b69 SN |
744 | if ((!dspi->rcount && !dspi->wcount) || status) |
745 | complete(&dspi->done); | |
e0d205e9 BN |
746 | |
747 | return IRQ_HANDLED; | |
748 | } | |
749 | ||
212d4b69 | 750 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b | 751 | { |
048177ce | 752 | struct device *sdev = dspi->bitbang.master->dev.parent; |
048177ce | 753 | |
fe5fd254 PU |
754 | dspi->dma_rx = dma_request_chan(sdev, "rx"); |
755 | if (IS_ERR(dspi->dma_rx)) | |
756 | return PTR_ERR(dspi->dma_rx); | |
903ca25b | 757 | |
fe5fd254 PU |
758 | dspi->dma_tx = dma_request_chan(sdev, "tx"); |
759 | if (IS_ERR(dspi->dma_tx)) { | |
760 | dma_release_channel(dspi->dma_rx); | |
761 | return PTR_ERR(dspi->dma_tx); | |
903ca25b SN |
762 | } |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
aae7147d | 767 | #if defined(CONFIG_OF) |
fa466c91 FCJ |
768 | |
769 | /* OF SPI data structure */ | |
770 | struct davinci_spi_of_data { | |
771 | u8 version; | |
772 | u8 prescaler_limit; | |
773 | }; | |
774 | ||
775 | static const struct davinci_spi_of_data dm6441_spi_data = { | |
776 | .version = SPI_VERSION_1, | |
777 | .prescaler_limit = 2, | |
778 | }; | |
779 | ||
780 | static const struct davinci_spi_of_data da830_spi_data = { | |
781 | .version = SPI_VERSION_2, | |
782 | .prescaler_limit = 2, | |
783 | }; | |
784 | ||
785 | static const struct davinci_spi_of_data keystone_spi_data = { | |
786 | .version = SPI_VERSION_1, | |
787 | .prescaler_limit = 0, | |
788 | }; | |
789 | ||
aae7147d MK |
790 | static const struct of_device_id davinci_spi_of_match[] = { |
791 | { | |
804413f2 | 792 | .compatible = "ti,dm6441-spi", |
fa466c91 | 793 | .data = &dm6441_spi_data, |
aae7147d MK |
794 | }, |
795 | { | |
804413f2 | 796 | .compatible = "ti,da830-spi", |
fa466c91 FCJ |
797 | .data = &da830_spi_data, |
798 | }, | |
799 | { | |
800 | .compatible = "ti,keystone-spi", | |
801 | .data = &keystone_spi_data, | |
aae7147d MK |
802 | }, |
803 | { }, | |
804 | }; | |
0d2d0cc5 | 805 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
aae7147d MK |
806 | |
807 | /** | |
808 | * spi_davinci_get_pdata - Get platform data from DTS binding | |
809 | * @pdev: ptr to platform data | |
810 | * @dspi: ptr to driver data | |
811 | * | |
812 | * Parses and populates pdata in dspi from device tree bindings. | |
813 | * | |
814 | * NOTE: Not all platform data params are supported currently. | |
815 | */ | |
816 | static int spi_davinci_get_pdata(struct platform_device *pdev, | |
817 | struct davinci_spi *dspi) | |
818 | { | |
819 | struct device_node *node = pdev->dev.of_node; | |
fa466c91 | 820 | struct davinci_spi_of_data *spi_data; |
aae7147d MK |
821 | struct davinci_spi_platform_data *pdata; |
822 | unsigned int num_cs, intr_line = 0; | |
823 | const struct of_device_id *match; | |
824 | ||
825 | pdata = &dspi->pdata; | |
826 | ||
b53b34f0 | 827 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
aae7147d MK |
828 | if (!match) |
829 | return -ENODEV; | |
830 | ||
fa466c91 | 831 | spi_data = (struct davinci_spi_of_data *)match->data; |
aae7147d | 832 | |
fa466c91 FCJ |
833 | pdata->version = spi_data->version; |
834 | pdata->prescaler_limit = spi_data->prescaler_limit; | |
aae7147d MK |
835 | /* |
836 | * default num_cs is 1 and all chipsel are internal to the chip | |
a88e34ea MK |
837 | * indicated by chip_sel being NULL or cs_gpios being NULL or |
838 | * set to -ENOENT. num-cs includes internal as well as gpios. | |
aae7147d MK |
839 | * indicated by chip_sel being NULL. GPIO based CS is not |
840 | * supported yet in DT bindings. | |
841 | */ | |
842 | num_cs = 1; | |
843 | of_property_read_u32(node, "num-cs", &num_cs); | |
844 | pdata->num_chipselect = num_cs; | |
845 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | |
846 | pdata->intr_line = intr_line; | |
847 | return 0; | |
848 | } | |
849 | #else | |
2b747a5f AY |
850 | static int spi_davinci_get_pdata(struct platform_device *pdev, |
851 | struct davinci_spi *dspi) | |
aae7147d MK |
852 | { |
853 | return -ENODEV; | |
854 | } | |
855 | #endif | |
856 | ||
358934a6 SP |
857 | /** |
858 | * davinci_spi_probe - probe function for SPI Master Controller | |
859 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
860 | * |
861 | * According to Linux Device Model this function will be invoked by Linux | |
862 | * with platform_device struct which contains the device specific info. | |
863 | * This function will map the SPI controller's memory, register IRQ, | |
864 | * Reset SPI controller and setting its registers to default value. | |
865 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
866 | * can register transfer method to work queue. | |
358934a6 | 867 | */ |
fd4a319b | 868 | static int davinci_spi_probe(struct platform_device *pdev) |
358934a6 SP |
869 | { |
870 | struct spi_master *master; | |
212d4b69 | 871 | struct davinci_spi *dspi; |
358934a6 | 872 | struct davinci_spi_platform_data *pdata; |
5b3bb596 | 873 | struct resource *r; |
c0600140 | 874 | int ret = 0; |
f34bd4cc | 875 | u32 spipc0; |
358934a6 | 876 | |
358934a6 SP |
877 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
878 | if (master == NULL) { | |
879 | ret = -ENOMEM; | |
880 | goto err; | |
881 | } | |
882 | ||
24b5a82c | 883 | platform_set_drvdata(pdev, master); |
358934a6 | 884 | |
212d4b69 | 885 | dspi = spi_master_get_devdata(master); |
358934a6 | 886 | |
8074cf06 JH |
887 | if (dev_get_platdata(&pdev->dev)) { |
888 | pdata = dev_get_platdata(&pdev->dev); | |
aae7147d MK |
889 | dspi->pdata = *pdata; |
890 | } else { | |
891 | /* update dspi pdata with that from the DT */ | |
892 | ret = spi_davinci_get_pdata(pdev, dspi); | |
893 | if (ret < 0) | |
894 | goto free_master; | |
895 | } | |
896 | ||
897 | /* pdata in dspi is now updated and point pdata to that */ | |
898 | pdata = &dspi->pdata; | |
899 | ||
a86854d0 KC |
900 | dspi->bytes_per_word = devm_kcalloc(&pdev->dev, |
901 | pdata->num_chipselect, | |
902 | sizeof(*dspi->bytes_per_word), | |
903 | GFP_KERNEL); | |
7480e755 MK |
904 | if (dspi->bytes_per_word == NULL) { |
905 | ret = -ENOMEM; | |
906 | goto free_master; | |
907 | } | |
908 | ||
358934a6 SP |
909 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
910 | if (r == NULL) { | |
911 | ret = -ENOENT; | |
912 | goto free_master; | |
913 | } | |
914 | ||
212d4b69 | 915 | dspi->pbase = r->start; |
358934a6 | 916 | |
5b3bb596 JH |
917 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
918 | if (IS_ERR(dspi->base)) { | |
919 | ret = PTR_ERR(dspi->base); | |
358934a6 SP |
920 | goto free_master; |
921 | } | |
922 | ||
87248dc7 MD |
923 | init_completion(&dspi->done); |
924 | ||
8494cdea AH |
925 | ret = platform_get_irq(pdev, 0); |
926 | if (ret == 0) | |
e0d205e9 | 927 | ret = -EINVAL; |
8494cdea | 928 | if (ret < 0) |
5b3bb596 | 929 | goto free_master; |
8494cdea | 930 | dspi->irq = ret; |
e0d205e9 | 931 | |
5b3bb596 JH |
932 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
933 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); | |
e0d205e9 | 934 | if (ret) |
5b3bb596 | 935 | goto free_master; |
e0d205e9 | 936 | |
94c69f76 | 937 | dspi->bitbang.master = master; |
358934a6 | 938 | |
5b3bb596 | 939 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
212d4b69 | 940 | if (IS_ERR(dspi->clk)) { |
358934a6 | 941 | ret = -ENODEV; |
5b3bb596 | 942 | goto free_master; |
358934a6 | 943 | } |
35fc3b9f AY |
944 | ret = clk_prepare_enable(dspi->clk); |
945 | if (ret) | |
946 | goto free_master; | |
358934a6 | 947 | |
101a68e7 | 948 | master->use_gpio_descriptors = true; |
aae7147d | 949 | master->dev.of_node = pdev->dev.of_node; |
358934a6 SP |
950 | master->bus_num = pdev->id; |
951 | master->num_chipselect = pdata->num_chipselect; | |
24778be2 | 952 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
6b3a631e | 953 | master->flags = SPI_MASTER_MUST_RX; |
358934a6 | 954 | master->setup = davinci_spi_setup; |
365a7bb3 | 955 | master->cleanup = davinci_spi_cleanup; |
8aedbf58 | 956 | master->can_dma = davinci_spi_can_dma; |
358934a6 | 957 | |
212d4b69 SN |
958 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
959 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
fa466c91 | 960 | dspi->prescaler_limit = pdata->prescaler_limit; |
212d4b69 | 961 | dspi->version = pdata->version; |
358934a6 | 962 | |
a3762b13 | 963 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD; |
212d4b69 SN |
964 | if (dspi->version == SPI_VERSION_2) |
965 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 966 | |
212d4b69 | 967 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
fe5fd254 PU |
968 | |
969 | ret = davinci_spi_request_dma(dspi); | |
970 | if (ret == -EPROBE_DEFER) { | |
971 | goto free_clk; | |
972 | } else if (ret) { | |
973 | dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret); | |
974 | dspi->dma_rx = NULL; | |
975 | dspi->dma_tx = NULL; | |
358934a6 SP |
976 | } |
977 | ||
212d4b69 SN |
978 | dspi->get_rx = davinci_spi_rx_buf_u8; |
979 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 980 | |
358934a6 | 981 | /* Reset In/OUT SPI module */ |
212d4b69 | 982 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 983 | udelay(100); |
212d4b69 | 984 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 985 | |
be88471b | 986 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 987 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 988 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 989 | |
e0d205e9 | 990 | if (pdata->intr_line) |
212d4b69 | 991 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 992 | else |
212d4b69 | 993 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 994 | |
212d4b69 | 995 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 996 | |
358934a6 | 997 | /* master mode default */ |
212d4b69 SN |
998 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
999 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1000 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 1001 | |
212d4b69 | 1002 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 1003 | if (ret) |
903ca25b | 1004 | goto free_dma; |
358934a6 | 1005 | |
212d4b69 | 1006 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 1007 | |
358934a6 SP |
1008 | return ret; |
1009 | ||
903ca25b | 1010 | free_dma: |
fe5fd254 PU |
1011 | if (dspi->dma_rx) { |
1012 | dma_release_channel(dspi->dma_rx); | |
1013 | dma_release_channel(dspi->dma_tx); | |
1014 | } | |
358934a6 | 1015 | free_clk: |
aae7147d | 1016 | clk_disable_unprepare(dspi->clk); |
358934a6 | 1017 | free_master: |
94c69f76 | 1018 | spi_master_put(master); |
358934a6 SP |
1019 | err: |
1020 | return ret; | |
1021 | } | |
1022 | ||
1023 | /** | |
1024 | * davinci_spi_remove - remove function for SPI Master Controller | |
1025 | * @pdev: platform_device structure which contains plateform specific data | |
1026 | * | |
1027 | * This function will do the reverse action of davinci_spi_probe function | |
1028 | * It will free the IRQ and SPI controller's memory region. | |
1029 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1030 | * created by spi_bitbang_start. | |
1031 | */ | |
fd4a319b | 1032 | static int davinci_spi_remove(struct platform_device *pdev) |
358934a6 | 1033 | { |
212d4b69 | 1034 | struct davinci_spi *dspi; |
358934a6 SP |
1035 | struct spi_master *master; |
1036 | ||
24b5a82c | 1037 | master = platform_get_drvdata(pdev); |
212d4b69 | 1038 | dspi = spi_master_get_devdata(master); |
358934a6 | 1039 | |
212d4b69 | 1040 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 1041 | |
aae7147d | 1042 | clk_disable_unprepare(dspi->clk); |
94c69f76 | 1043 | spi_master_put(master); |
358934a6 | 1044 | |
fe5fd254 PU |
1045 | if (dspi->dma_rx) { |
1046 | dma_release_channel(dspi->dma_rx); | |
1047 | dma_release_channel(dspi->dma_tx); | |
1048 | } | |
1049 | ||
358934a6 SP |
1050 | return 0; |
1051 | } | |
1052 | ||
1053 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1054 | .driver = { |
1055 | .name = "spi_davinci", | |
b53b34f0 | 1056 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
d8c174cd | 1057 | }, |
940ab889 | 1058 | .probe = davinci_spi_probe, |
fd4a319b | 1059 | .remove = davinci_spi_remove, |
358934a6 | 1060 | }; |
940ab889 | 1061 | module_platform_driver(davinci_spi_driver); |
358934a6 SP |
1062 | |
1063 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1064 | MODULE_LICENSE("GPL"); |