[linux-block.git] / drivers / spi / spi-coldfire-qspi.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Freescale/Motorola Coldfire Queued SPI driver
 *
 * Copyright 2010 Steven King <sfking@fdwdc.com>
*/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/pm_runtime.h>

#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfqspi.h>

#define	DRIVER_NAME "mcfqspi"

#define	MCFQSPI_BUSCLK			(MCF_BUSCLK / 2)

#define	MCFQSPI_QMR			0x00
#define		MCFQSPI_QMR_MSTR	0x8000
#define		MCFQSPI_QMR_CPOL	0x0200
#define		MCFQSPI_QMR_CPHA	0x0100
#define	MCFQSPI_QDLYR			0x04
#define		MCFQSPI_QDLYR_SPE	0x8000
#define	MCFQSPI_QWR			0x08
#define		MCFQSPI_QWR_HALT	0x8000
#define		MCFQSPI_QWR_WREN	0x4000
#define		MCFQSPI_QWR_CSIV	0x1000
#define	MCFQSPI_QIR			0x0C
#define		MCFQSPI_QIR_WCEFB	0x8000
#define		MCFQSPI_QIR_ABRTB	0x4000
#define		MCFQSPI_QIR_ABRTL	0x1000
#define		MCFQSPI_QIR_WCEFE	0x0800
#define		MCFQSPI_QIR_ABRTE	0x0400
#define		MCFQSPI_QIR_SPIFE	0x0100
#define		MCFQSPI_QIR_WCEF	0x0008
#define		MCFQSPI_QIR_ABRT	0x0004
#define		MCFQSPI_QIR_SPIF	0x0001
#define	MCFQSPI_QAR			0x010
#define		MCFQSPI_QAR_TXBUF	0x00
#define		MCFQSPI_QAR_RXBUF	0x10
#define		MCFQSPI_QAR_CMDBUF	0x20
#define	MCFQSPI_QDR			0x014
#define	MCFQSPI_QCR			0x014
#define		MCFQSPI_QCR_CONT	0x8000
#define		MCFQSPI_QCR_BITSE	0x4000
#define		MCFQSPI_QCR_DT		0x2000

struct mcfqspi {
	void __iomem *iobase;
	int irq;
	struct clk *clk;
	struct mcfqspi_cs_control *cs_control;

	wait_queue_head_t waitq;
};

static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QMR);
}

static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
}

static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
{
	return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
}

static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QWR);
}

static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QIR);
}

static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QAR);
}

static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QDR);
}

static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
{
	return readw(mcfqspi->iobase + MCFQSPI_QDR);
}

static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
			    bool cs_high)
{
	mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
}

static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
				bool cs_high)
{
	mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
}

static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
{
	return (mcfqspi->cs_control->setup) ?
		mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
}

static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
{
	if (mcfqspi->cs_control->teardown)
		mcfqspi->cs_control->teardown(mcfqspi->cs_control);
}

static u8 mcfqspi_qmr_baud(u32 speed_hz)
{
	return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
}

static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
{
	return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
}

static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
{
	struct mcfqspi *mcfqspi = dev_id;

	/* clear interrupt */
	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
	wake_up(&mcfqspi->waitq);

	return IRQ_HANDLED;
}

static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
				  const u8 *txbuf, u8 *rxbuf)
{
	unsigned i, n, offset = 0;

	n = min(count, 16u);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	for (i = 0; i < n; ++i)
		mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	if (txbuf)
		for (i = 0; i < n; ++i)
			mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	else
		for (i = 0; i < count; ++i)
			mcfqspi_wr_qdr(mcfqspi, 0);

	count -= n;
	if (count) {
		u16 qwr = 0xf08;
		mcfqspi_wr_qwr(mcfqspi, 0x700);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);

		do {
			wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
			mcfqspi_wr_qwr(mcfqspi, qwr);
			mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
			if (rxbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_RXBUF + offset);
				for (i = 0; i < 8; ++i)
					*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			}
			n = min(count, 8u);
			if (txbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_TXBUF + offset);
				for (i = 0; i < n; ++i)
					mcfqspi_wr_qdr(mcfqspi, *txbuf++);
			}
			qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
			offset ^= 8;
			count -= n;
		} while (count);
		wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
		mcfqspi_wr_qwr(mcfqspi, qwr);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
		if (rxbuf) {
			mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
			for (i = 0; i < 8; ++i)
				*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			offset ^= 8;
		}
	} else {
		mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	}
	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	if (rxbuf) {
		mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
		for (i = 0; i < n; ++i)
			*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	}
}

static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
				   const u16 *txbuf, u16 *rxbuf)
{
	unsigned i, n, offset = 0;

	n = min(count, 16u);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	for (i = 0; i < n; ++i)
		mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	if (txbuf)
		for (i = 0; i < n; ++i)
			mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	else
		for (i = 0; i < count; ++i)
			mcfqspi_wr_qdr(mcfqspi, 0);

	count -= n;
	if (count) {
		u16 qwr = 0xf08;
		mcfqspi_wr_qwr(mcfqspi, 0x700);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);

		do {
			wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
			mcfqspi_wr_qwr(mcfqspi, qwr);
			mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
			if (rxbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_RXBUF + offset);
				for (i = 0; i < 8; ++i)
					*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			}
			n = min(count, 8u);
			if (txbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_TXBUF + offset);
				for (i = 0; i < n; ++i)
					mcfqspi_wr_qdr(mcfqspi, *txbuf++);
			}
			qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
			offset ^= 8;
			count -= n;
		} while (count);
		wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
		mcfqspi_wr_qwr(mcfqspi, qwr);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
		if (rxbuf) {
			mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
			for (i = 0; i < 8; ++i)
				*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			offset ^= 8;
		}
	} else {
		mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	}
	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	if (rxbuf) {
		mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
		for (i = 0; i < n; ++i)
			*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	}
}

static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
	bool cs_high = spi->mode & SPI_CS_HIGH;

	if (enable)
		mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
	else
		mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
}

static int mcfqspi_transfer_one(struct spi_master *master,
				struct spi_device *spi,
				struct spi_transfer *t)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	u16 qmr = MCFQSPI_QMR_MSTR;

	qmr |= t->bits_per_word << 10;
	if (spi->mode & SPI_CPHA)
		qmr |= MCFQSPI_QMR_CPHA;
	if (spi->mode & SPI_CPOL)
		qmr |= MCFQSPI_QMR_CPOL;
	qmr |= mcfqspi_qmr_baud(t->speed_hz);
	mcfqspi_wr_qmr(mcfqspi, qmr);

	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
	if (t->bits_per_word == 8)
		mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
	else
		mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
				       t->rx_buf);
	mcfqspi_wr_qir(mcfqspi, 0);

	return 0;
}

static int mcfqspi_setup(struct spi_device *spi)
{
	mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
			    spi->chip_select, spi->mode & SPI_CS_HIGH);

	dev_dbg(&spi->dev,
			"bits per word %d, chip select %d, speed %d KHz\n",
			spi->bits_per_word, spi->chip_select,
			(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
			/ 1000);

	return 0;
}

static int mcfqspi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mcfqspi *mcfqspi;
	struct mcfqspi_platform_data *pdata;
	int status;

	pdata = dev_get_platdata(&pdev->dev);
	if (!pdata) {
		dev_dbg(&pdev->dev, "platform data is missing\n");
		return -ENOENT;
	}

	if (!pdata->cs_control) {
		dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
		return -ENOMEM;
	}

	mcfqspi = spi_master_get_devdata(master);

	mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mcfqspi->iobase)) {
		status = PTR_ERR(mcfqspi->iobase);
		goto fail0;
	}

	mcfqspi->irq = platform_get_irq(pdev, 0);
	if (mcfqspi->irq < 0) {
		dev_dbg(&pdev->dev, "platform_get_irq failed\n");
		status = -ENXIO;
		goto fail0;
	}

	status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
				0, pdev->name, mcfqspi);
	if (status) {
		dev_dbg(&pdev->dev, "request_irq failed\n");
		goto fail0;
	}

	mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
	if (IS_ERR(mcfqspi->clk)) {
		dev_dbg(&pdev->dev, "clk_get failed\n");
		status = PTR_ERR(mcfqspi->clk);
		goto fail0;
	}
	clk_prepare_enable(mcfqspi->clk);

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;

	mcfqspi->cs_control = pdata->cs_control;
	status = mcfqspi_cs_setup(mcfqspi);
	if (status) {
		dev_dbg(&pdev->dev, "error initializing cs_control\n");
		goto fail1;
	}

	init_waitqueue_head(&mcfqspi->waitq);

	master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
	master->setup = mcfqspi_setup;
	master->set_cs = mcfqspi_set_cs;
	master->transfer_one = mcfqspi_transfer_one;
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);
	pm_runtime_enable(&pdev->dev);

	status = devm_spi_register_master(&pdev->dev, master);
	if (status) {
		dev_dbg(&pdev->dev, "spi_register_master failed\n");
		goto fail2;
	}

	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");

	return 0;

fail2:
	pm_runtime_disable(&pdev->dev);
	mcfqspi_cs_teardown(mcfqspi);
fail1:
	clk_disable_unprepare(mcfqspi->clk);
fail0:
	spi_master_put(master);

	dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");

	return status;
}

static int mcfqspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	pm_runtime_disable(&pdev->dev);
	/* disable the hardware (set the baud rate to 0) */
	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);

	mcfqspi_cs_teardown(mcfqspi);
	clk_disable_unprepare(mcfqspi->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mcfqspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	int ret;

	ret = spi_master_suspend(master);
	if (ret)
		return ret;

	clk_disable(mcfqspi->clk);

	return 0;
}

static int mcfqspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	clk_enable(mcfqspi->clk);

	return spi_master_resume(master);
}
#endif

#ifdef CONFIG_PM
static int mcfqspi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	clk_disable(mcfqspi->clk);

	return 0;
}

static int mcfqspi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	clk_enable(mcfqspi->clk);

	return 0;
}
#endif

static const struct dev_pm_ops mcfqspi_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
			NULL)
};

static struct platform_driver mcfqspi_driver = {
	.driver.name	= DRIVER_NAME,
	.driver.owner	= THIS_MODULE,
	.driver.pm	= &mcfqspi_pm,
	.probe		= mcfqspi_probe,
	.remove		= mcfqspi_remove,
};
module_platform_driver(mcfqspi_driver);

MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
34b8c661 SK	2	/*
	3	* Freescale/Motorola Coldfire Queued SPI driver
	4	*
	5	* Copyright 2010 Steven King <sfking@fdwdc.com>
34b8c661 SK	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/module.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/errno.h>
	12	#include <linux/platform_device.h>
5e1c5335	13	#include <linux/sched.h>
34b8c661 SK	14	#include <linux/delay.h>
	15	#include <linux/io.h>
	16	#include <linux/clk.h>
	17	#include <linux/err.h>
	18	#include <linux/spi/spi.h>
bc98d13f	19	#include <linux/pm_runtime.h>
34b8c661 SK	20
34b8c661 SK	21	#include <asm/coldfire.h>
0b4bf782	22	#include <asm/mcfsim.h>
34b8c661 SK	23	#include <asm/mcfqspi.h>
	24
	25	#define DRIVER_NAME "mcfqspi"
	26
	27	#define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
	28
	29	#define MCFQSPI_QMR 0x00
	30	#define MCFQSPI_QMR_MSTR 0x8000
	31	#define MCFQSPI_QMR_CPOL 0x0200
	32	#define MCFQSPI_QMR_CPHA 0x0100
	33	#define MCFQSPI_QDLYR 0x04
	34	#define MCFQSPI_QDLYR_SPE 0x8000
	35	#define MCFQSPI_QWR 0x08
	36	#define MCFQSPI_QWR_HALT 0x8000
	37	#define MCFQSPI_QWR_WREN 0x4000
	38	#define MCFQSPI_QWR_CSIV 0x1000
	39	#define MCFQSPI_QIR 0x0C
	40	#define MCFQSPI_QIR_WCEFB 0x8000
	41	#define MCFQSPI_QIR_ABRTB 0x4000
	42	#define MCFQSPI_QIR_ABRTL 0x1000
	43	#define MCFQSPI_QIR_WCEFE 0x0800
	44	#define MCFQSPI_QIR_ABRTE 0x0400
	45	#define MCFQSPI_QIR_SPIFE 0x0100
	46	#define MCFQSPI_QIR_WCEF 0x0008
	47	#define MCFQSPI_QIR_ABRT 0x0004
	48	#define MCFQSPI_QIR_SPIF 0x0001
	49	#define MCFQSPI_QAR 0x010
	50	#define MCFQSPI_QAR_TXBUF 0x00
	51	#define MCFQSPI_QAR_RXBUF 0x10
	52	#define MCFQSPI_QAR_CMDBUF 0x20
	53	#define MCFQSPI_QDR 0x014
	54	#define MCFQSPI_QCR 0x014
	55	#define MCFQSPI_QCR_CONT 0x8000
	56	#define MCFQSPI_QCR_BITSE 0x4000
	57	#define MCFQSPI_QCR_DT 0x2000
	58
	59	struct mcfqspi {
	60	void __iomem *iobase;
	61	int irq;
	62	struct clk *clk;
	63	struct mcfqspi_cs_control *cs_control;
	64
	65	wait_queue_head_t waitq;
34b8c661 SK	66	};
	67
	68	static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
	69	{
	70	writew(val, mcfqspi->iobase + MCFQSPI_QMR);
	71	}
	72
	73	static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
	74	{
	75	writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
	76	}
	77
	78	static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
	79	{
	80	return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
	81	}
	82
	83	static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
	84	{
	85	writew(val, mcfqspi->iobase + MCFQSPI_QWR);
	86	}
	87
	88	static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
	89	{
	90	writew(val, mcfqspi->iobase + MCFQSPI_QIR);
	91	}
	92
	93	static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
	94	{
	95	writew(val, mcfqspi->iobase + MCFQSPI_QAR);
	96	}
	97
	98	static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
	99	{
	100	writew(val, mcfqspi->iobase + MCFQSPI_QDR);
	101	}
	102
	103	static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
	104	{
	105	return readw(mcfqspi->iobase + MCFQSPI_QDR);
	106	}
	107
	108	static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
	109	bool cs_high)
	110	{
	111	mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
	112	}
	113
	114	static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
	115	bool cs_high)
	116	{
	117	mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
	118	}
	119
	120	static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
	121	{
2271cf12	122	return (mcfqspi->cs_control->setup) ?
34b8c661 SK	123	mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
	124	}
	125
	126	static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
	127	{
2271cf12	128	if (mcfqspi->cs_control->teardown)
34b8c661 SK	129	mcfqspi->cs_control->teardown(mcfqspi->cs_control);
	130	}
	131
	132	static u8 mcfqspi_qmr_baud(u32 speed_hz)
	133	{
	134	return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
	135	}
	136
	137	static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
	138	{
	139	return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
	140	}
	141
	142	static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
	143	{
	144	struct mcfqspi *mcfqspi = dev_id;
	145
	146	/* clear interrupt */
	147	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE \| MCFQSPI_QIR_SPIF);
	148	wake_up(&mcfqspi->waitq);
	149
	150	return IRQ_HANDLED;
	151	}
	152
	153	static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
	154	const u8 txbuf, u8 rxbuf)
	155	{
	156	unsigned i, n, offset = 0;
	157
	158	n = min(count, 16u);
	159
	160	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	161	for (i = 0; i < n; ++i)
	162	mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
	163
	164	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	165	if (txbuf)
	166	for (i = 0; i < n; ++i)
	167	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	168	else
	169	for (i = 0; i < count; ++i)
	170	mcfqspi_wr_qdr(mcfqspi, 0);
	171
	172	count -= n;
	173	if (count) {
	174	u16 qwr = 0xf08;
	175	mcfqspi_wr_qwr(mcfqspi, 0x700);
	176	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	177
	178	do {
	179	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	180	mcfqspi_wr_qwr(mcfqspi, qwr);
	181	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	182	if (rxbuf) {
	183	mcfqspi_wr_qar(mcfqspi,
	184	MCFQSPI_QAR_RXBUF + offset);
	185	for (i = 0; i < 8; ++i)
	186	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	187	}
	188	n = min(count, 8u);
	189	if (txbuf) {
	190	mcfqspi_wr_qar(mcfqspi,
	191	MCFQSPI_QAR_TXBUF + offset);
	192	for (i = 0; i < n; ++i)
193	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
194	}
195	qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
196	offset ^= 8;
197	count -= n;
198	} while (count);
199	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
200	mcfqspi_wr_qwr(mcfqspi, qwr);
201	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
202	if (rxbuf) {
203	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
204	for (i = 0; i < 8; ++i)
205	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
206	offset ^= 8;
207	}
208	} else {
209	mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
210	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
211	}
212	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
213	if (rxbuf) {
214	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
215	for (i = 0; i < n; ++i)
216	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
217	}
218	}
219
220	static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
221	const u16 txbuf, u16 rxbuf)
222	{
223	unsigned i, n, offset = 0;
224
225	n = min(count, 16u);
226
227	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
228	for (i = 0; i < n; ++i)
229	mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
230
231	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
232	if (txbuf)
233	for (i = 0; i < n; ++i)
234	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
235	else
236	for (i = 0; i < count; ++i)
237	mcfqspi_wr_qdr(mcfqspi, 0);
238
239	count -= n;
240	if (count) {
241	u16 qwr = 0xf08;
242	mcfqspi_wr_qwr(mcfqspi, 0x700);
243	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
244
245	do {
246	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
247	mcfqspi_wr_qwr(mcfqspi, qwr);
248	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
249	if (rxbuf) {
250	mcfqspi_wr_qar(mcfqspi,
251	MCFQSPI_QAR_RXBUF + offset);
252	for (i = 0; i < 8; ++i)
253	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
254	}
255	n = min(count, 8u);
256	if (txbuf) {
257	mcfqspi_wr_qar(mcfqspi,
258	MCFQSPI_QAR_TXBUF + offset);
259	for (i = 0; i < n; ++i)
260	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
261	}
262	qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
263	offset ^= 8;
264	count -= n;
265	} while (count);
266	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
267	mcfqspi_wr_qwr(mcfqspi, qwr);
268	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
269	if (rxbuf) {
270	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
271	for (i = 0; i < 8; ++i)
272	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
273	offset ^= 8;
274	}
275	} else {
276	mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
277	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
278	}
279	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
280	if (rxbuf) {
281	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
282	for (i = 0; i < n; ++i)
283	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
284	}
285	}
286
3531b717	287	static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
34b8c661	288	{
3531b717 AL	289	struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
3531b717 AL	290	bool cs_high = spi->mode & SPI_CS_HIGH;
bc98d13f	291
3531b717	292	if (enable)
bc98d13f	293	mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
3531b717 AL	294	else
	295	mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
	296	}
bc98d13f	297
3531b717 AL	298	static int mcfqspi_transfer_one(struct spi_master *master,
	299	struct spi_device *spi,
	300	struct spi_transfer *t)
	301	{
	302	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	303	u16 qmr = MCFQSPI_QMR_MSTR;
	304
	305	qmr \|= t->bits_per_word << 10;
	306	if (spi->mode & SPI_CPHA)
	307	qmr \|= MCFQSPI_QMR_CPHA;
	308	if (spi->mode & SPI_CPOL)
	309	qmr \|= MCFQSPI_QMR_CPOL;
8023d384	310	qmr \|= mcfqspi_qmr_baud(t->speed_hz);
3531b717	311	mcfqspi_wr_qmr(mcfqspi, qmr);
bc98d13f	312
3531b717 AL	313	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
	314	if (t->bits_per_word == 8)
	315	mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
	316	else
	317	mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
	318	t->rx_buf);
	319	mcfqspi_wr_qir(mcfqspi, 0);
bc98d13f	320
3531b717	321	return 0;
34b8c661 SK	322	}
34b8c661 SK	323
34b8c661 SK	324	static int mcfqspi_setup(struct spi_device *spi)
34b8c661 SK	325	{
34b8c661 SK	326	mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
	327	spi->chip_select, spi->mode & SPI_CS_HIGH);
	328
	329	dev_dbg(&spi->dev,
	330	"bits per word %d, chip select %d, speed %d KHz\n",
	331	spi->bits_per_word, spi->chip_select,
	332	(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
	333	/ 1000);
	334
	335	return 0;
	336	}
	337
fd4a319b	338	static int mcfqspi_probe(struct platform_device *pdev)
34b8c661 SK	339	{
	340	struct spi_master *master;
	341	struct mcfqspi *mcfqspi;
34b8c661 SK	342	struct mcfqspi_platform_data *pdata;
	343	int status;
	344
8074cf06	345	pdata = dev_get_platdata(&pdev->dev);
4a577f52 WY	346	if (!pdata) {
	347	dev_dbg(&pdev->dev, "platform data is missing\n");
	348	return -ENOENT;
	349	}
	350
2271cf12 AL	351	if (!pdata->cs_control) {
	352	dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
	353	return -EINVAL;
	354	}
	355
34b8c661 SK	356	master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
	357	if (master == NULL) {
	358	dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
	359	return -ENOMEM;
	360	}
	361
	362	mcfqspi = spi_master_get_devdata(master);
	363
1e2d65d0	364	mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
9a3ced19 JH	365	if (IS_ERR(mcfqspi->iobase)) {
9a3ced19 JH	366	status = PTR_ERR(mcfqspi->iobase);
34b8c661 SK	367	goto fail0;
	368	}
	369
34b8c661 SK	370	mcfqspi->irq = platform_get_irq(pdev, 0);
	371	if (mcfqspi->irq < 0) {
	372	dev_dbg(&pdev->dev, "platform_get_irq failed\n");
	373	status = -ENXIO;
9a3ced19	374	goto fail0;
34b8c661 SK	375	}
34b8c661 SK	376
9a3ced19 JH	377	status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
9a3ced19 JH	378	0, pdev->name, mcfqspi);
34b8c661 SK	379	if (status) {
34b8c661 SK	380	dev_dbg(&pdev->dev, "request_irq failed\n");
9a3ced19	381	goto fail0;
34b8c661 SK	382	}
34b8c661 SK	383
9a3ced19	384	mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
34b8c661 SK	385	if (IS_ERR(mcfqspi->clk)) {
	386	dev_dbg(&pdev->dev, "clk_get failed\n");
	387	status = PTR_ERR(mcfqspi->clk);
9a3ced19	388	goto fail0;
34b8c661	389	}
499de01c	390	clk_prepare_enable(mcfqspi->clk);
34b8c661	391
34b8c661 SK	392	master->bus_num = pdata->bus_num;
	393	master->num_chipselect = pdata->num_chipselect;
	394
	395	mcfqspi->cs_control = pdata->cs_control;
	396	status = mcfqspi_cs_setup(mcfqspi);
	397	if (status) {
	398	dev_dbg(&pdev->dev, "error initializing cs_control\n");
9a3ced19	399	goto fail1;
34b8c661 SK	400	}
34b8c661 SK	401
bc98d13f	402	init_waitqueue_head(&mcfqspi->waitq);
bc98d13f	403
34b8c661	404	master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
24778be2	405	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
34b8c661	406	master->setup = mcfqspi_setup;
3531b717 AL	407	master->set_cs = mcfqspi_set_cs;
3531b717 AL	408	master->transfer_one = mcfqspi_transfer_one;
3f36e80a	409	master->auto_runtime_pm = true;
34b8c661 SK	410
34b8c661 SK	411	platform_set_drvdata(pdev, master);
f9b841af	412	pm_runtime_enable(&pdev->dev);
34b8c661	413
9a3ced19	414	status = devm_spi_register_master(&pdev->dev, master);
34b8c661 SK	415	if (status) {
34b8c661 SK	416	dev_dbg(&pdev->dev, "spi_register_master failed\n");
9a3ced19	417	goto fail2;
34b8c661	418	}
bc98d13f	419
34b8c661 SK	420	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
	421
	422	return 0;
	423
34b8c661	424	fail2:
f9b841af	425	pm_runtime_disable(&pdev->dev);
9a3ced19	426	mcfqspi_cs_teardown(mcfqspi);
34b8c661	427	fail1:
499de01c	428	clk_disable_unprepare(mcfqspi->clk);
34b8c661 SK	429	fail0:
	430	spi_master_put(master);
	431
	432	dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
	433
	434	return status;
	435	}
	436
fd4a319b	437	static int mcfqspi_remove(struct platform_device *pdev)
34b8c661 SK	438	{
	439	struct spi_master *master = platform_get_drvdata(pdev);
	440	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
34b8c661	441
8bd31345	442	pm_runtime_disable(&pdev->dev);
34b8c661 SK	443	/* disable the hardware (set the baud rate to 0) */
	444	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
	445
34b8c661	446	mcfqspi_cs_teardown(mcfqspi);
d68f4c73	447	clk_disable_unprepare(mcfqspi->clk);
34b8c661 SK	448
	449	return 0;
	450	}
	451
bc98d13f	452	#ifdef CONFIG_PM_SLEEP
34b8c661 SK	453	static int mcfqspi_suspend(struct device *dev)
34b8c661 SK	454	{
af361079	455	struct spi_master *master = dev_get_drvdata(dev);
bc98d13f	456	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
2aa237f4	457	int ret;
bc98d13f	458
2aa237f4 AL	459	ret = spi_master_suspend(master);
	460	if (ret)
	461	return ret;
34b8c661 SK	462
	463	clk_disable(mcfqspi->clk);
	464
	465	return 0;
	466	}
	467
	468	static int mcfqspi_resume(struct device *dev)
	469	{
af361079	470	struct spi_master *master = dev_get_drvdata(dev);
bc98d13f SK	471	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
bc98d13f SK	472
34b8c661 SK	473	clk_enable(mcfqspi->clk);
34b8c661 SK	474
2aa237f4	475	return spi_master_resume(master);
34b8c661	476	}
bc98d13f	477	#endif
34b8c661	478
ec833050	479	#ifdef CONFIG_PM
bc98d13f SK	480	static int mcfqspi_runtime_suspend(struct device *dev)
bc98d13f SK	481	{
ee73b4c6 AL	482	struct spi_master *master = dev_get_drvdata(dev);
ee73b4c6 AL	483	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
34b8c661	484
bc98d13f SK	485	clk_disable(mcfqspi->clk);
	486
	487	return 0;
	488	}
	489
	490	static int mcfqspi_runtime_resume(struct device *dev)
	491	{
ee73b4c6 AL	492	struct spi_master *master = dev_get_drvdata(dev);
ee73b4c6 AL	493	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
bc98d13f SK	494
	495	clk_enable(mcfqspi->clk);
	496
	497	return 0;
	498	}
34b8c661 SK	499	#endif
34b8c661 SK	500
bc98d13f SK	501	static const struct dev_pm_ops mcfqspi_pm = {
	502	SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	503	SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
	504	NULL)
	505	};
	506
34b8c661 SK	507	static struct platform_driver mcfqspi_driver = {
	508	.driver.name = DRIVER_NAME,
	509	.driver.owner = THIS_MODULE,
bc98d13f	510	.driver.pm = &mcfqspi_pm,
940ab889	511	.probe = mcfqspi_probe,
fd4a319b	512	.remove = mcfqspi_remove,
34b8c661	513	};
940ab889	514	module_platform_driver(mcfqspi_driver);
34b8c661 SK	515
	516	MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
	517	MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
	518	MODULE_LICENSE("GPL");
	519	MODULE_ALIAS("platform:" DRIVER_NAME);