[linux-2.6-block.git] / drivers / spi / spi-clps711x.c

/*
 *  CLPS711X SPI bus driver
 *
 *  Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/io.h>
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/spi-clps711x.h>

#include <mach/hardware.h>

#define DRIVER_NAME	"spi-clps711x"

struct spi_clps711x_data {
	struct clk		*spi_clk;
	u32			max_speed_hz;

	u8			*tx_buf;
	u8			*rx_buf;
	unsigned int		bpw;
	int			len;
};

static int spi_clps711x_setup(struct spi_device *spi)
{
	/* We are expect that SPI-device is not selected */
	gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));

	return 0;
}

static void spi_clps711x_setup_xfer(struct spi_device *spi,
				    struct spi_transfer *xfer)
{
	u32 speed = xfer->speed_hz ? : spi->max_speed_hz;
	struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);

	/* Setup SPI frequency divider */
	if (!speed || (speed >= hw->max_speed_hz))
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(3), SYSCON1);
	else if (speed >= (hw->max_speed_hz / 2))
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(2), SYSCON1);
	else if (speed >= (hw->max_speed_hz / 8))
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(1), SYSCON1);
	else
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(0), SYSCON1);
}

static int spi_clps711x_prepare_message(struct spi_master *master,
					struct spi_message *msg)
{
	struct spi_device *spi = msg->spi;

	/* Setup edge for transfer */
	if (spi->mode & SPI_CPHA)
		clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3);
	else
		clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);

	return 0;
}

static int spi_clps711x_transfer_one(struct spi_master *master,
				     struct spi_device *spi,
				     struct spi_transfer *xfer)
{
	struct spi_clps711x_data *hw = spi_master_get_devdata(master);
	u8 data;

	spi_clps711x_setup_xfer(spi, xfer);

	hw->len = xfer->len;
	hw->bpw = xfer->bits_per_word ? : spi->bits_per_word;
	hw->tx_buf = (u8 *)xfer->tx_buf;
	hw->rx_buf = (u8 *)xfer->rx_buf;

	/* Initiate transfer */
	data = hw->tx_buf ? *hw->tx_buf++ : 0;
	clps_writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, SYNCIO);
	return 1;
}

static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct spi_clps711x_data *hw = spi_master_get_devdata(master);
	u8 data;

	/* Handle RX */
	data = clps_readb(SYNCIO);
	if (hw->rx_buf)
		*hw->rx_buf++ = data;

	/* Handle TX */
	if (--hw->len > 0) {
		data = hw->tx_buf ? *hw->tx_buf++ : 0;
		clps_writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
			    SYNCIO);
	} else
		spi_finalize_current_transfer(master);

	return IRQ_HANDLED;
}

static int spi_clps711x_probe(struct platform_device *pdev)
{
	int i, ret;
	struct spi_master *master;
	struct spi_clps711x_data *hw;
	struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);

	if (!pdata) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		return -EINVAL;
	}

	if (pdata->num_chipselect < 1) {
		dev_err(&pdev->dev, "At least one CS must be defined\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*hw));
	if (!master)
		return -ENOMEM;

	master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
					pdata->num_chipselect, GFP_KERNEL);
	if (!master->cs_gpios) {
		ret = -ENOMEM;
		goto err_out;
	}

	master->bus_num = pdev->id;
	master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
	master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(1, 8);
	master->num_chipselect = pdata->num_chipselect;
	master->setup = spi_clps711x_setup;
	master->prepare_message = spi_clps711x_prepare_message;
	master->transfer_one = spi_clps711x_transfer_one;

	hw = spi_master_get_devdata(master);

	for (i = 0; i < master->num_chipselect; i++) {
		master->cs_gpios[i] = pdata->chipselect[i];
		ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
					DRIVER_NAME);
		if (ret) {
			dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
			goto err_out;
		}
	}

	hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
	if (IS_ERR(hw->spi_clk)) {
		dev_err(&pdev->dev, "Can't get clocks\n");
		ret = PTR_ERR(hw->spi_clk);
		goto err_out;
	}
	hw->max_speed_hz = clk_get_rate(hw->spi_clk);

	platform_set_drvdata(pdev, master);

	/* Disable extended mode due hardware problems */
	clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3);

	/* Clear possible pending interrupt */
	clps_readl(SYNCIO);

	ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0,
			       dev_name(&pdev->dev), master);
	if (ret) {
		dev_err(&pdev->dev, "Can't request IRQ\n");
		goto err_out;
	}

	ret = devm_spi_register_master(&pdev->dev, master);
	if (!ret) {
		dev_info(&pdev->dev,
			 "SPI bus driver initialized. Master clock %u Hz\n",
			 hw->max_speed_hz);
		return 0;
	}

	dev_err(&pdev->dev, "Failed to register master\n");

err_out:
	spi_master_put(master);

	return ret;
}

static struct platform_driver clps711x_spi_driver = {
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
	},
	.probe	= spi_clps711x_probe,
};
module_platform_driver(clps711x_spi_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("CLPS711X SPI bus driver");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
161b96c3 AS	1	/*
	2	* CLPS711X SPI bus driver
	3	*
98984796	4	* Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
161b96c3 AS	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/clk.h>
	14	#include <linux/init.h>
	15	#include <linux/gpio.h>
	16	#include <linux/delay.h>
	17	#include <linux/module.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/spi/spi.h>
	21	#include <linux/platform_data/spi-clps711x.h>
	22
	23	#include <mach/hardware.h>
	24
	25	#define DRIVER_NAME "spi-clps711x"
	26
	27	struct spi_clps711x_data {
161b96c3 AS	28	struct clk *spi_clk;
	29	u32 max_speed_hz;
	30
	31	u8 *tx_buf;
	32	u8 *rx_buf;
8dda9d9a	33	unsigned int bpw;
161b96c3	34	int len;
161b96c3 AS	35	};
	36
	37	static int spi_clps711x_setup(struct spi_device *spi)
	38	{
161b96c3	39	/* We are expect that SPI-device is not selected */
3e9ea4b4	40	gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
161b96c3 AS	41
	42	return 0;
	43	}
	44
8dda9d9a AS	45	static void spi_clps711x_setup_xfer(struct spi_device *spi,
8dda9d9a AS	46	struct spi_transfer *xfer)
161b96c3 AS	47	{
161b96c3 AS	48	u32 speed = xfer->speed_hz ? : spi->max_speed_hz;
161b96c3 AS	49	struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
161b96c3 AS	50
161b96c3 AS	51	/* Setup SPI frequency divider */
	52	if (!speed \|\| (speed >= hw->max_speed_hz))
	53	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	54	SYSCON1_ADCKSEL(3), SYSCON1);
	55	else if (speed >= (hw->max_speed_hz / 2))
	56	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	57	SYSCON1_ADCKSEL(2), SYSCON1);
	58	else if (speed >= (hw->max_speed_hz / 8))
	59	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	60	SYSCON1_ADCKSEL(1), SYSCON1);
	61	else
	62	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	63	SYSCON1_ADCKSEL(0), SYSCON1);
161b96c3 AS	64	}
161b96c3 AS	65
bf5c2e27 AL	66	static int spi_clps711x_prepare_message(struct spi_master *master,
bf5c2e27 AL	67	struct spi_message *msg)
161b96c3	68	{
8dda9d9a	69	struct spi_device *spi = msg->spi;
161b96c3	70
bf5c2e27 AL	71	/* Setup edge for transfer */
	72	if (spi->mode & SPI_CPHA)
	73	clps_writew(clps_readw(SYSCON3) \| SYSCON3_ADCCKNSEN, SYSCON3);
	74	else
	75	clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
161b96c3	76
bf5c2e27 AL	77	return 0;
bf5c2e27 AL	78	}
161b96c3	79
bf5c2e27 AL	80	static int spi_clps711x_transfer_one(struct spi_master *master,
	81	struct spi_device *spi,
	82	struct spi_transfer *xfer)
	83	{
	84	struct spi_clps711x_data *hw = spi_master_get_devdata(master);
	85	u8 data;
161b96c3	86
bf5c2e27	87	spi_clps711x_setup_xfer(spi, xfer);
161b96c3	88
bf5c2e27 AL	89	hw->len = xfer->len;
	90	hw->bpw = xfer->bits_per_word ? : spi->bits_per_word;
	91	hw->tx_buf = (u8 *)xfer->tx_buf;
	92	hw->rx_buf = (u8 *)xfer->rx_buf;
161b96c3	93
bf5c2e27 AL	94	/* Initiate transfer */
	95	data = hw->tx_buf ? *hw->tx_buf++ : 0;
	96	clps_writel(data \| SYNCIO_FRMLEN(hw->bpw) \| SYNCIO_TXFRMEN, SYNCIO);
	97	return 1;
161b96c3 AS	98	}
	99
	100	static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
	101	{
bf5c2e27 AL	102	struct spi_master *master = dev_id;
bf5c2e27 AL	103	struct spi_clps711x_data *hw = spi_master_get_devdata(master);
c7a26f12	104	u8 data;
161b96c3 AS	105
	106	/* Handle RX */
	107	data = clps_readb(SYNCIO);
	108	if (hw->rx_buf)
c7a26f12	109	*hw->rx_buf++ = data;
161b96c3 AS	110
161b96c3 AS	111	/* Handle TX */
c7a26f12 AS	112	if (--hw->len > 0) {
c7a26f12 AS	113	data = hw->tx_buf ? *hw->tx_buf++ : 0;
8dda9d9a AS	114	clps_writel(data \| SYNCIO_FRMLEN(hw->bpw) \| SYNCIO_TXFRMEN,
8dda9d9a AS	115	SYNCIO);
161b96c3	116	} else
bf5c2e27	117	spi_finalize_current_transfer(master);
161b96c3 AS	118
	119	return IRQ_HANDLED;
	120	}
	121
fd4a319b	122	static int spi_clps711x_probe(struct platform_device *pdev)
161b96c3 AS	123	{
	124	int i, ret;
	125	struct spi_master *master;
	126	struct spi_clps711x_data *hw;
	127	struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
	128
	129	if (!pdata) {
	130	dev_err(&pdev->dev, "No platform data supplied\n");
	131	return -EINVAL;
	132	}
	133
	134	if (pdata->num_chipselect < 1) {
	135	dev_err(&pdev->dev, "At least one CS must be defined\n");
	136	return -EINVAL;
	137	}
	138
3e9ea4b4 AS	139	master = spi_alloc_master(&pdev->dev, sizeof(*hw));
3e9ea4b4 AS	140	if (!master)
161b96c3	141	return -ENOMEM;
3e9ea4b4 AS	142
	143	master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
	144	pdata->num_chipselect, GFP_KERNEL);
	145	if (!master->cs_gpios) {
	146	ret = -ENOMEM;
	147	goto err_out;
161b96c3 AS	148	}
	149
	150	master->bus_num = pdev->id;
	151	master->mode_bits = SPI_CPHA \| SPI_CS_HIGH;
8dda9d9a	152	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
161b96c3 AS	153	master->num_chipselect = pdata->num_chipselect;
161b96c3 AS	154	master->setup = spi_clps711x_setup;
bf5c2e27 AL	155	master->prepare_message = spi_clps711x_prepare_message;
bf5c2e27 AL	156	master->transfer_one = spi_clps711x_transfer_one;
161b96c3 AS	157
	158	hw = spi_master_get_devdata(master);
	159
	160	for (i = 0; i < master->num_chipselect; i++) {
3e9ea4b4	161	master->cs_gpios[i] = pdata->chipselect[i];
fcba212d AL	162	ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
	163	DRIVER_NAME);
	164	if (ret) {
161b96c3	165	dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
161b96c3 AS	166	goto err_out;
	167	}
	168	}
	169
	170	hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
	171	if (IS_ERR(hw->spi_clk)) {
	172	dev_err(&pdev->dev, "Can't get clocks\n");
	173	ret = PTR_ERR(hw->spi_clk);
	174	goto err_out;
	175	}
	176	hw->max_speed_hz = clk_get_rate(hw->spi_clk);
	177
161b96c3 AS	178	platform_set_drvdata(pdev, master);
	179
	180	/* Disable extended mode due hardware problems */
	181	clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3);
	182
	183	/* Clear possible pending interrupt */
	184	clps_readl(SYNCIO);
	185
	186	ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0,
bf5c2e27	187	dev_name(&pdev->dev), master);
161b96c3 AS	188	if (ret) {
161b96c3 AS	189	dev_err(&pdev->dev, "Can't request IRQ\n");
c7083790	190	goto err_out;
161b96c3 AS	191	}
161b96c3 AS	192
c493fc4b	193	ret = devm_spi_register_master(&pdev->dev, master);
161b96c3 AS	194	if (!ret) {
	195	dev_info(&pdev->dev,
	196	"SPI bus driver initialized. Master clock %u Hz\n",
	197	hw->max_speed_hz);
	198	return 0;
	199	}
	200
	201	dev_err(&pdev->dev, "Failed to register master\n");
161b96c3	202
161b96c3	203	err_out:
161b96c3	204	spi_master_put(master);
161b96c3 AS	205
	206	return ret;
	207	}
	208
161b96c3 AS	209	static struct platform_driver clps711x_spi_driver = {
	210	.driver = {
	211	.name = DRIVER_NAME,
	212	.owner = THIS_MODULE,
	213	},
	214	.probe = spi_clps711x_probe,
161b96c3 AS	215	};
	216	module_platform_driver(clps711x_spi_driver);
	217
	218	MODULE_LICENSE("GPL");
	219	MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
	220	MODULE_DESCRIPTION("CLPS711X SPI bus driver");
350a9b33	221	MODULE_ALIAS("platform:" DRIVER_NAME);