Commit | Line | Data |
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59899843 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c474b386 | 2 | /* |
f75c04a9 | 3 | * Cadence SPI controller driver (host and target mode) |
c474b386 HK |
4 | * |
5 | * Copyright (C) 2008 - 2014 Xilinx, Inc. | |
6 | * | |
7 | * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) | |
c474b386 HK |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
cfeefa79 | 12 | #include <linux/gpio/consumer.h> |
c474b386 HK |
13 | #include <linux/interrupt.h> |
14 | #include <linux/io.h> | |
6afe2ae8 | 15 | #include <linux/kernel.h> |
c474b386 HK |
16 | #include <linux/module.h> |
17 | #include <linux/of_irq.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/platform_device.h> | |
d36ccd9f | 20 | #include <linux/pm_runtime.h> |
c474b386 HK |
21 | #include <linux/spi/spi.h> |
22 | ||
23 | /* Name of this driver */ | |
24 | #define CDNS_SPI_NAME "cdns-spi" | |
25 | ||
26 | /* Register offset definitions */ | |
24746675 SD |
27 | #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */ |
28 | #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */ | |
29 | #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */ | |
30 | #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */ | |
31 | #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */ | |
32 | #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */ | |
33 | #define CDNS_SPI_DR 0x18 /* Delay Register, RW */ | |
34 | #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */ | |
35 | #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */ | |
36 | #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */ | |
37 | #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */ | |
c474b386 | 38 | |
d36ccd9f | 39 | #define SPI_AUTOSUSPEND_TIMEOUT 3000 |
c474b386 HK |
40 | /* |
41 | * SPI Configuration Register bit Masks | |
42 | * | |
43 | * This register contains various control bits that affect the operation | |
44 | * of the SPI controller | |
45 | */ | |
24746675 SD |
46 | #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */ |
47 | #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */ | |
48 | #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */ | |
49 | #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */ | |
50 | #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */ | |
51 | #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */ | |
52 | #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */ | |
53 | #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */ | |
54 | #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */ | |
55 | #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */ | |
56 | #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \ | |
57 | CDNS_SPI_CR_SSCTRL | \ | |
58 | CDNS_SPI_CR_SSFORCE | \ | |
59 | CDNS_SPI_CR_BAUD_DIV_4) | |
c474b386 HK |
60 | |
61 | /* | |
f75c04a9 | 62 | * SPI Configuration Register - Baud rate and target select |
c474b386 HK |
63 | * |
64 | * These are the values used in the calculation of baud rate divisor and | |
f75c04a9 | 65 | * setting the target select. |
c474b386 HK |
66 | */ |
67 | ||
68 | #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ | |
69 | #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ | |
70 | #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ | |
71 | #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ | |
72 | #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ | |
e1502ba4 | 73 | #define CDNS_SPI_NOSS 0xF /* No Slave select */ |
c474b386 HK |
74 | |
75 | /* | |
76 | * SPI Interrupt Registers bit Masks | |
77 | * | |
78 | * All the four interrupt registers (Status/Mask/Enable/Disable) have the same | |
79 | * bit definitions. | |
80 | */ | |
24746675 SD |
81 | #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */ |
82 | #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */ | |
83 | #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */ | |
84 | #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \ | |
85 | CDNS_SPI_IXR_MODF) | |
86 | #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */ | |
87 | #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */ | |
c474b386 HK |
88 | |
89 | /* | |
90 | * SPI Enable Register bit Masks | |
91 | * | |
92 | * This register is used to enable or disable the SPI controller | |
93 | */ | |
24746675 SD |
94 | #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */ |
95 | #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */ | |
c474b386 | 96 | |
c474b386 HK |
97 | /* Default number of chip select lines */ |
98 | #define CDNS_SPI_DEFAULT_NUM_CS 4 | |
99 | ||
100 | /** | |
101 | * struct cdns_spi - This definition defines spi driver instance | |
102 | * @regs: Virtual address of the SPI controller registers | |
103 | * @ref_clk: Pointer to the peripheral clock | |
104 | * @pclk: Pointer to the APB clock | |
b6e4686c | 105 | * @clk_rate: Reference clock frequency, taken from @ref_clk |
c474b386 HK |
106 | * @speed_hz: Current SPI bus clock speed in Hz |
107 | * @txbuf: Pointer to the TX buffer | |
108 | * @rxbuf: Pointer to the RX buffer | |
109 | * @tx_bytes: Number of bytes left to transfer | |
110 | * @rx_bytes: Number of bytes requested | |
111 | * @dev_busy: Device busy flag | |
112 | * @is_decoded_cs: Flag for decoder property set or not | |
7b40322f | 113 | * @tx_fifo_depth: Depth of the TX FIFO |
c474b386 HK |
114 | */ |
115 | struct cdns_spi { | |
116 | void __iomem *regs; | |
117 | struct clk *ref_clk; | |
118 | struct clk *pclk; | |
4d163ad7 | 119 | unsigned int clk_rate; |
c474b386 HK |
120 | u32 speed_hz; |
121 | const u8 *txbuf; | |
122 | u8 *rxbuf; | |
123 | int tx_bytes; | |
124 | int rx_bytes; | |
125 | u8 dev_busy; | |
126 | u32 is_decoded_cs; | |
7b40322f | 127 | unsigned int tx_fifo_depth; |
c474b386 HK |
128 | }; |
129 | ||
130 | /* Macros for the SPI controller read/write */ | |
131 | static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) | |
132 | { | |
133 | return readl_relaxed(xspi->regs + offset); | |
134 | } | |
135 | ||
136 | static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) | |
137 | { | |
138 | writel_relaxed(val, xspi->regs + offset); | |
139 | } | |
140 | ||
141 | /** | |
142 | * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller | |
143 | * @xspi: Pointer to the cdns_spi structure | |
f75c04a9 YY |
144 | * @is_target: Flag to indicate target or host mode |
145 | * * On reset the SPI controller is configured to target or host mode. | |
146 | * In host mode baud rate divisor is set to 4, threshold value for TX FIFO | |
b1b90514 | 147 | * not full interrupt is set to 1 and size of the word to be transferred as 8 bit. |
c474b386 | 148 | * |
c474b386 | 149 | * This function initializes the SPI controller to disable and clear all the |
f75c04a9 | 150 | * interrupts, enable manual target select and manual start, deselect all the |
c474b386 HK |
151 | * chip select lines, and enable the SPI controller. |
152 | */ | |
f75c04a9 | 153 | static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target) |
c474b386 | 154 | { |
b1b90514 SG |
155 | u32 ctrl_reg = 0; |
156 | ||
f75c04a9 | 157 | if (!is_target) |
b1b90514 | 158 | ctrl_reg |= CDNS_SPI_CR_DEFAULT; |
ee0ebe81 LPC |
159 | |
160 | if (xspi->is_decoded_cs) | |
24746675 | 161 | ctrl_reg |= CDNS_SPI_CR_PERI_SEL; |
ee0ebe81 | 162 | |
24746675 SD |
163 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
164 | cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); | |
c474b386 HK |
165 | |
166 | /* Clear the RX FIFO */ | |
24746675 SD |
167 | while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) |
168 | cdns_spi_read(xspi, CDNS_SPI_RXD); | |
169 | ||
170 | cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL); | |
171 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); | |
172 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); | |
c474b386 HK |
173 | } |
174 | ||
175 | /** | |
176 | * cdns_spi_chipselect - Select or deselect the chip select line | |
177 | * @spi: Pointer to the spi_device structure | |
61acd19f | 178 | * @is_high: Select(0) or deselect (1) the chip select line |
c474b386 | 179 | */ |
61acd19f | 180 | static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) |
c474b386 | 181 | { |
f6997e9b | 182 | struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller); |
c474b386 HK |
183 | u32 ctrl_reg; |
184 | ||
24746675 | 185 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
c474b386 | 186 | |
61acd19f | 187 | if (is_high) { |
f75c04a9 | 188 | /* Deselect the target */ |
24746675 | 189 | ctrl_reg |= CDNS_SPI_CR_SSCTRL; |
c474b386 | 190 | } else { |
f75c04a9 | 191 | /* Select the target */ |
24746675 | 192 | ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; |
c474b386 | 193 | if (!(xspi->is_decoded_cs)) |
9e264f3f | 194 | ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) << |
c474b386 | 195 | CDNS_SPI_SS_SHIFT) & |
24746675 | 196 | CDNS_SPI_CR_SSCTRL; |
c474b386 | 197 | else |
9e264f3f | 198 | ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) & |
24746675 | 199 | CDNS_SPI_CR_SSCTRL; |
c474b386 HK |
200 | } |
201 | ||
24746675 | 202 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
c474b386 HK |
203 | } |
204 | ||
205 | /** | |
206 | * cdns_spi_config_clock_mode - Sets clock polarity and phase | |
207 | * @spi: Pointer to the spi_device structure | |
208 | * | |
209 | * Sets the requested clock polarity and phase. | |
210 | */ | |
211 | static void cdns_spi_config_clock_mode(struct spi_device *spi) | |
212 | { | |
f6997e9b | 213 | struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller); |
a39e65e9 | 214 | u32 ctrl_reg, new_ctrl_reg; |
c474b386 | 215 | |
57bb1369 SD |
216 | new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
217 | ctrl_reg = new_ctrl_reg; | |
c474b386 HK |
218 | |
219 | /* Set the SPI clock phase and clock polarity */ | |
24746675 | 220 | new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL); |
c474b386 | 221 | if (spi->mode & SPI_CPHA) |
24746675 | 222 | new_ctrl_reg |= CDNS_SPI_CR_CPHA; |
c474b386 | 223 | if (spi->mode & SPI_CPOL) |
24746675 | 224 | new_ctrl_reg |= CDNS_SPI_CR_CPOL; |
a39e65e9 LPC |
225 | |
226 | if (new_ctrl_reg != ctrl_reg) { | |
227 | /* | |
228 | * Just writing the CR register does not seem to apply the clock | |
229 | * setting changes. This is problematic when changing the clock | |
f75c04a9 | 230 | * polarity as it will cause the SPI target to see spurious clock |
a39e65e9 LPC |
231 | * transitions. To workaround the issue toggle the ER register. |
232 | */ | |
24746675 SD |
233 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
234 | cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg); | |
235 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); | |
a39e65e9 | 236 | } |
c474b386 HK |
237 | } |
238 | ||
239 | /** | |
240 | * cdns_spi_config_clock_freq - Sets clock frequency | |
241 | * @spi: Pointer to the spi_device structure | |
242 | * @transfer: Pointer to the spi_transfer structure which provides | |
243 | * information about next transfer setup parameters | |
244 | * | |
245 | * Sets the requested clock frequency. | |
246 | * Note: If the requested frequency is not an exact match with what can be | |
247 | * obtained using the prescalar value the driver sets the clock frequency which | |
248 | * is lower than the requested frequency (maximum lower) for the transfer. If | |
249 | * the requested frequency is higher or lower than that is supported by the SPI | |
250 | * controller the driver will set the highest or lowest frequency supported by | |
251 | * controller. | |
252 | */ | |
253 | static void cdns_spi_config_clock_freq(struct spi_device *spi, | |
57bb1369 | 254 | struct spi_transfer *transfer) |
c474b386 | 255 | { |
f6997e9b | 256 | struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller); |
c474b386 HK |
257 | u32 ctrl_reg, baud_rate_val; |
258 | unsigned long frequency; | |
259 | ||
4d163ad7 | 260 | frequency = xspi->clk_rate; |
c474b386 | 261 | |
24746675 | 262 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
c474b386 HK |
263 | |
264 | /* Set the clock frequency */ | |
265 | if (xspi->speed_hz != transfer->speed_hz) { | |
266 | /* first valid value is 1 */ | |
267 | baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; | |
268 | while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && | |
269 | (frequency / (2 << baud_rate_val)) > transfer->speed_hz) | |
270 | baud_rate_val++; | |
271 | ||
24746675 | 272 | ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV; |
c474b386 HK |
273 | ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; |
274 | ||
275 | xspi->speed_hz = frequency / (2 << baud_rate_val); | |
276 | } | |
24746675 | 277 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
c474b386 HK |
278 | } |
279 | ||
280 | /** | |
281 | * cdns_spi_setup_transfer - Configure SPI controller for specified transfer | |
282 | * @spi: Pointer to the spi_device structure | |
283 | * @transfer: Pointer to the spi_transfer structure which provides | |
284 | * information about next transfer setup parameters | |
285 | * | |
286 | * Sets the operational mode of SPI controller for the next SPI transfer and | |
287 | * sets the requested clock frequency. | |
288 | * | |
289 | * Return: Always 0 | |
290 | */ | |
291 | static int cdns_spi_setup_transfer(struct spi_device *spi, | |
292 | struct spi_transfer *transfer) | |
293 | { | |
f6997e9b | 294 | struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller); |
c474b386 HK |
295 | |
296 | cdns_spi_config_clock_freq(spi, transfer); | |
297 | ||
298 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", | |
299 | __func__, spi->mode, spi->bits_per_word, | |
300 | xspi->speed_hz); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | /** | |
6afe2ae8 | 306 | * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO |
c474b386 | 307 | * @xspi: Pointer to the cdns_spi structure |
6afe2ae8 CK |
308 | * @ntx: Number of bytes to pack into the TX FIFO |
309 | * @nrx: Number of bytes to drain from the RX FIFO | |
c474b386 | 310 | */ |
6afe2ae8 | 311 | static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx) |
c474b386 | 312 | { |
6afe2ae8 CK |
313 | ntx = clamp(ntx, 0, xspi->tx_bytes); |
314 | nrx = clamp(nrx, 0, xspi->rx_bytes); | |
c474b386 | 315 | |
6afe2ae8 CK |
316 | xspi->tx_bytes -= ntx; |
317 | xspi->rx_bytes -= nrx; | |
49530e64 | 318 | |
6afe2ae8 | 319 | while (ntx || nrx) { |
633cd6fe AKM |
320 | if (nrx) { |
321 | u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD); | |
322 | ||
323 | if (xspi->rxbuf) | |
324 | *xspi->rxbuf++ = data; | |
325 | ||
326 | nrx--; | |
327 | } | |
328 | ||
6afe2ae8 CK |
329 | if (ntx) { |
330 | if (xspi->txbuf) | |
331 | cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); | |
332 | else | |
333 | cdns_spi_write(xspi, CDNS_SPI_TXD, 0); | |
c474b386 | 334 | |
6afe2ae8 CK |
335 | ntx--; |
336 | } | |
c474b386 | 337 | |
b1b90514 SG |
338 | } |
339 | } | |
340 | ||
c474b386 HK |
341 | /** |
342 | * cdns_spi_irq - Interrupt service routine of the SPI controller | |
343 | * @irq: IRQ number | |
344 | * @dev_id: Pointer to the xspi structure | |
345 | * | |
346 | * This function handles TX empty and Mode Fault interrupts only. | |
347 | * On TX empty interrupt this function reads the received data from RX FIFO and | |
348 | * fills the TX FIFO if there is any data remaining to be transferred. | |
349 | * On Mode Fault interrupt this function indicates that transfer is completed, | |
350 | * the SPI subsystem will identify the error as the remaining bytes to be | |
351 | * transferred is non-zero. | |
352 | * | |
353 | * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. | |
354 | */ | |
355 | static irqreturn_t cdns_spi_irq(int irq, void *dev_id) | |
356 | { | |
f6997e9b SG |
357 | struct spi_controller *ctlr = dev_id; |
358 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); | |
22d35e40 AKM |
359 | irqreturn_t status; |
360 | u32 intr_status; | |
c474b386 HK |
361 | |
362 | status = IRQ_NONE; | |
24746675 SD |
363 | intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR); |
364 | cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status); | |
c474b386 | 365 | |
24746675 | 366 | if (intr_status & CDNS_SPI_IXR_MODF) { |
c474b386 HK |
367 | /* Indicate that transfer is completed, the SPI subsystem will |
368 | * identify the error as the remaining bytes to be | |
369 | * transferred is non-zero | |
370 | */ | |
24746675 | 371 | cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); |
f6997e9b | 372 | spi_finalize_current_transfer(ctlr); |
c474b386 | 373 | status = IRQ_HANDLED; |
24746675 | 374 | } else if (intr_status & CDNS_SPI_IXR_TXOW) { |
a84c11e1 CK |
375 | int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD); |
376 | int trans_cnt = xspi->rx_bytes - xspi->tx_bytes; | |
377 | ||
378 | if (threshold > 1) | |
379 | trans_cnt -= threshold; | |
380 | ||
b1b90514 SG |
381 | /* Set threshold to one if number of pending are |
382 | * less than half fifo | |
383 | */ | |
384 | if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1) | |
385 | cdns_spi_write(xspi, CDNS_SPI_THLD, 1); | |
c474b386 | 386 | |
a84c11e1 | 387 | if (xspi->tx_bytes) { |
6afe2ae8 | 388 | cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt); |
a84c11e1 | 389 | } else { |
627d05a4 SG |
390 | /* Fixed delay due to controller limitation with |
391 | * RX_NEMPTY incorrect status | |
392 | * Xilinx AR:65885 contains more details | |
393 | */ | |
394 | udelay(10); | |
6afe2ae8 | 395 | cdns_spi_process_fifo(xspi, 0, trans_cnt); |
24746675 SD |
396 | cdns_spi_write(xspi, CDNS_SPI_IDR, |
397 | CDNS_SPI_IXR_DEFAULT); | |
f6997e9b | 398 | spi_finalize_current_transfer(ctlr); |
c474b386 HK |
399 | } |
400 | status = IRQ_HANDLED; | |
401 | } | |
402 | ||
403 | return status; | |
404 | } | |
57bb1369 | 405 | |
f6997e9b | 406 | static int cdns_prepare_message(struct spi_controller *ctlr, |
b48b9488 LPC |
407 | struct spi_message *msg) |
408 | { | |
f75c04a9 | 409 | if (!spi_controller_is_target(ctlr)) |
b1b90514 | 410 | cdns_spi_config_clock_mode(msg->spi); |
b48b9488 LPC |
411 | return 0; |
412 | } | |
c474b386 HK |
413 | |
414 | /** | |
415 | * cdns_transfer_one - Initiates the SPI transfer | |
f6997e9b | 416 | * @ctlr: Pointer to spi_controller structure |
c474b386 HK |
417 | * @spi: Pointer to the spi_device structure |
418 | * @transfer: Pointer to the spi_transfer structure which provides | |
419 | * information about next transfer parameters | |
420 | * | |
f75c04a9 | 421 | * This function in host mode fills the TX FIFO, starts the SPI transfer and |
c474b386 | 422 | * returns a positive transfer count so that core will wait for completion. |
f75c04a9 | 423 | * This function in target mode fills the TX FIFO and wait for transfer trigger. |
c474b386 HK |
424 | * |
425 | * Return: Number of bytes transferred in the last transfer | |
426 | */ | |
f6997e9b | 427 | static int cdns_transfer_one(struct spi_controller *ctlr, |
c474b386 HK |
428 | struct spi_device *spi, |
429 | struct spi_transfer *transfer) | |
430 | { | |
f6997e9b | 431 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); |
c474b386 HK |
432 | |
433 | xspi->txbuf = transfer->tx_buf; | |
434 | xspi->rxbuf = transfer->rx_buf; | |
435 | xspi->tx_bytes = transfer->len; | |
436 | xspi->rx_bytes = transfer->len; | |
437 | ||
f75c04a9 | 438 | if (!spi_controller_is_target(ctlr)) { |
b1b90514 | 439 | cdns_spi_setup_transfer(spi, transfer); |
a0eb7be2 CK |
440 | } else { |
441 | /* Set TX empty threshold to half of FIFO depth | |
627d05a4 | 442 | * only if TX bytes are more than FIFO depth. |
a0eb7be2 CK |
443 | */ |
444 | if (xspi->tx_bytes > xspi->tx_fifo_depth) | |
445 | cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1); | |
446 | } | |
b1b90514 | 447 | |
627d05a4 SG |
448 | /* When xspi in busy condition, bytes may send failed, |
449 | * then spi control didn't work thoroughly, add one byte delay | |
450 | */ | |
451 | if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL) | |
452 | udelay(10); | |
453 | ||
6afe2ae8 | 454 | cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0); |
c474b386 | 455 | |
24746675 | 456 | cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT); |
c474b386 HK |
457 | return transfer->len; |
458 | } | |
459 | ||
460 | /** | |
461 | * cdns_prepare_transfer_hardware - Prepares hardware for transfer. | |
f6997e9b | 462 | * @ctlr: Pointer to the spi_controller structure which provides |
c474b386 HK |
463 | * information about the controller. |
464 | * | |
f75c04a9 | 465 | * This function enables SPI host controller. |
c474b386 HK |
466 | * |
467 | * Return: 0 always | |
468 | */ | |
f6997e9b | 469 | static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr) |
c474b386 | 470 | { |
f6997e9b | 471 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); |
c474b386 | 472 | |
24746675 | 473 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); |
c474b386 HK |
474 | |
475 | return 0; | |
476 | } | |
477 | ||
478 | /** | |
479 | * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer | |
f6997e9b | 480 | * @ctlr: Pointer to the spi_controller structure which provides |
c474b386 HK |
481 | * information about the controller. |
482 | * | |
f75c04a9 | 483 | * This function disables the SPI host controller when no target selected. |
b1b90514 | 484 | * This function flush out if any pending data in FIFO. |
c474b386 HK |
485 | * |
486 | * Return: 0 always | |
487 | */ | |
f6997e9b | 488 | static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr) |
c474b386 | 489 | { |
f6997e9b | 490 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); |
21b511dd | 491 | u32 ctrl_reg; |
b1b90514 SG |
492 | unsigned int cnt = xspi->tx_fifo_depth; |
493 | ||
f75c04a9 | 494 | if (spi_controller_is_target(ctlr)) { |
b1b90514 SG |
495 | while (cnt--) |
496 | cdns_spi_read(xspi, CDNS_SPI_RXD); | |
497 | } | |
c474b386 | 498 | |
f75c04a9 | 499 | /* Disable the SPI if target is deselected */ |
21b511dd SKP |
500 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
501 | ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT; | |
f75c04a9 | 502 | if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr)) |
21b511dd | 503 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
c474b386 | 504 | |
b1b90514 SG |
505 | /* Reset to default */ |
506 | cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1); | |
c474b386 HK |
507 | return 0; |
508 | } | |
509 | ||
7b40322f LPC |
510 | /** |
511 | * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware | |
512 | * @xspi: Pointer to the cdns_spi structure | |
513 | * | |
514 | * The depth of the TX FIFO is a synthesis configuration parameter of the SPI | |
515 | * IP. The FIFO threshold register is sized so that its maximum value can be the | |
516 | * FIFO size - 1. This is used to detect the size of the FIFO. | |
517 | */ | |
518 | static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi) | |
519 | { | |
520 | /* The MSBs will get truncated giving us the size of the FIFO */ | |
521 | cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff); | |
522 | xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1; | |
523 | ||
524 | /* Reset to default */ | |
525 | cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1); | |
526 | } | |
527 | ||
b1b90514 | 528 | /** |
f75c04a9 | 529 | * cdns_target_abort - Abort target transfer |
b1b90514 SG |
530 | * @ctlr: Pointer to the spi_controller structure |
531 | * | |
f75c04a9 | 532 | * This function abort target transfer if there any transfer timeout. |
b1b90514 SG |
533 | * |
534 | * Return: 0 always | |
535 | */ | |
f75c04a9 | 536 | static int cdns_target_abort(struct spi_controller *ctlr) |
b1b90514 SG |
537 | { |
538 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); | |
539 | u32 intr_status; | |
540 | ||
541 | intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR); | |
542 | cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status); | |
543 | cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY)); | |
544 | spi_finalize_current_transfer(ctlr); | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
c474b386 HK |
549 | /** |
550 | * cdns_spi_probe - Probe method for the SPI driver | |
551 | * @pdev: Pointer to the platform_device structure | |
552 | * | |
553 | * This function initializes the driver data structures and the hardware. | |
554 | * | |
555 | * Return: 0 on success and error value on error | |
556 | */ | |
557 | static int cdns_spi_probe(struct platform_device *pdev) | |
558 | { | |
559 | int ret = 0, irq; | |
f6997e9b | 560 | struct spi_controller *ctlr; |
c474b386 | 561 | struct cdns_spi *xspi; |
c474b386 | 562 | u32 num_cs; |
f75c04a9 | 563 | bool target; |
b1b90514 | 564 | |
f75c04a9 YY |
565 | target = of_property_read_bool(pdev->dev.of_node, "spi-slave"); |
566 | if (target) | |
567 | ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi)); | |
b1b90514 | 568 | else |
f75c04a9 | 569 | ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi)); |
c474b386 | 570 | |
f6997e9b | 571 | if (!ctlr) |
c474b386 HK |
572 | return -ENOMEM; |
573 | ||
f6997e9b SG |
574 | xspi = spi_controller_get_devdata(ctlr); |
575 | ctlr->dev.of_node = pdev->dev.of_node; | |
576 | platform_set_drvdata(pdev, ctlr); | |
c474b386 | 577 | |
4585bb92 | 578 | xspi->regs = devm_platform_ioremap_resource(pdev, 0); |
c474b386 HK |
579 | if (IS_ERR(xspi->regs)) { |
580 | ret = PTR_ERR(xspi->regs); | |
f6997e9b | 581 | goto remove_ctlr; |
c474b386 HK |
582 | } |
583 | ||
f64b1600 | 584 | xspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); |
c474b386 HK |
585 | if (IS_ERR(xspi->pclk)) { |
586 | dev_err(&pdev->dev, "pclk clock not found.\n"); | |
587 | ret = PTR_ERR(xspi->pclk); | |
f6997e9b | 588 | goto remove_ctlr; |
c474b386 HK |
589 | } |
590 | ||
f75c04a9 | 591 | if (!spi_controller_is_target(ctlr)) { |
f64b1600 | 592 | xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk"); |
b1b90514 SG |
593 | if (IS_ERR(xspi->ref_clk)) { |
594 | dev_err(&pdev->dev, "ref_clk clock not found.\n"); | |
595 | ret = PTR_ERR(xspi->ref_clk); | |
f64b1600 | 596 | goto remove_ctlr; |
b1b90514 | 597 | } |
56912da7 | 598 | |
b1b90514 SG |
599 | pm_runtime_use_autosuspend(&pdev->dev); |
600 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
601 | pm_runtime_get_noresume(&pdev->dev); | |
602 | pm_runtime_set_active(&pdev->dev); | |
603 | pm_runtime_enable(&pdev->dev); | |
604 | ||
605 | ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); | |
606 | if (ret < 0) | |
607 | ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; | |
608 | else | |
609 | ctlr->num_chipselect = num_cs; | |
3cc29106 | 610 | |
b1b90514 SG |
611 | ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", |
612 | &xspi->is_decoded_cs); | |
613 | if (ret < 0) | |
614 | xspi->is_decoded_cs = 0; | |
615 | } | |
3cc29106 | 616 | |
7b40322f LPC |
617 | cdns_spi_detect_fifo_depth(xspi); |
618 | ||
c474b386 | 619 | /* SPI controller initializations */ |
f75c04a9 | 620 | cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr)); |
c474b386 HK |
621 | |
622 | irq = platform_get_irq(pdev, 0); | |
8102d64c RJ |
623 | if (irq < 0) { |
624 | ret = irq; | |
50ac697b | 625 | goto clk_dis_all; |
c474b386 HK |
626 | } |
627 | ||
628 | ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, | |
f6997e9b | 629 | 0, pdev->name, ctlr); |
c474b386 HK |
630 | if (ret != 0) { |
631 | ret = -ENXIO; | |
632 | dev_err(&pdev->dev, "request_irq failed\n"); | |
50ac697b | 633 | goto clk_dis_all; |
c474b386 HK |
634 | } |
635 | ||
f6997e9b SG |
636 | ctlr->use_gpio_descriptors = true; |
637 | ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware; | |
638 | ctlr->prepare_message = cdns_prepare_message; | |
639 | ctlr->transfer_one = cdns_transfer_one; | |
640 | ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; | |
b1b90514 | 641 | ctlr->mode_bits = SPI_CPOL | SPI_CPHA; |
f6997e9b | 642 | ctlr->bits_per_word_mask = SPI_BPW_MASK(8); |
c474b386 | 643 | |
f75c04a9 | 644 | if (!spi_controller_is_target(ctlr)) { |
b1b90514 SG |
645 | ctlr->mode_bits |= SPI_CS_HIGH; |
646 | ctlr->set_cs = cdns_spi_chipselect; | |
647 | ctlr->auto_runtime_pm = true; | |
648 | xspi->clk_rate = clk_get_rate(xspi->ref_clk); | |
649 | /* Set to default valid value */ | |
650 | ctlr->max_speed_hz = xspi->clk_rate / 4; | |
651 | xspi->speed_hz = ctlr->max_speed_hz; | |
652 | pm_runtime_mark_last_busy(&pdev->dev); | |
653 | pm_runtime_put_autosuspend(&pdev->dev); | |
654 | } else { | |
655 | ctlr->mode_bits |= SPI_NO_CS; | |
f75c04a9 | 656 | ctlr->target_abort = cdns_target_abort; |
b1b90514 | 657 | } |
f6997e9b | 658 | ret = spi_register_controller(ctlr); |
c474b386 | 659 | if (ret) { |
f6997e9b | 660 | dev_err(&pdev->dev, "spi_register_controller failed\n"); |
c474b386 HK |
661 | goto clk_dis_all; |
662 | } | |
663 | ||
664 | return ret; | |
665 | ||
666 | clk_dis_all: | |
f75c04a9 | 667 | if (!spi_controller_is_target(ctlr)) { |
b1b90514 SG |
668 | pm_runtime_set_suspended(&pdev->dev); |
669 | pm_runtime_disable(&pdev->dev); | |
b1b90514 | 670 | } |
f6997e9b SG |
671 | remove_ctlr: |
672 | spi_controller_put(ctlr); | |
c474b386 HK |
673 | return ret; |
674 | } | |
675 | ||
676 | /** | |
677 | * cdns_spi_remove - Remove method for the SPI driver | |
678 | * @pdev: Pointer to the platform_device structure | |
679 | * | |
680 | * This function is called if a device is physically removed from the system or | |
681 | * if the driver module is being unloaded. It frees all resources allocated to | |
682 | * the device. | |
c474b386 | 683 | */ |
42735301 | 684 | static void cdns_spi_remove(struct platform_device *pdev) |
c474b386 | 685 | { |
f6997e9b SG |
686 | struct spi_controller *ctlr = platform_get_drvdata(pdev); |
687 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); | |
c474b386 | 688 | |
24746675 | 689 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
c474b386 | 690 | |
d36ccd9f SD |
691 | pm_runtime_set_suspended(&pdev->dev); |
692 | pm_runtime_disable(&pdev->dev); | |
c474b386 | 693 | |
f6997e9b | 694 | spi_unregister_controller(ctlr); |
c474b386 HK |
695 | } |
696 | ||
697 | /** | |
698 | * cdns_spi_suspend - Suspend method for the SPI driver | |
699 | * @dev: Address of the platform_device structure | |
700 | * | |
701 | * This function disables the SPI controller and | |
702 | * changes the driver state to "suspend" | |
703 | * | |
6fe9b67d | 704 | * Return: 0 on success and error value on error |
c474b386 HK |
705 | */ |
706 | static int __maybe_unused cdns_spi_suspend(struct device *dev) | |
707 | { | |
f6997e9b | 708 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
c474b386 | 709 | |
f6997e9b | 710 | return spi_controller_suspend(ctlr); |
c474b386 HK |
711 | } |
712 | ||
713 | /** | |
714 | * cdns_spi_resume - Resume method for the SPI driver | |
715 | * @dev: Address of the platform_device structure | |
716 | * | |
717 | * This function changes the driver state to "ready" | |
718 | * | |
719 | * Return: 0 on success and error value on error | |
720 | */ | |
721 | static int __maybe_unused cdns_spi_resume(struct device *dev) | |
722 | { | |
f6997e9b SG |
723 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
724 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); | |
c474b386 | 725 | |
f75c04a9 | 726 | cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr)); |
f6997e9b | 727 | return spi_controller_resume(ctlr); |
c474b386 HK |
728 | } |
729 | ||
d36ccd9f SD |
730 | /** |
731 | * cdns_spi_runtime_resume - Runtime resume method for the SPI driver | |
732 | * @dev: Address of the platform_device structure | |
733 | * | |
734 | * This function enables the clocks | |
735 | * | |
736 | * Return: 0 on success and error value on error | |
737 | */ | |
4df6836d | 738 | static int __maybe_unused cdns_spi_runtime_resume(struct device *dev) |
d36ccd9f | 739 | { |
f6997e9b SG |
740 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
741 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); | |
d36ccd9f SD |
742 | int ret; |
743 | ||
744 | ret = clk_prepare_enable(xspi->pclk); | |
745 | if (ret) { | |
746 | dev_err(dev, "Cannot enable APB clock.\n"); | |
747 | return ret; | |
748 | } | |
749 | ||
750 | ret = clk_prepare_enable(xspi->ref_clk); | |
751 | if (ret) { | |
752 | dev_err(dev, "Cannot enable device clock.\n"); | |
2ba87a9b | 753 | clk_disable_unprepare(xspi->pclk); |
d36ccd9f SD |
754 | return ret; |
755 | } | |
756 | return 0; | |
757 | } | |
758 | ||
759 | /** | |
760 | * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver | |
761 | * @dev: Address of the platform_device structure | |
762 | * | |
763 | * This function disables the clocks | |
764 | * | |
765 | * Return: Always 0 | |
766 | */ | |
4df6836d | 767 | static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev) |
d36ccd9f | 768 | { |
f6997e9b SG |
769 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
770 | struct cdns_spi *xspi = spi_controller_get_devdata(ctlr); | |
d36ccd9f SD |
771 | |
772 | clk_disable_unprepare(xspi->ref_clk); | |
773 | clk_disable_unprepare(xspi->pclk); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static const struct dev_pm_ops cdns_spi_dev_pm_ops = { | |
4df6836d MS |
779 | SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend, |
780 | cdns_spi_runtime_resume, NULL) | |
d36ccd9f SD |
781 | SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume) |
782 | }; | |
c474b386 | 783 | |
f7f994a4 | 784 | static const struct of_device_id cdns_spi_of_match[] = { |
c474b386 HK |
785 | { .compatible = "xlnx,zynq-spi-r1p6" }, |
786 | { .compatible = "cdns,spi-r1p6" }, | |
787 | { /* end of table */ } | |
788 | }; | |
789 | MODULE_DEVICE_TABLE(of, cdns_spi_of_match); | |
790 | ||
791 | /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ | |
792 | static struct platform_driver cdns_spi_driver = { | |
793 | .probe = cdns_spi_probe, | |
42735301 | 794 | .remove_new = cdns_spi_remove, |
c474b386 HK |
795 | .driver = { |
796 | .name = CDNS_SPI_NAME, | |
c474b386 HK |
797 | .of_match_table = cdns_spi_of_match, |
798 | .pm = &cdns_spi_dev_pm_ops, | |
799 | }, | |
800 | }; | |
801 | ||
802 | module_platform_driver(cdns_spi_driver); | |
803 | ||
804 | MODULE_AUTHOR("Xilinx, Inc."); | |
805 | MODULE_DESCRIPTION("Cadence SPI driver"); | |
806 | MODULE_LICENSE("GPL"); |