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59899843 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c474b386 HK |
2 | /* |
3 | * Cadence SPI controller driver (master mode only) | |
4 | * | |
5 | * Copyright (C) 2008 - 2014 Xilinx, Inc. | |
6 | * | |
7 | * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) | |
c474b386 HK |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
cfeefa79 | 12 | #include <linux/gpio/consumer.h> |
c474b386 HK |
13 | #include <linux/interrupt.h> |
14 | #include <linux/io.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/platform_device.h> | |
d36ccd9f | 19 | #include <linux/pm_runtime.h> |
c474b386 HK |
20 | #include <linux/spi/spi.h> |
21 | ||
22 | /* Name of this driver */ | |
23 | #define CDNS_SPI_NAME "cdns-spi" | |
24 | ||
25 | /* Register offset definitions */ | |
24746675 SD |
26 | #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */ |
27 | #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */ | |
28 | #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */ | |
29 | #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */ | |
30 | #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */ | |
31 | #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */ | |
32 | #define CDNS_SPI_DR 0x18 /* Delay Register, RW */ | |
33 | #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */ | |
34 | #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */ | |
35 | #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */ | |
36 | #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */ | |
c474b386 | 37 | |
d36ccd9f | 38 | #define SPI_AUTOSUSPEND_TIMEOUT 3000 |
c474b386 HK |
39 | /* |
40 | * SPI Configuration Register bit Masks | |
41 | * | |
42 | * This register contains various control bits that affect the operation | |
43 | * of the SPI controller | |
44 | */ | |
24746675 SD |
45 | #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */ |
46 | #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */ | |
47 | #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */ | |
48 | #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */ | |
49 | #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */ | |
50 | #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */ | |
51 | #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */ | |
52 | #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */ | |
53 | #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */ | |
54 | #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */ | |
55 | #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \ | |
56 | CDNS_SPI_CR_SSCTRL | \ | |
57 | CDNS_SPI_CR_SSFORCE | \ | |
58 | CDNS_SPI_CR_BAUD_DIV_4) | |
c474b386 HK |
59 | |
60 | /* | |
61 | * SPI Configuration Register - Baud rate and slave select | |
62 | * | |
63 | * These are the values used in the calculation of baud rate divisor and | |
64 | * setting the slave select. | |
65 | */ | |
66 | ||
67 | #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ | |
68 | #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ | |
69 | #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ | |
70 | #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ | |
71 | #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ | |
72 | ||
73 | /* | |
74 | * SPI Interrupt Registers bit Masks | |
75 | * | |
76 | * All the four interrupt registers (Status/Mask/Enable/Disable) have the same | |
77 | * bit definitions. | |
78 | */ | |
24746675 SD |
79 | #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */ |
80 | #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */ | |
81 | #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */ | |
82 | #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \ | |
83 | CDNS_SPI_IXR_MODF) | |
84 | #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */ | |
85 | #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */ | |
c474b386 HK |
86 | |
87 | /* | |
88 | * SPI Enable Register bit Masks | |
89 | * | |
90 | * This register is used to enable or disable the SPI controller | |
91 | */ | |
24746675 SD |
92 | #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */ |
93 | #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */ | |
c474b386 HK |
94 | |
95 | /* SPI FIFO depth in bytes */ | |
96 | #define CDNS_SPI_FIFO_DEPTH 128 | |
97 | ||
98 | /* Default number of chip select lines */ | |
99 | #define CDNS_SPI_DEFAULT_NUM_CS 4 | |
100 | ||
101 | /** | |
102 | * struct cdns_spi - This definition defines spi driver instance | |
103 | * @regs: Virtual address of the SPI controller registers | |
104 | * @ref_clk: Pointer to the peripheral clock | |
105 | * @pclk: Pointer to the APB clock | |
106 | * @speed_hz: Current SPI bus clock speed in Hz | |
107 | * @txbuf: Pointer to the TX buffer | |
108 | * @rxbuf: Pointer to the RX buffer | |
109 | * @tx_bytes: Number of bytes left to transfer | |
110 | * @rx_bytes: Number of bytes requested | |
111 | * @dev_busy: Device busy flag | |
112 | * @is_decoded_cs: Flag for decoder property set or not | |
113 | */ | |
114 | struct cdns_spi { | |
115 | void __iomem *regs; | |
116 | struct clk *ref_clk; | |
117 | struct clk *pclk; | |
4d163ad7 | 118 | unsigned int clk_rate; |
c474b386 HK |
119 | u32 speed_hz; |
120 | const u8 *txbuf; | |
121 | u8 *rxbuf; | |
122 | int tx_bytes; | |
123 | int rx_bytes; | |
124 | u8 dev_busy; | |
125 | u32 is_decoded_cs; | |
126 | }; | |
127 | ||
128 | /* Macros for the SPI controller read/write */ | |
129 | static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) | |
130 | { | |
131 | return readl_relaxed(xspi->regs + offset); | |
132 | } | |
133 | ||
134 | static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) | |
135 | { | |
136 | writel_relaxed(val, xspi->regs + offset); | |
137 | } | |
138 | ||
139 | /** | |
140 | * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller | |
141 | * @xspi: Pointer to the cdns_spi structure | |
142 | * | |
143 | * On reset the SPI controller is configured to be in master mode, baud rate | |
144 | * divisor is set to 4, threshold value for TX FIFO not full interrupt is set | |
145 | * to 1 and size of the word to be transferred as 8 bit. | |
146 | * This function initializes the SPI controller to disable and clear all the | |
147 | * interrupts, enable manual slave select and manual start, deselect all the | |
148 | * chip select lines, and enable the SPI controller. | |
149 | */ | |
150 | static void cdns_spi_init_hw(struct cdns_spi *xspi) | |
151 | { | |
24746675 | 152 | u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; |
ee0ebe81 LPC |
153 | |
154 | if (xspi->is_decoded_cs) | |
24746675 | 155 | ctrl_reg |= CDNS_SPI_CR_PERI_SEL; |
ee0ebe81 | 156 | |
24746675 SD |
157 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
158 | cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); | |
c474b386 HK |
159 | |
160 | /* Clear the RX FIFO */ | |
24746675 SD |
161 | while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) |
162 | cdns_spi_read(xspi, CDNS_SPI_RXD); | |
163 | ||
164 | cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL); | |
165 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); | |
166 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); | |
c474b386 HK |
167 | } |
168 | ||
169 | /** | |
170 | * cdns_spi_chipselect - Select or deselect the chip select line | |
171 | * @spi: Pointer to the spi_device structure | |
61acd19f | 172 | * @is_high: Select(0) or deselect (1) the chip select line |
c474b386 | 173 | */ |
61acd19f | 174 | static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) |
c474b386 HK |
175 | { |
176 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); | |
177 | u32 ctrl_reg; | |
178 | ||
24746675 | 179 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
c474b386 | 180 | |
61acd19f | 181 | if (is_high) { |
c474b386 | 182 | /* Deselect the slave */ |
24746675 | 183 | ctrl_reg |= CDNS_SPI_CR_SSCTRL; |
c474b386 HK |
184 | } else { |
185 | /* Select the slave */ | |
24746675 | 186 | ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; |
c474b386 HK |
187 | if (!(xspi->is_decoded_cs)) |
188 | ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << | |
189 | CDNS_SPI_SS_SHIFT) & | |
24746675 | 190 | CDNS_SPI_CR_SSCTRL; |
c474b386 HK |
191 | else |
192 | ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & | |
24746675 | 193 | CDNS_SPI_CR_SSCTRL; |
c474b386 HK |
194 | } |
195 | ||
24746675 | 196 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
c474b386 HK |
197 | } |
198 | ||
199 | /** | |
200 | * cdns_spi_config_clock_mode - Sets clock polarity and phase | |
201 | * @spi: Pointer to the spi_device structure | |
202 | * | |
203 | * Sets the requested clock polarity and phase. | |
204 | */ | |
205 | static void cdns_spi_config_clock_mode(struct spi_device *spi) | |
206 | { | |
207 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); | |
a39e65e9 | 208 | u32 ctrl_reg, new_ctrl_reg; |
c474b386 | 209 | |
57bb1369 SD |
210 | new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
211 | ctrl_reg = new_ctrl_reg; | |
c474b386 HK |
212 | |
213 | /* Set the SPI clock phase and clock polarity */ | |
24746675 | 214 | new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL); |
c474b386 | 215 | if (spi->mode & SPI_CPHA) |
24746675 | 216 | new_ctrl_reg |= CDNS_SPI_CR_CPHA; |
c474b386 | 217 | if (spi->mode & SPI_CPOL) |
24746675 | 218 | new_ctrl_reg |= CDNS_SPI_CR_CPOL; |
a39e65e9 LPC |
219 | |
220 | if (new_ctrl_reg != ctrl_reg) { | |
221 | /* | |
222 | * Just writing the CR register does not seem to apply the clock | |
223 | * setting changes. This is problematic when changing the clock | |
224 | * polarity as it will cause the SPI slave to see spurious clock | |
225 | * transitions. To workaround the issue toggle the ER register. | |
226 | */ | |
24746675 SD |
227 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
228 | cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg); | |
229 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); | |
a39e65e9 | 230 | } |
c474b386 HK |
231 | } |
232 | ||
233 | /** | |
234 | * cdns_spi_config_clock_freq - Sets clock frequency | |
235 | * @spi: Pointer to the spi_device structure | |
236 | * @transfer: Pointer to the spi_transfer structure which provides | |
237 | * information about next transfer setup parameters | |
238 | * | |
239 | * Sets the requested clock frequency. | |
240 | * Note: If the requested frequency is not an exact match with what can be | |
241 | * obtained using the prescalar value the driver sets the clock frequency which | |
242 | * is lower than the requested frequency (maximum lower) for the transfer. If | |
243 | * the requested frequency is higher or lower than that is supported by the SPI | |
244 | * controller the driver will set the highest or lowest frequency supported by | |
245 | * controller. | |
246 | */ | |
247 | static void cdns_spi_config_clock_freq(struct spi_device *spi, | |
57bb1369 | 248 | struct spi_transfer *transfer) |
c474b386 HK |
249 | { |
250 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); | |
251 | u32 ctrl_reg, baud_rate_val; | |
252 | unsigned long frequency; | |
253 | ||
4d163ad7 | 254 | frequency = xspi->clk_rate; |
c474b386 | 255 | |
24746675 | 256 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
c474b386 HK |
257 | |
258 | /* Set the clock frequency */ | |
259 | if (xspi->speed_hz != transfer->speed_hz) { | |
260 | /* first valid value is 1 */ | |
261 | baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; | |
262 | while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && | |
263 | (frequency / (2 << baud_rate_val)) > transfer->speed_hz) | |
264 | baud_rate_val++; | |
265 | ||
24746675 | 266 | ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV; |
c474b386 HK |
267 | ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; |
268 | ||
269 | xspi->speed_hz = frequency / (2 << baud_rate_val); | |
270 | } | |
24746675 | 271 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
c474b386 HK |
272 | } |
273 | ||
274 | /** | |
275 | * cdns_spi_setup_transfer - Configure SPI controller for specified transfer | |
276 | * @spi: Pointer to the spi_device structure | |
277 | * @transfer: Pointer to the spi_transfer structure which provides | |
278 | * information about next transfer setup parameters | |
279 | * | |
280 | * Sets the operational mode of SPI controller for the next SPI transfer and | |
281 | * sets the requested clock frequency. | |
282 | * | |
283 | * Return: Always 0 | |
284 | */ | |
285 | static int cdns_spi_setup_transfer(struct spi_device *spi, | |
286 | struct spi_transfer *transfer) | |
287 | { | |
288 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); | |
289 | ||
290 | cdns_spi_config_clock_freq(spi, transfer); | |
291 | ||
292 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", | |
293 | __func__, spi->mode, spi->bits_per_word, | |
294 | xspi->speed_hz); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | /** | |
300 | * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible | |
301 | * @xspi: Pointer to the cdns_spi structure | |
302 | */ | |
303 | static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) | |
304 | { | |
305 | unsigned long trans_cnt = 0; | |
306 | ||
307 | while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && | |
308 | (xspi->tx_bytes > 0)) { | |
49530e64 | 309 | |
310 | /* When xspi in busy condition, bytes may send failed, | |
311 | * then spi control did't work thoroughly, add one byte delay | |
312 | */ | |
313 | if (cdns_spi_read(xspi, CDNS_SPI_ISR) & | |
314 | CDNS_SPI_IXR_TXFULL) | |
931c4e9a | 315 | udelay(10); |
49530e64 | 316 | |
c474b386 | 317 | if (xspi->txbuf) |
24746675 | 318 | cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); |
c474b386 | 319 | else |
24746675 | 320 | cdns_spi_write(xspi, CDNS_SPI_TXD, 0); |
c474b386 HK |
321 | |
322 | xspi->tx_bytes--; | |
323 | trans_cnt++; | |
324 | } | |
325 | } | |
326 | ||
327 | /** | |
328 | * cdns_spi_irq - Interrupt service routine of the SPI controller | |
329 | * @irq: IRQ number | |
330 | * @dev_id: Pointer to the xspi structure | |
331 | * | |
332 | * This function handles TX empty and Mode Fault interrupts only. | |
333 | * On TX empty interrupt this function reads the received data from RX FIFO and | |
334 | * fills the TX FIFO if there is any data remaining to be transferred. | |
335 | * On Mode Fault interrupt this function indicates that transfer is completed, | |
336 | * the SPI subsystem will identify the error as the remaining bytes to be | |
337 | * transferred is non-zero. | |
338 | * | |
339 | * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. | |
340 | */ | |
341 | static irqreturn_t cdns_spi_irq(int irq, void *dev_id) | |
342 | { | |
343 | struct spi_master *master = dev_id; | |
344 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
345 | u32 intr_status, status; | |
346 | ||
347 | status = IRQ_NONE; | |
24746675 SD |
348 | intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR); |
349 | cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status); | |
c474b386 | 350 | |
24746675 | 351 | if (intr_status & CDNS_SPI_IXR_MODF) { |
c474b386 HK |
352 | /* Indicate that transfer is completed, the SPI subsystem will |
353 | * identify the error as the remaining bytes to be | |
354 | * transferred is non-zero | |
355 | */ | |
24746675 | 356 | cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); |
c474b386 HK |
357 | spi_finalize_current_transfer(master); |
358 | status = IRQ_HANDLED; | |
24746675 | 359 | } else if (intr_status & CDNS_SPI_IXR_TXOW) { |
c474b386 HK |
360 | unsigned long trans_cnt; |
361 | ||
362 | trans_cnt = xspi->rx_bytes - xspi->tx_bytes; | |
363 | ||
364 | /* Read out the data from the RX FIFO */ | |
365 | while (trans_cnt) { | |
366 | u8 data; | |
367 | ||
24746675 | 368 | data = cdns_spi_read(xspi, CDNS_SPI_RXD); |
c474b386 HK |
369 | if (xspi->rxbuf) |
370 | *xspi->rxbuf++ = data; | |
371 | ||
372 | xspi->rx_bytes--; | |
373 | trans_cnt--; | |
374 | } | |
375 | ||
376 | if (xspi->tx_bytes) { | |
377 | /* There is more data to send */ | |
378 | cdns_spi_fill_tx_fifo(xspi); | |
379 | } else { | |
380 | /* Transfer is completed */ | |
24746675 SD |
381 | cdns_spi_write(xspi, CDNS_SPI_IDR, |
382 | CDNS_SPI_IXR_DEFAULT); | |
c474b386 HK |
383 | spi_finalize_current_transfer(master); |
384 | } | |
385 | status = IRQ_HANDLED; | |
386 | } | |
387 | ||
388 | return status; | |
389 | } | |
57bb1369 | 390 | |
b48b9488 LPC |
391 | static int cdns_prepare_message(struct spi_master *master, |
392 | struct spi_message *msg) | |
393 | { | |
394 | cdns_spi_config_clock_mode(msg->spi); | |
395 | return 0; | |
396 | } | |
c474b386 HK |
397 | |
398 | /** | |
399 | * cdns_transfer_one - Initiates the SPI transfer | |
400 | * @master: Pointer to spi_master structure | |
401 | * @spi: Pointer to the spi_device structure | |
402 | * @transfer: Pointer to the spi_transfer structure which provides | |
403 | * information about next transfer parameters | |
404 | * | |
405 | * This function fills the TX FIFO, starts the SPI transfer and | |
406 | * returns a positive transfer count so that core will wait for completion. | |
407 | * | |
408 | * Return: Number of bytes transferred in the last transfer | |
409 | */ | |
410 | static int cdns_transfer_one(struct spi_master *master, | |
411 | struct spi_device *spi, | |
412 | struct spi_transfer *transfer) | |
413 | { | |
414 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
415 | ||
416 | xspi->txbuf = transfer->tx_buf; | |
417 | xspi->rxbuf = transfer->rx_buf; | |
418 | xspi->tx_bytes = transfer->len; | |
419 | xspi->rx_bytes = transfer->len; | |
420 | ||
421 | cdns_spi_setup_transfer(spi, transfer); | |
c474b386 | 422 | cdns_spi_fill_tx_fifo(xspi); |
855a40cd | 423 | spi_transfer_delay_exec(transfer); |
c474b386 | 424 | |
24746675 | 425 | cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT); |
c474b386 HK |
426 | return transfer->len; |
427 | } | |
428 | ||
429 | /** | |
430 | * cdns_prepare_transfer_hardware - Prepares hardware for transfer. | |
431 | * @master: Pointer to the spi_master structure which provides | |
432 | * information about the controller. | |
433 | * | |
434 | * This function enables SPI master controller. | |
435 | * | |
436 | * Return: 0 always | |
437 | */ | |
438 | static int cdns_prepare_transfer_hardware(struct spi_master *master) | |
439 | { | |
440 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
441 | ||
24746675 | 442 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); |
c474b386 HK |
443 | |
444 | return 0; | |
445 | } | |
446 | ||
447 | /** | |
448 | * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer | |
449 | * @master: Pointer to the spi_master structure which provides | |
450 | * information about the controller. | |
451 | * | |
452 | * This function disables the SPI master controller. | |
453 | * | |
454 | * Return: 0 always | |
455 | */ | |
456 | static int cdns_unprepare_transfer_hardware(struct spi_master *master) | |
457 | { | |
458 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
459 | ||
24746675 | 460 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
c474b386 HK |
461 | |
462 | return 0; | |
463 | } | |
464 | ||
465 | /** | |
466 | * cdns_spi_probe - Probe method for the SPI driver | |
467 | * @pdev: Pointer to the platform_device structure | |
468 | * | |
469 | * This function initializes the driver data structures and the hardware. | |
470 | * | |
471 | * Return: 0 on success and error value on error | |
472 | */ | |
473 | static int cdns_spi_probe(struct platform_device *pdev) | |
474 | { | |
475 | int ret = 0, irq; | |
476 | struct spi_master *master; | |
477 | struct cdns_spi *xspi; | |
c474b386 HK |
478 | u32 num_cs; |
479 | ||
480 | master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); | |
15a1c503 | 481 | if (!master) |
c474b386 HK |
482 | return -ENOMEM; |
483 | ||
484 | xspi = spi_master_get_devdata(master); | |
485 | master->dev.of_node = pdev->dev.of_node; | |
486 | platform_set_drvdata(pdev, master); | |
487 | ||
4585bb92 | 488 | xspi->regs = devm_platform_ioremap_resource(pdev, 0); |
c474b386 HK |
489 | if (IS_ERR(xspi->regs)) { |
490 | ret = PTR_ERR(xspi->regs); | |
491 | goto remove_master; | |
492 | } | |
493 | ||
494 | xspi->pclk = devm_clk_get(&pdev->dev, "pclk"); | |
495 | if (IS_ERR(xspi->pclk)) { | |
496 | dev_err(&pdev->dev, "pclk clock not found.\n"); | |
497 | ret = PTR_ERR(xspi->pclk); | |
498 | goto remove_master; | |
499 | } | |
500 | ||
501 | xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); | |
502 | if (IS_ERR(xspi->ref_clk)) { | |
503 | dev_err(&pdev->dev, "ref_clk clock not found.\n"); | |
504 | ret = PTR_ERR(xspi->ref_clk); | |
505 | goto remove_master; | |
506 | } | |
507 | ||
508 | ret = clk_prepare_enable(xspi->pclk); | |
509 | if (ret) { | |
510 | dev_err(&pdev->dev, "Unable to enable APB clock.\n"); | |
511 | goto remove_master; | |
512 | } | |
513 | ||
514 | ret = clk_prepare_enable(xspi->ref_clk); | |
515 | if (ret) { | |
516 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); | |
517 | goto clk_dis_apb; | |
518 | } | |
519 | ||
3cc29106 PC |
520 | ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); |
521 | if (ret < 0) | |
522 | master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; | |
523 | else | |
524 | master->num_chipselect = num_cs; | |
525 | ||
526 | ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", | |
527 | &xspi->is_decoded_cs); | |
528 | if (ret < 0) | |
529 | xspi->is_decoded_cs = 0; | |
530 | ||
c474b386 HK |
531 | /* SPI controller initializations */ |
532 | cdns_spi_init_hw(xspi); | |
533 | ||
734882a8 CK |
534 | pm_runtime_set_active(&pdev->dev); |
535 | pm_runtime_enable(&pdev->dev); | |
536 | pm_runtime_use_autosuspend(&pdev->dev); | |
537 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
d36ccd9f | 538 | |
c474b386 HK |
539 | irq = platform_get_irq(pdev, 0); |
540 | if (irq <= 0) { | |
541 | ret = -ENXIO; | |
50ac697b | 542 | goto clk_dis_all; |
c474b386 HK |
543 | } |
544 | ||
545 | ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, | |
546 | 0, pdev->name, master); | |
547 | if (ret != 0) { | |
548 | ret = -ENXIO; | |
549 | dev_err(&pdev->dev, "request_irq failed\n"); | |
50ac697b | 550 | goto clk_dis_all; |
c474b386 HK |
551 | } |
552 | ||
cfeefa79 | 553 | master->use_gpio_descriptors = true; |
c474b386 | 554 | master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; |
b48b9488 | 555 | master->prepare_message = cdns_prepare_message; |
c474b386 HK |
556 | master->transfer_one = cdns_transfer_one; |
557 | master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; | |
558 | master->set_cs = cdns_spi_chipselect; | |
d36ccd9f | 559 | master->auto_runtime_pm = true; |
ce8e60fe | 560 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
c474b386 | 561 | |
4d163ad7 | 562 | xspi->clk_rate = clk_get_rate(xspi->ref_clk); |
c474b386 | 563 | /* Set to default valid value */ |
4d163ad7 | 564 | master->max_speed_hz = xspi->clk_rate / 4; |
c474b386 HK |
565 | xspi->speed_hz = master->max_speed_hz; |
566 | ||
567 | master->bits_per_word_mask = SPI_BPW_MASK(8); | |
568 | ||
569 | ret = spi_register_master(master); | |
570 | if (ret) { | |
571 | dev_err(&pdev->dev, "spi_register_master failed\n"); | |
572 | goto clk_dis_all; | |
573 | } | |
574 | ||
575 | return ret; | |
576 | ||
577 | clk_dis_all: | |
d36ccd9f SD |
578 | pm_runtime_set_suspended(&pdev->dev); |
579 | pm_runtime_disable(&pdev->dev); | |
c474b386 HK |
580 | clk_disable_unprepare(xspi->ref_clk); |
581 | clk_dis_apb: | |
582 | clk_disable_unprepare(xspi->pclk); | |
583 | remove_master: | |
584 | spi_master_put(master); | |
585 | return ret; | |
586 | } | |
587 | ||
588 | /** | |
589 | * cdns_spi_remove - Remove method for the SPI driver | |
590 | * @pdev: Pointer to the platform_device structure | |
591 | * | |
592 | * This function is called if a device is physically removed from the system or | |
593 | * if the driver module is being unloaded. It frees all resources allocated to | |
594 | * the device. | |
595 | * | |
596 | * Return: 0 on success and error value on error | |
597 | */ | |
598 | static int cdns_spi_remove(struct platform_device *pdev) | |
599 | { | |
600 | struct spi_master *master = platform_get_drvdata(pdev); | |
601 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
602 | ||
24746675 | 603 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
c474b386 HK |
604 | |
605 | clk_disable_unprepare(xspi->ref_clk); | |
606 | clk_disable_unprepare(xspi->pclk); | |
d36ccd9f SD |
607 | pm_runtime_set_suspended(&pdev->dev); |
608 | pm_runtime_disable(&pdev->dev); | |
c474b386 HK |
609 | |
610 | spi_unregister_master(master); | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | /** | |
616 | * cdns_spi_suspend - Suspend method for the SPI driver | |
617 | * @dev: Address of the platform_device structure | |
618 | * | |
619 | * This function disables the SPI controller and | |
620 | * changes the driver state to "suspend" | |
621 | * | |
6fe9b67d | 622 | * Return: 0 on success and error value on error |
c474b386 HK |
623 | */ |
624 | static int __maybe_unused cdns_spi_suspend(struct device *dev) | |
625 | { | |
e1f16b04 | 626 | struct spi_master *master = dev_get_drvdata(dev); |
c474b386 | 627 | |
6fe9b67d | 628 | return spi_master_suspend(master); |
c474b386 HK |
629 | } |
630 | ||
631 | /** | |
632 | * cdns_spi_resume - Resume method for the SPI driver | |
633 | * @dev: Address of the platform_device structure | |
634 | * | |
635 | * This function changes the driver state to "ready" | |
636 | * | |
637 | * Return: 0 on success and error value on error | |
638 | */ | |
639 | static int __maybe_unused cdns_spi_resume(struct device *dev) | |
640 | { | |
e1f16b04 | 641 | struct spi_master *master = dev_get_drvdata(dev); |
80274089 | 642 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
c474b386 | 643 | |
80274089 | 644 | cdns_spi_init_hw(xspi); |
6fe9b67d | 645 | return spi_master_resume(master); |
c474b386 HK |
646 | } |
647 | ||
d36ccd9f SD |
648 | /** |
649 | * cdns_spi_runtime_resume - Runtime resume method for the SPI driver | |
650 | * @dev: Address of the platform_device structure | |
651 | * | |
652 | * This function enables the clocks | |
653 | * | |
654 | * Return: 0 on success and error value on error | |
655 | */ | |
148b1eb9 | 656 | static int __maybe_unused cnds_runtime_resume(struct device *dev) |
d36ccd9f SD |
657 | { |
658 | struct spi_master *master = dev_get_drvdata(dev); | |
659 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
660 | int ret; | |
661 | ||
662 | ret = clk_prepare_enable(xspi->pclk); | |
663 | if (ret) { | |
664 | dev_err(dev, "Cannot enable APB clock.\n"); | |
665 | return ret; | |
666 | } | |
667 | ||
668 | ret = clk_prepare_enable(xspi->ref_clk); | |
669 | if (ret) { | |
670 | dev_err(dev, "Cannot enable device clock.\n"); | |
2ba87a9b | 671 | clk_disable_unprepare(xspi->pclk); |
d36ccd9f SD |
672 | return ret; |
673 | } | |
674 | return 0; | |
675 | } | |
676 | ||
677 | /** | |
678 | * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver | |
679 | * @dev: Address of the platform_device structure | |
680 | * | |
681 | * This function disables the clocks | |
682 | * | |
683 | * Return: Always 0 | |
684 | */ | |
148b1eb9 | 685 | static int __maybe_unused cnds_runtime_suspend(struct device *dev) |
d36ccd9f SD |
686 | { |
687 | struct spi_master *master = dev_get_drvdata(dev); | |
688 | struct cdns_spi *xspi = spi_master_get_devdata(master); | |
689 | ||
690 | clk_disable_unprepare(xspi->ref_clk); | |
691 | clk_disable_unprepare(xspi->pclk); | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | static const struct dev_pm_ops cdns_spi_dev_pm_ops = { | |
697 | SET_RUNTIME_PM_OPS(cnds_runtime_suspend, | |
698 | cnds_runtime_resume, NULL) | |
699 | SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume) | |
700 | }; | |
c474b386 | 701 | |
f7f994a4 | 702 | static const struct of_device_id cdns_spi_of_match[] = { |
c474b386 HK |
703 | { .compatible = "xlnx,zynq-spi-r1p6" }, |
704 | { .compatible = "cdns,spi-r1p6" }, | |
705 | { /* end of table */ } | |
706 | }; | |
707 | MODULE_DEVICE_TABLE(of, cdns_spi_of_match); | |
708 | ||
709 | /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ | |
710 | static struct platform_driver cdns_spi_driver = { | |
711 | .probe = cdns_spi_probe, | |
712 | .remove = cdns_spi_remove, | |
713 | .driver = { | |
714 | .name = CDNS_SPI_NAME, | |
c474b386 HK |
715 | .of_match_table = cdns_spi_of_match, |
716 | .pm = &cdns_spi_dev_pm_ops, | |
717 | }, | |
718 | }; | |
719 | ||
720 | module_platform_driver(cdns_spi_driver); | |
721 | ||
722 | MODULE_AUTHOR("Xilinx, Inc."); | |
723 | MODULE_DESCRIPTION("Cadence SPI driver"); | |
724 | MODULE_LICENSE("GPL"); |