[linux-2.6-block.git] / drivers / spi / spi-bitbang.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * polling/bitbanging SPI master controller driver utilities
 */

#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>

#define SPI_BITBANG_CS_DELAY	100


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits, unsigned flags);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits,
						unsigned flags),
					unsigned, struct spi_transfer *,
					unsigned);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (1000000000/2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/**
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi->master);

	if (!cs) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word)
		return -EINVAL;

	if (bitbang->setup_transfer) {
		int retval = bitbang->setup_transfer(spi, NULL);
		if (retval < 0)
			return retval;
	}

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/**
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi->master);
	if (bitbang->set_line_direction) {
		int err;

		err = bitbang->set_line_direction(spi, !!(t->tx_buf));
		if (err < 0)
			return err;
	}

	if (spi->mode & SPI_3WIRE) {
		unsigned flags;

		flags = t->tx_buf ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX;
		return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
	}
	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */

static int spi_bitbang_prepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 1;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static int spi_bitbang_transfer_one(struct spi_master *master,
				    struct spi_device *spi,
				    struct spi_transfer *transfer)
{
	struct spi_bitbang *bitbang = spi_master_get_devdata(master);
	int status = 0;

	if (bitbang->setup_transfer) {
		status = bitbang->setup_transfer(spi, transfer);
		if (status < 0)
			goto out;
	}

	if (transfer->len)
		status = bitbang->txrx_bufs(spi, transfer);

	if (status == transfer->len)
		status = 0;
	else if (status >= 0)
		status = -EREMOTEIO;

out:
	spi_finalize_current_transfer(master);

	return status;
}

static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 0;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
{
	struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);

	/* SPI core provides CS high / low, but bitbang driver
	 * expects CS active
	 * spi device driver takes care of handling SPI_CS_HIGH
	 */
	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);

	ndelay(SPI_BITBANG_CS_DELAY);
	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
			    BITBANG_CS_INACTIVE);
	ndelay(SPI_BITBANG_CS_DELAY);
}

/*----------------------------------------------------------------------*/

int spi_bitbang_init(struct spi_bitbang *bitbang)
{
	struct spi_master *master = bitbang->master;

	if (!master || !bitbang->chipselect)
		return -EINVAL;

	mutex_init(&bitbang->lock);

	if (!master->mode_bits)
		master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (master->transfer || master->transfer_one_message)
		return -EINVAL;

	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	master->transfer_one = spi_bitbang_transfer_one;
	master->set_cs = spi_bitbang_set_cs;

	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!master->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			master->setup = spi_bitbang_setup;
			master->cleanup = spi_bitbang_cleanup;
		}
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_init);

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the master has
 * a transfer method, its final step should call spi_bitbang_transfer; or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_master, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 *
 * On success, this routine will take a reference to master. The caller is
 * responsible for calling spi_bitbang_stop() to decrement the reference and
 * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
 * leak.
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	struct spi_master *master = bitbang->master;
	int ret;

	ret = spi_bitbang_init(bitbang);
	if (ret)
		return ret;

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	ret = spi_register_master(spi_master_get(master));
	if (ret)
		spi_master_put(master);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/**
 * spi_bitbang_stop - stops the task providing spi communication
 */
void spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_master(bitbang->master);
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
9904f22a	2	/*
ca632f55	3	* polling/bitbanging SPI master controller driver utilities
9904f22a DB	4	*/
9904f22a DB	5
9904f22a DB	6	#include <linux/spinlock.h>
	7	#include <linux/workqueue.h>
	8	#include <linux/interrupt.h>
d7614de4	9	#include <linux/module.h>
9904f22a DB	10	#include <linux/delay.h>
	11	#include <linux/errno.h>
	12	#include <linux/platform_device.h>
5a0e3ad6	13	#include <linux/slab.h>
9904f22a DB	14
	15	#include <linux/spi/spi.h>
	16	#include <linux/spi/spi_bitbang.h>
	17
00376865 HK	18	#define SPI_BITBANG_CS_DELAY 100
00376865 HK	19
9904f22a DB	20
	21	/----------------------------------------------------------------------/
	22
	23	/*
	24	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	25	* Use this for GPIO or shift-register level hardware APIs.
	26	*
	27	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	28	* to glue code. These bitbang setup() and cleanup() routines are always
	29	* used, though maybe they're called from controller-aware code.
	30	*
03ddcbc5	31	* chipselect() and friends may use spi_device->controller_data and
9904f22a DB	32	* controller registers as appropriate.
	33	*
	34	*
	35	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	36	* which means you could use a bitbang driver either to get hardware
	37	* working quickly, or testing for differences that aren't speed related.
	38	*/
	39
	40	struct spi_bitbang_cs {
	41	unsigned nsecs; /* (clock cycle time)/2 */
	42	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
304d3436	43	u32 word, u8 bits, unsigned flags);
9904f22a DB	44	unsigned (txrx_bufs)(struct spi_device ,
	45	u32 (*txrx_word)(
	46	struct spi_device *spi,
	47	unsigned nsecs,
304d3436 LB	48	u32 word, u8 bits,
	49	unsigned flags),
	50	unsigned, struct spi_transfer *,
	51	unsigned);
9904f22a DB	52	};
	53
	54	static unsigned bitbang_txrx_8(
	55	struct spi_device *spi,
	56	u32 (txrx_word)(struct spi_device spi,
	57	unsigned nsecs,
304d3436 LB	58	u32 word, u8 bits,
304d3436 LB	59	unsigned flags),
9904f22a	60	unsigned ns,
304d3436 LB	61	struct spi_transfer *t,
304d3436 LB	62	unsigned flags
9904f22a	63	) {
766ed704	64	unsigned bits = t->bits_per_word;
9904f22a DB	65	unsigned count = t->len;
	66	const u8 *tx = t->tx_buf;
	67	u8 *rx = t->rx_buf;
	68
	69	while (likely(count > 0)) {
	70	u8 word = 0;
	71
	72	if (tx)
	73	word = *tx++;
304d3436	74	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	75	if (rx)
	76	*rx++ = word;
	77	count -= 1;
	78	}
	79	return t->len - count;
	80	}
	81
	82	static unsigned bitbang_txrx_16(
	83	struct spi_device *spi,
	84	u32 (txrx_word)(struct spi_device spi,
	85	unsigned nsecs,
304d3436 LB	86	u32 word, u8 bits,
304d3436 LB	87	unsigned flags),
9904f22a	88	unsigned ns,
304d3436 LB	89	struct spi_transfer *t,
304d3436 LB	90	unsigned flags
9904f22a	91	) {
766ed704	92	unsigned bits = t->bits_per_word;
9904f22a DB	93	unsigned count = t->len;
	94	const u16 *tx = t->tx_buf;
	95	u16 *rx = t->rx_buf;
	96
	97	while (likely(count > 1)) {
	98	u16 word = 0;
	99
	100	if (tx)
	101	word = *tx++;
304d3436	102	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	103	if (rx)
	104	*rx++ = word;
	105	count -= 2;
	106	}
	107	return t->len - count;
	108	}
	109
	110	static unsigned bitbang_txrx_32(
	111	struct spi_device *spi,
	112	u32 (txrx_word)(struct spi_device spi,
	113	unsigned nsecs,
304d3436 LB	114	u32 word, u8 bits,
304d3436 LB	115	unsigned flags),
9904f22a	116	unsigned ns,
304d3436 LB	117	struct spi_transfer *t,
304d3436 LB	118	unsigned flags
9904f22a	119	) {
766ed704	120	unsigned bits = t->bits_per_word;
9904f22a DB	121	unsigned count = t->len;
	122	const u32 *tx = t->tx_buf;
	123	u32 *rx = t->rx_buf;
	124
	125	while (likely(count > 3)) {
	126	u32 word = 0;
	127
	128	if (tx)
	129	word = *tx++;
304d3436	130	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	131	if (rx)
	132	*rx++ = word;
	133	count -= 4;
	134	}
	135	return t->len - count;
	136	}
	137
ff9f4771	138	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	139	{
	140	struct spi_bitbang_cs *cs = spi->controller_state;
	141	u8 bits_per_word;
	142	u32 hz;
	143
	144	if (t) {
	145	bits_per_word = t->bits_per_word;
	146	hz = t->speed_hz;
	147	} else {
	148	bits_per_word = 0;
	149	hz = 0;
	150	}
	151
	152	/* spi_transfer level calls that work per-word */
	153	if (!bits_per_word)
	154	bits_per_word = spi->bits_per_word;
	155	if (bits_per_word <= 8)
	156	cs->txrx_bufs = bitbang_txrx_8;
	157	else if (bits_per_word <= 16)
	158	cs->txrx_bufs = bitbang_txrx_16;
	159	else if (bits_per_word <= 32)
	160	cs->txrx_bufs = bitbang_txrx_32;
	161	else
	162	return -EINVAL;
	163
	164	/* nsecs = (clock period)/2 */
	165	if (!hz)
	166	hz = spi->max_speed_hz;
1e316d75 DB	167	if (hz) {
	168	cs->nsecs = (1000000000/2) / hz;
	169	if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
	170	return -EINVAL;
	171	}
4cff33f9 ID	172
	173	return 0;
	174	}
ff9f4771	175	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	176
9904f22a DB	177	/**
	178	* spi_bitbang_setup - default setup for per-word I/O loops
	179	*/
	180	int spi_bitbang_setup(struct spi_device *spi)
	181	{
	182	struct spi_bitbang_cs *cs = spi->controller_state;
	183	struct spi_bitbang *bitbang;
	184
ccf77cc4 DB	185	bitbang = spi_master_get_devdata(spi->master);
ccf77cc4 DB	186
9904f22a	187	if (!cs) {
cff93c58	188	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
9904f22a DB	189	if (!cs)
	190	return -ENOMEM;
	191	spi->controller_state = cs;
	192	}
9904f22a	193
9904f22a DB	194	/* per-word shift register access, in hardware or bitbanging */
	195	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
	196	if (!cs->txrx_word)
	197	return -EINVAL;
	198
7d0ec8b6 PN	199	if (bitbang->setup_transfer) {
	200	int retval = bitbang->setup_transfer(spi, NULL);
	201	if (retval < 0)
	202	return retval;
	203	}
9904f22a	204
7d077197	205	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a	206
9904f22a DB	207	return 0;
	208	}
	209	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	210
	211	/**
	212	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
	213	*/
0ffa0285	214	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	215	{
	216	kfree(spi->controller_state);
	217	}
	218	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	219
	220	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	221	{
	222	struct spi_bitbang_cs *cs = spi->controller_state;
	223	unsigned nsecs = cs->nsecs;
4b859db2 LB	224	struct spi_bitbang *bitbang;
	225
	226	bitbang = spi_master_get_devdata(spi->master);
	227	if (bitbang->set_line_direction) {
	228	int err;
9904f22a	229
4b859db2 LB	230	err = bitbang->set_line_direction(spi, !!(t->tx_buf));
	231	if (err < 0)
	232	return err;
	233	}
	234
	235	if (spi->mode & SPI_3WIRE) {
	236	unsigned flags;
	237
	238	flags = t->tx_buf ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX;
	239	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
	240	}
304d3436	241	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
9904f22a DB	242	}
	243
	244	/----------------------------------------------------------------------/
	245
	246	/*
	247	* SECOND PART ... simple transfer queue runner.
	248	*
	249	* This costs a task context per controller, running the queue by
	250	* performing each transfer in sequence. Smarter hardware can queue
	251	* several DMA transfers at once, and process several controller queues
	252	* in parallel; this driver doesn't match such hardware very well.
	253	*
	254	* Drivers can provide word-at-a-time i/o primitives, or provide
	255	* transfer-at-a-time ones to leverage dma or fifo hardware.
	256	*/
2025172e MB	257
	258	static int spi_bitbang_prepare_hardware(struct spi_master *spi)
	259	{
cff93c58	260	struct spi_bitbang *bitbang;
2025172e MB	261
	262	bitbang = spi_master_get_devdata(spi);
	263
c15f6ed3	264	mutex_lock(&bitbang->lock);
2025172e	265	bitbang->busy = 1;
c15f6ed3	266	mutex_unlock(&bitbang->lock);
2025172e MB	267
	268	return 0;
	269	}
	270
d60990d5	271	static int spi_bitbang_transfer_one(struct spi_master *master,
00376865 HK	272	struct spi_device *spi,
00376865 HK	273	struct spi_transfer *transfer)
9904f22a	274	{
00376865 HK	275	struct spi_bitbang *bitbang = spi_master_get_devdata(master);
00376865 HK	276	int status = 0;
91b30858	277
00376865 HK	278	if (bitbang->setup_transfer) {
	279	status = bitbang->setup_transfer(spi, transfer);
	280	if (status < 0)
	281	goto out;
91b30858 MB	282	}
91b30858 MB	283
00376865 HK	284	if (transfer->len)
00376865 HK	285	status = bitbang->txrx_bufs(spi, transfer);
91b30858	286
00376865 HK	287	if (status == transfer->len)
	288	status = 0;
	289	else if (status >= 0)
	290	status = -EREMOTEIO;
91b30858	291
00376865 HK	292	out:
00376865 HK	293	spi_finalize_current_transfer(master);
9904f22a	294
2025172e	295	return status;
9904f22a DB	296	}
9904f22a DB	297
2025172e	298	static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
9904f22a	299	{
cff93c58	300	struct spi_bitbang *bitbang;
9904f22a	301
2025172e	302	bitbang = spi_master_get_devdata(spi);
9904f22a	303
c15f6ed3	304	mutex_lock(&bitbang->lock);
2025172e	305	bitbang->busy = 0;
c15f6ed3	306	mutex_unlock(&bitbang->lock);
9904f22a	307
2025172e	308	return 0;
9904f22a	309	}
9904f22a	310
00376865 HK	311	static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
	312	{
	313	struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);
	314
	315	/* SPI core provides CS high / low, but bitbang driver
	316	* expects CS active
	317	* spi device driver takes care of handling SPI_CS_HIGH
	318	*/
	319	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
	320
	321	ndelay(SPI_BITBANG_CS_DELAY);
	322	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
	323	BITBANG_CS_INACTIVE);
	324	ndelay(SPI_BITBANG_CS_DELAY);
	325	}
	326
9904f22a DB	327	/----------------------------------------------------------------------/
9904f22a DB	328
45beec35 AS	329	int spi_bitbang_init(struct spi_bitbang *bitbang)
	330	{
	331	struct spi_master *master = bitbang->master;
	332
	333	if (!master \|\| !bitbang->chipselect)
	334	return -EINVAL;
	335
	336	mutex_init(&bitbang->lock);
	337
	338	if (!master->mode_bits)
	339	master->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
	340
	341	if (master->transfer \|\| master->transfer_one_message)
	342	return -EINVAL;
	343
	344	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	345	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	346	master->transfer_one = spi_bitbang_transfer_one;
	347	master->set_cs = spi_bitbang_set_cs;
	348
	349	if (!bitbang->txrx_bufs) {
	350	bitbang->use_dma = 0;
	351	bitbang->txrx_bufs = spi_bitbang_bufs;
	352	if (!master->setup) {
	353	if (!bitbang->setup_transfer)
	354	bitbang->setup_transfer =
	355	spi_bitbang_setup_transfer;
	356	master->setup = spi_bitbang_setup;
	357	master->cleanup = spi_bitbang_cleanup;
	358	}
	359	}
	360
	361	return 0;
	362	}
	363	EXPORT_SYMBOL_GPL(spi_bitbang_init);
	364
9904f22a DB	365	/**
	366	* spi_bitbang_start - start up a polled/bitbanging SPI master driver
	367	* @bitbang: driver handle
	368	*
	369	* Caller should have zero-initialized all parts of the structure, and then
	370	* provided callbacks for chip selection and I/O loops. If the master has
	371	* a transfer method, its final step should call spi_bitbang_transfer; or,
	372	* that's the default if the transfer routine is not initialized. It should
	373	* also set up the bus number and number of chipselects.
	374	*
	375	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	376	* hardware that basically exposes a shift register) or per-spi_transfer
	377	* (which takes better advantage of hardware like fifos or DMA engines).
	378	*
7f8c7619 HPN	379	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
	380	* spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
	381	* master methods. Those methods are the defaults if the bitbang->txrx_bufs
	382	* routine isn't initialized.
9904f22a DB	383	*
	384	* This routine registers the spi_master, which will process requests in a
	385	* dedicated task, keeping IRQs unblocked most of the time. To stop
	386	* processing those requests, call spi_bitbang_stop().
702a4879 AL	387	*
	388	* On success, this routine will take a reference to master. The caller is
	389	* responsible for calling spi_bitbang_stop() to decrement the reference and
	390	* spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
	391	* leak.
9904f22a DB	392	*/
	393	int spi_bitbang_start(struct spi_bitbang *bitbang)
	394	{
7a5d8ca1	395	struct spi_master *master = bitbang->master;
702a4879	396	int ret;
9904f22a	397
45beec35 AS	398	ret = spi_bitbang_init(bitbang);
	399	if (ret)
	400	return ret;
9904f22a DB	401
	402	/* driver may get busy before register() returns, especially
	403	* if someone registered boardinfo for devices
	404	*/
702a4879 AL	405	ret = spi_register_master(spi_master_get(master));
	406	if (ret)
	407	spi_master_put(master);
	408
	409	return 0;
9904f22a DB	410	}
	411	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	412
	413	/**
	414	* spi_bitbang_stop - stops the task providing spi communication
	415	*/
d9721ae1	416	void spi_bitbang_stop(struct spi_bitbang *bitbang)
9904f22a	417	{
a836f585	418	spi_unregister_master(bitbang->master);
9904f22a DB	419	}
	420	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	421
	422	MODULE_LICENSE("GPL");
	423