[linux-block.git] / drivers / spi / spi-bitbang.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * polling/bitbanging SPI master controller driver utilities
 */

#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>

#define SPI_BITBANG_CS_DELAY	100


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits, unsigned flags);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits,
						unsigned flags),
					unsigned, struct spi_transfer *,
					unsigned);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
)
{
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
)
{
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
)
{
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (1000000000/2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/*
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi->master);

	if (!cs) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word)
		return -EINVAL;

	if (bitbang->setup_transfer) {
		int retval = bitbang->setup_transfer(spi, NULL);
		if (retval < 0)
			return retval;
	}

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/*
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi->master);
	if (bitbang->set_line_direction) {
		int err;

		err = bitbang->set_line_direction(spi, !!(t->tx_buf));
		if (err < 0)
			return err;
	}

	if (spi->mode & SPI_3WIRE) {
		unsigned flags;

		flags = t->tx_buf ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX;
		return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
	}
	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */

static int spi_bitbang_prepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 1;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static int spi_bitbang_transfer_one(struct spi_master *master,
				    struct spi_device *spi,
				    struct spi_transfer *transfer)
{
	struct spi_bitbang *bitbang = spi_master_get_devdata(master);
	int status = 0;

	if (bitbang->setup_transfer) {
		status = bitbang->setup_transfer(spi, transfer);
		if (status < 0)
			goto out;
	}

	if (transfer->len)
		status = bitbang->txrx_bufs(spi, transfer);

	if (status == transfer->len)
		status = 0;
	else if (status >= 0)
		status = -EREMOTEIO;

out:
	spi_finalize_current_transfer(master);

	return status;
}

static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 0;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
{
	struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);

	/* SPI core provides CS high / low, but bitbang driver
	 * expects CS active
	 * spi device driver takes care of handling SPI_CS_HIGH
	 */
	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);

	ndelay(SPI_BITBANG_CS_DELAY);
	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
			    BITBANG_CS_INACTIVE);
	ndelay(SPI_BITBANG_CS_DELAY);
}

/*----------------------------------------------------------------------*/

int spi_bitbang_init(struct spi_bitbang *bitbang)
{
	struct spi_master *master = bitbang->master;
	bool custom_cs;

	if (!master)
		return -EINVAL;
	/*
	 * We only need the chipselect callback if we are actually using it.
	 * If we just use GPIO descriptors, it is surplus. If the
	 * SPI_MASTER_GPIO_SS flag is set, we always need to call the
	 * driver-specific chipselect routine.
	 */
	custom_cs = (!master->use_gpio_descriptors ||
		     (master->flags & SPI_MASTER_GPIO_SS));

	if (custom_cs && !bitbang->chipselect)
		return -EINVAL;

	mutex_init(&bitbang->lock);

	if (!master->mode_bits)
		master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (master->transfer || master->transfer_one_message)
		return -EINVAL;

	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	master->transfer_one = spi_bitbang_transfer_one;
	/*
	 * When using GPIO descriptors, the ->set_cs() callback doesn't even
	 * get called unless SPI_MASTER_GPIO_SS is set.
	 */
	if (custom_cs)
		master->set_cs = spi_bitbang_set_cs;

	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!master->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			master->setup = spi_bitbang_setup;
			master->cleanup = spi_bitbang_cleanup;
		}
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_init);

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the master has
 * a transfer method, its final step should call spi_bitbang_transfer; or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_master, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 *
 * On success, this routine will take a reference to master. The caller is
 * responsible for calling spi_bitbang_stop() to decrement the reference and
 * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
 * leak.
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	struct spi_master *master = bitbang->master;
	int ret;

	ret = spi_bitbang_init(bitbang);
	if (ret)
		return ret;

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	ret = spi_register_master(spi_master_get(master));
	if (ret)
		spi_master_put(master);

	return ret;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/*
 * spi_bitbang_stop - stops the task providing spi communication
 */
void spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_master(bitbang->master);
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
9904f22a	2	/*
ca632f55	3	* polling/bitbanging SPI master controller driver utilities
9904f22a DB	4	*/
9904f22a DB	5
9904f22a DB	6	#include <linux/spinlock.h>
	7	#include <linux/workqueue.h>
	8	#include <linux/interrupt.h>
d7614de4	9	#include <linux/module.h>
9904f22a DB	10	#include <linux/delay.h>
	11	#include <linux/errno.h>
	12	#include <linux/platform_device.h>
5a0e3ad6	13	#include <linux/slab.h>
9904f22a DB	14
	15	#include <linux/spi/spi.h>
	16	#include <linux/spi/spi_bitbang.h>
	17
00376865 HK	18	#define SPI_BITBANG_CS_DELAY 100
00376865 HK	19
9904f22a DB	20
	21	/----------------------------------------------------------------------/
	22
	23	/*
	24	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	25	* Use this for GPIO or shift-register level hardware APIs.
	26	*
	27	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	28	* to glue code. These bitbang setup() and cleanup() routines are always
	29	* used, though maybe they're called from controller-aware code.
	30	*
03ddcbc5	31	* chipselect() and friends may use spi_device->controller_data and
9904f22a DB	32	* controller registers as appropriate.
	33	*
	34	*
	35	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	36	* which means you could use a bitbang driver either to get hardware
	37	* working quickly, or testing for differences that aren't speed related.
	38	*/
	39
	40	struct spi_bitbang_cs {
	41	unsigned nsecs; /* (clock cycle time)/2 */
	42	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
304d3436	43	u32 word, u8 bits, unsigned flags);
9904f22a DB	44	unsigned (txrx_bufs)(struct spi_device ,
	45	u32 (*txrx_word)(
	46	struct spi_device *spi,
	47	unsigned nsecs,
304d3436 LB	48	u32 word, u8 bits,
	49	unsigned flags),
	50	unsigned, struct spi_transfer *,
	51	unsigned);
9904f22a DB	52	};
	53
	54	static unsigned bitbang_txrx_8(
	55	struct spi_device *spi,
	56	u32 (txrx_word)(struct spi_device spi,
	57	unsigned nsecs,
304d3436 LB	58	u32 word, u8 bits,
304d3436 LB	59	unsigned flags),
9904f22a	60	unsigned ns,
304d3436 LB	61	struct spi_transfer *t,
304d3436 LB	62	unsigned flags
f96c19fa JF	63	)
f96c19fa JF	64	{
766ed704	65	unsigned bits = t->bits_per_word;
9904f22a DB	66	unsigned count = t->len;
	67	const u8 *tx = t->tx_buf;
	68	u8 *rx = t->rx_buf;
	69
	70	while (likely(count > 0)) {
	71	u8 word = 0;
	72
	73	if (tx)
	74	word = *tx++;
304d3436	75	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	76	if (rx)
	77	*rx++ = word;
	78	count -= 1;
	79	}
	80	return t->len - count;
	81	}
	82
	83	static unsigned bitbang_txrx_16(
	84	struct spi_device *spi,
	85	u32 (txrx_word)(struct spi_device spi,
	86	unsigned nsecs,
304d3436 LB	87	u32 word, u8 bits,
304d3436 LB	88	unsigned flags),
9904f22a	89	unsigned ns,
304d3436 LB	90	struct spi_transfer *t,
304d3436 LB	91	unsigned flags
f96c19fa JF	92	)
f96c19fa JF	93	{
766ed704	94	unsigned bits = t->bits_per_word;
9904f22a DB	95	unsigned count = t->len;
	96	const u16 *tx = t->tx_buf;
	97	u16 *rx = t->rx_buf;
	98
	99	while (likely(count > 1)) {
	100	u16 word = 0;
	101
	102	if (tx)
	103	word = *tx++;
304d3436	104	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	105	if (rx)
	106	*rx++ = word;
	107	count -= 2;
	108	}
	109	return t->len - count;
	110	}
	111
	112	static unsigned bitbang_txrx_32(
	113	struct spi_device *spi,
	114	u32 (txrx_word)(struct spi_device spi,
	115	unsigned nsecs,
304d3436 LB	116	u32 word, u8 bits,
304d3436 LB	117	unsigned flags),
9904f22a	118	unsigned ns,
304d3436 LB	119	struct spi_transfer *t,
304d3436 LB	120	unsigned flags
f96c19fa JF	121	)
f96c19fa JF	122	{
766ed704	123	unsigned bits = t->bits_per_word;
9904f22a DB	124	unsigned count = t->len;
	125	const u32 *tx = t->tx_buf;
	126	u32 *rx = t->rx_buf;
	127
	128	while (likely(count > 3)) {
	129	u32 word = 0;
	130
	131	if (tx)
	132	word = *tx++;
304d3436	133	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	134	if (rx)
	135	*rx++ = word;
	136	count -= 4;
	137	}
	138	return t->len - count;
	139	}
	140
ff9f4771	141	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	142	{
	143	struct spi_bitbang_cs *cs = spi->controller_state;
	144	u8 bits_per_word;
	145	u32 hz;
	146
	147	if (t) {
	148	bits_per_word = t->bits_per_word;
	149	hz = t->speed_hz;
	150	} else {
	151	bits_per_word = 0;
	152	hz = 0;
	153	}
	154
	155	/* spi_transfer level calls that work per-word */
	156	if (!bits_per_word)
	157	bits_per_word = spi->bits_per_word;
	158	if (bits_per_word <= 8)
	159	cs->txrx_bufs = bitbang_txrx_8;
	160	else if (bits_per_word <= 16)
	161	cs->txrx_bufs = bitbang_txrx_16;
	162	else if (bits_per_word <= 32)
	163	cs->txrx_bufs = bitbang_txrx_32;
	164	else
	165	return -EINVAL;
	166
	167	/* nsecs = (clock period)/2 */
	168	if (!hz)
	169	hz = spi->max_speed_hz;
1e316d75 DB	170	if (hz) {
	171	cs->nsecs = (1000000000/2) / hz;
	172	if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
	173	return -EINVAL;
	174	}
4cff33f9 ID	175
	176	return 0;
	177	}
ff9f4771	178	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	179
c13b5044	180	/*
9904f22a DB	181	* spi_bitbang_setup - default setup for per-word I/O loops
	182	*/
	183	int spi_bitbang_setup(struct spi_device *spi)
	184	{
	185	struct spi_bitbang_cs *cs = spi->controller_state;
	186	struct spi_bitbang *bitbang;
	187
ccf77cc4 DB	188	bitbang = spi_master_get_devdata(spi->master);
ccf77cc4 DB	189
9904f22a	190	if (!cs) {
cff93c58	191	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
9904f22a DB	192	if (!cs)
	193	return -ENOMEM;
	194	spi->controller_state = cs;
	195	}
9904f22a	196
9904f22a DB	197	/* per-word shift register access, in hardware or bitbanging */
	198	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
	199	if (!cs->txrx_word)
	200	return -EINVAL;
	201
7d0ec8b6 PN	202	if (bitbang->setup_transfer) {
	203	int retval = bitbang->setup_transfer(spi, NULL);
	204	if (retval < 0)
	205	return retval;
	206	}
9904f22a	207
7d077197	208	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a	209
9904f22a DB	210	return 0;
	211	}
	212	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	213
c13b5044	214	/*
9904f22a DB	215	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
9904f22a DB	216	*/
0ffa0285	217	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	218	{
	219	kfree(spi->controller_state);
	220	}
	221	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	222
	223	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	224	{
	225	struct spi_bitbang_cs *cs = spi->controller_state;
	226	unsigned nsecs = cs->nsecs;
4b859db2 LB	227	struct spi_bitbang *bitbang;
	228
	229	bitbang = spi_master_get_devdata(spi->master);
	230	if (bitbang->set_line_direction) {
	231	int err;
9904f22a	232
4b859db2 LB	233	err = bitbang->set_line_direction(spi, !!(t->tx_buf));
	234	if (err < 0)
	235	return err;
	236	}
	237
	238	if (spi->mode & SPI_3WIRE) {
	239	unsigned flags;
	240
	241	flags = t->tx_buf ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX;
	242	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
	243	}
304d3436	244	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
9904f22a DB	245	}
	246
	247	/----------------------------------------------------------------------/
	248
	249	/*
	250	* SECOND PART ... simple transfer queue runner.
	251	*
	252	* This costs a task context per controller, running the queue by
	253	* performing each transfer in sequence. Smarter hardware can queue
	254	* several DMA transfers at once, and process several controller queues
	255	* in parallel; this driver doesn't match such hardware very well.
	256	*
	257	* Drivers can provide word-at-a-time i/o primitives, or provide
	258	* transfer-at-a-time ones to leverage dma or fifo hardware.
	259	*/
2025172e MB	260
	261	static int spi_bitbang_prepare_hardware(struct spi_master *spi)
	262	{
cff93c58	263	struct spi_bitbang *bitbang;
2025172e MB	264
	265	bitbang = spi_master_get_devdata(spi);
	266
c15f6ed3	267	mutex_lock(&bitbang->lock);
2025172e	268	bitbang->busy = 1;
c15f6ed3	269	mutex_unlock(&bitbang->lock);
2025172e MB	270
	271	return 0;
	272	}
	273
d60990d5	274	static int spi_bitbang_transfer_one(struct spi_master *master,
00376865 HK	275	struct spi_device *spi,
00376865 HK	276	struct spi_transfer *transfer)
9904f22a	277	{
00376865 HK	278	struct spi_bitbang *bitbang = spi_master_get_devdata(master);
00376865 HK	279	int status = 0;
91b30858	280
00376865 HK	281	if (bitbang->setup_transfer) {
	282	status = bitbang->setup_transfer(spi, transfer);
	283	if (status < 0)
	284	goto out;
91b30858 MB	285	}
91b30858 MB	286
00376865 HK	287	if (transfer->len)
00376865 HK	288	status = bitbang->txrx_bufs(spi, transfer);
91b30858	289
00376865 HK	290	if (status == transfer->len)
	291	status = 0;
	292	else if (status >= 0)
	293	status = -EREMOTEIO;
91b30858	294
00376865 HK	295	out:
00376865 HK	296	spi_finalize_current_transfer(master);
9904f22a	297
2025172e	298	return status;
9904f22a DB	299	}
9904f22a DB	300
2025172e	301	static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
9904f22a	302	{
cff93c58	303	struct spi_bitbang *bitbang;
9904f22a	304
2025172e	305	bitbang = spi_master_get_devdata(spi);
9904f22a	306
c15f6ed3	307	mutex_lock(&bitbang->lock);
2025172e	308	bitbang->busy = 0;
c15f6ed3	309	mutex_unlock(&bitbang->lock);
9904f22a	310
2025172e	311	return 0;
9904f22a	312	}
9904f22a	313
00376865 HK	314	static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
	315	{
	316	struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);
	317
	318	/* SPI core provides CS high / low, but bitbang driver
	319	* expects CS active
	320	* spi device driver takes care of handling SPI_CS_HIGH
	321	*/
	322	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
	323
	324	ndelay(SPI_BITBANG_CS_DELAY);
	325	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
	326	BITBANG_CS_INACTIVE);
	327	ndelay(SPI_BITBANG_CS_DELAY);
	328	}
	329
9904f22a DB	330	/----------------------------------------------------------------------/
9904f22a DB	331
45beec35 AS	332	int spi_bitbang_init(struct spi_bitbang *bitbang)
	333	{
	334	struct spi_master *master = bitbang->master;
4a07b8bc	335	bool custom_cs;
45beec35	336
4a07b8bc LW	337	if (!master)
	338	return -EINVAL;
	339	/*
	340	* We only need the chipselect callback if we are actually using it.
	341	* If we just use GPIO descriptors, it is surplus. If the
	342	* SPI_MASTER_GPIO_SS flag is set, we always need to call the
	343	* driver-specific chipselect routine.
	344	*/
	345	custom_cs = (!master->use_gpio_descriptors \|\|
	346	(master->flags & SPI_MASTER_GPIO_SS));
	347
	348	if (custom_cs && !bitbang->chipselect)
45beec35 AS	349	return -EINVAL;
	350
	351	mutex_init(&bitbang->lock);
	352
	353	if (!master->mode_bits)
	354	master->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
	355
	356	if (master->transfer \|\| master->transfer_one_message)
	357	return -EINVAL;
	358
	359	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	360	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	361	master->transfer_one = spi_bitbang_transfer_one;
4a07b8bc LW	362	/*
	363	* When using GPIO descriptors, the ->set_cs() callback doesn't even
	364	* get called unless SPI_MASTER_GPIO_SS is set.
	365	*/
	366	if (custom_cs)
	367	master->set_cs = spi_bitbang_set_cs;
45beec35 AS	368
	369	if (!bitbang->txrx_bufs) {
	370	bitbang->use_dma = 0;
	371	bitbang->txrx_bufs = spi_bitbang_bufs;
	372	if (!master->setup) {
	373	if (!bitbang->setup_transfer)
	374	bitbang->setup_transfer =
	375	spi_bitbang_setup_transfer;
	376	master->setup = spi_bitbang_setup;
	377	master->cleanup = spi_bitbang_cleanup;
	378	}
	379	}
	380
	381	return 0;
	382	}
	383	EXPORT_SYMBOL_GPL(spi_bitbang_init);
	384
9904f22a DB	385	/**
	386	* spi_bitbang_start - start up a polled/bitbanging SPI master driver
	387	* @bitbang: driver handle
	388	*
	389	* Caller should have zero-initialized all parts of the structure, and then
	390	* provided callbacks for chip selection and I/O loops. If the master has
	391	* a transfer method, its final step should call spi_bitbang_transfer; or,
	392	* that's the default if the transfer routine is not initialized. It should
	393	* also set up the bus number and number of chipselects.
	394	*
	395	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	396	* hardware that basically exposes a shift register) or per-spi_transfer
	397	* (which takes better advantage of hardware like fifos or DMA engines).
	398	*
7f8c7619 HPN	399	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
	400	* spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
	401	* master methods. Those methods are the defaults if the bitbang->txrx_bufs
	402	* routine isn't initialized.
9904f22a DB	403	*
	404	* This routine registers the spi_master, which will process requests in a
	405	* dedicated task, keeping IRQs unblocked most of the time. To stop
	406	* processing those requests, call spi_bitbang_stop().
702a4879 AL	407	*
	408	* On success, this routine will take a reference to master. The caller is
	409	* responsible for calling spi_bitbang_stop() to decrement the reference and
	410	* spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
	411	* leak.
9904f22a DB	412	*/
	413	int spi_bitbang_start(struct spi_bitbang *bitbang)
	414	{
7a5d8ca1	415	struct spi_master *master = bitbang->master;
702a4879	416	int ret;
9904f22a	417
45beec35 AS	418	ret = spi_bitbang_init(bitbang);
	419	if (ret)
	420	return ret;
9904f22a DB	421
	422	/* driver may get busy before register() returns, especially
	423	* if someone registered boardinfo for devices
	424	*/
702a4879 AL	425	ret = spi_register_master(spi_master_get(master));
	426	if (ret)
	427	spi_master_put(master);
	428
5caaf29a	429	return ret;
9904f22a DB	430	}
	431	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	432
c13b5044	433	/*
9904f22a DB	434	* spi_bitbang_stop - stops the task providing spi communication
9904f22a DB	435	*/
d9721ae1	436	void spi_bitbang_stop(struct spi_bitbang *bitbang)
9904f22a	437	{
a836f585	438	spi_unregister_master(bitbang->master);
9904f22a DB	439	}
	440	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	441
	442	MODULE_LICENSE("GPL");
	443