[linux-block.git] / drivers / spi / spi-bcm63xx.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>

/* BCM 6338/6348 SPI core */
#define SPI_6348_RSET_SIZE		64
#define SPI_6348_CMD			0x00	/* 16-bits register */
#define SPI_6348_INT_STATUS		0x02
#define SPI_6348_INT_MASK_ST		0x03
#define SPI_6348_INT_MASK		0x04
#define SPI_6348_ST			0x05
#define SPI_6348_CLK_CFG		0x06
#define SPI_6348_FILL_BYTE		0x07
#define SPI_6348_MSG_TAIL		0x09
#define SPI_6348_RX_TAIL		0x0b
#define SPI_6348_MSG_CTL		0x40	/* 8-bits register */
#define SPI_6348_MSG_CTL_WIDTH		8
#define SPI_6348_MSG_DATA		0x41
#define SPI_6348_MSG_DATA_SIZE		0x3f
#define SPI_6348_RX_DATA		0x80
#define SPI_6348_RX_DATA_SIZE		0x3f

/* BCM 3368/6358/6262/6368 SPI core */
#define SPI_6358_RSET_SIZE		1804
#define SPI_6358_MSG_CTL		0x00	/* 16-bits register */
#define SPI_6358_MSG_CTL_WIDTH		16
#define SPI_6358_MSG_DATA		0x02
#define SPI_6358_MSG_DATA_SIZE		0x21e
#define SPI_6358_RX_DATA		0x400
#define SPI_6358_RX_DATA_SIZE		0x220
#define SPI_6358_CMD			0x700	/* 16-bits register */
#define SPI_6358_INT_STATUS		0x702
#define SPI_6358_INT_MASK_ST		0x703
#define SPI_6358_INT_MASK		0x704
#define SPI_6358_ST			0x705
#define SPI_6358_CLK_CFG		0x706
#define SPI_6358_FILL_BYTE		0x707
#define SPI_6358_MSG_TAIL		0x709
#define SPI_6358_RX_TAIL		0x70B

/* Shared SPI definitions */

/* Message configuration */
#define SPI_FD_RW			0x00
#define SPI_HD_W			0x01
#define SPI_HD_R			0x02
#define SPI_BYTE_CNT_SHIFT		0
#define SPI_6348_MSG_TYPE_SHIFT		6
#define SPI_6358_MSG_TYPE_SHIFT		14

/* Command */
#define SPI_CMD_NOOP			0x00
#define SPI_CMD_SOFT_RESET		0x01
#define SPI_CMD_HARD_RESET		0x02
#define SPI_CMD_START_IMMEDIATE		0x03
#define SPI_CMD_COMMAND_SHIFT		0
#define SPI_CMD_COMMAND_MASK		0x000f
#define SPI_CMD_DEVICE_ID_SHIFT		4
#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT	8
#define SPI_CMD_ONE_BYTE_SHIFT		11
#define SPI_CMD_ONE_WIRE_SHIFT		12
#define SPI_DEV_ID_0			0
#define SPI_DEV_ID_1			1
#define SPI_DEV_ID_2			2
#define SPI_DEV_ID_3			3

/* Interrupt mask */
#define SPI_INTR_CMD_DONE		0x01
#define SPI_INTR_RX_OVERFLOW		0x02
#define SPI_INTR_TX_UNDERFLOW		0x04
#define SPI_INTR_TX_OVERFLOW		0x08
#define SPI_INTR_RX_UNDERFLOW		0x10
#define SPI_INTR_CLEAR_ALL		0x1f

/* Status */
#define SPI_RX_EMPTY			0x02
#define SPI_CMD_BUSY			0x04
#define SPI_SERIAL_BUSY			0x08

/* Clock configuration */
#define SPI_CLK_20MHZ			0x00
#define SPI_CLK_0_391MHZ		0x01
#define SPI_CLK_0_781MHZ		0x02	/* default */
#define SPI_CLK_1_563MHZ		0x03
#define SPI_CLK_3_125MHZ		0x04
#define SPI_CLK_6_250MHZ		0x05
#define SPI_CLK_12_50MHZ		0x06
#define SPI_CLK_MASK			0x07
#define SPI_SSOFFTIME_MASK		0x38
#define SPI_SSOFFTIME_SHIFT		3
#define SPI_BYTE_SWAP			0x80

enum bcm63xx_regs_spi {
	SPI_CMD,
	SPI_INT_STATUS,
	SPI_INT_MASK_ST,
	SPI_INT_MASK,
	SPI_ST,
	SPI_CLK_CFG,
	SPI_FILL_BYTE,
	SPI_MSG_TAIL,
	SPI_RX_TAIL,
	SPI_MSG_CTL,
	SPI_MSG_DATA,
	SPI_RX_DATA,
	SPI_MSG_TYPE_SHIFT,
	SPI_MSG_CTL_WIDTH,
	SPI_MSG_DATA_SIZE,
};

#define BCM63XX_SPI_MAX_PREPEND		15

#define BCM63XX_SPI_MAX_CS		8
#define BCM63XX_SPI_BUS_NUM		0

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	const unsigned long	*reg_offsets;
	unsigned int		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
			       unsigned int offset)
{
	return readb(bs->regs + bs->reg_offsets[offset]);
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
#ifdef CONFIG_CPU_BIG_ENDIAN
	return ioread16be(bs->regs + bs->reg_offsets[offset]);
#else
	return readw(bs->regs + bs->reg_offsets[offset]);
#endif
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	writeb(value, bs->regs + bs->reg_offsets[offset]);
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
#ifdef CONFIG_CPU_BIG_ENDIAN
	iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
#else
	writew(value, bs->regs + bs->reg_offsets[offset]);
#endif
}

static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u8 clk_cfg, reg;
	int i;

	/* Default to lowest clock configuration */
	clk_cfg = SPI_CLK_0_391MHZ;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, t->speed_hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
				unsigned int num_transfers)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;
	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	struct spi_transfer *t = first;
	bool do_rx = false;
	bool do_tx = false;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
		prepend_len = t->len;

	/* prepare the buffer */
	for (i = 0; i < num_transfers; i++) {
		if (t->tx_buf) {
			do_tx = true;
			memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);

			/* don't prepend more than one tx */
			if (t != first)
				prepend_len = 0;
		}

		if (t->rx_buf) {
			do_rx = true;
			/* prepend is half-duplex write only */
			if (t == first)
				prepend_len = 0;
		}

		len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	reinit_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);

	if (do_rx && do_tx && prepend_len == 0)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (do_rx)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (do_tx)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	timeout = wait_for_completion_timeout(&bs->done, HZ);
	if (!timeout)
		return -ETIMEDOUT;

	if (!do_rx)
		return 0;

	len = 0;
	t = first;
	/* Read out all the data */
	for (i = 0; i < num_transfers; i++) {
		if (t->rx_buf)
			memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);

		if (t != first || prepend_len == 0)
			len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t, *first = NULL;
	struct spi_device *spi = m->spi;
	int status = 0;
	unsigned int n_transfers = 0, total_len = 0;
	bool can_use_prepend = false;

	/*
	 * This SPI controller does not support keeping CS active after a
	 * transfer.
	 * Work around this by merging as many transfers we can into one big
	 * full-duplex transfers.
	 */
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (!first)
			first = t;

		n_transfers++;
		total_len += t->len;

		if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
		    first->len <= BCM63XX_SPI_MAX_PREPEND)
			can_use_prepend = true;
		else if (can_use_prepend && t->tx_buf)
			can_use_prepend = false;

		/* we can only transfer one fifo worth of data */
		if ((can_use_prepend &&
		     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
		    (!can_use_prepend && total_len > bs->fifo_size)) {
			dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
				total_len, bs->fifo_size);
			status = -EINVAL;
			goto exit;
		}

		/* all combined transfers have to have the same speed */
		if (t->speed_hz != first->speed_hz) {
			dev_err(&spi->dev, "unable to change speed between transfers\n");
			status = -EINVAL;
			goto exit;
		}

		/* CS will be deasserted directly after transfer */
		if (t->delay_usecs) {
			dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
			status = -EINVAL;
			goto exit;
		}

		if (t->cs_change ||
		    list_is_last(&t->transfer_list, &m->transfers)) {
			/* configure adapter for a new transfer */
			bcm63xx_spi_setup_transfer(spi, first);

			/* send the data */
			status = bcm63xx_txrx_bufs(spi, first, n_transfers);
			if (status)
				goto exit;

			m->actual_length += total_len;

			first = NULL;
			n_transfers = 0;
			total_len = 0;
			can_use_prepend = false;
		}
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}

static size_t bcm63xx_spi_max_length(struct spi_device *spi)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);

	return bs->fifo_size;
}

static const unsigned long bcm6348_spi_reg_offsets[] = {
	[SPI_CMD]		= SPI_6348_CMD,
	[SPI_INT_STATUS]	= SPI_6348_INT_STATUS,
	[SPI_INT_MASK_ST]	= SPI_6348_INT_MASK_ST,
	[SPI_INT_MASK]		= SPI_6348_INT_MASK,
	[SPI_ST]		= SPI_6348_ST,
	[SPI_CLK_CFG]		= SPI_6348_CLK_CFG,
	[SPI_FILL_BYTE]		= SPI_6348_FILL_BYTE,
	[SPI_MSG_TAIL]		= SPI_6348_MSG_TAIL,
	[SPI_RX_TAIL]		= SPI_6348_RX_TAIL,
	[SPI_MSG_CTL]		= SPI_6348_MSG_CTL,
	[SPI_MSG_DATA]		= SPI_6348_MSG_DATA,
	[SPI_RX_DATA]		= SPI_6348_RX_DATA,
	[SPI_MSG_TYPE_SHIFT]	= SPI_6348_MSG_TYPE_SHIFT,
	[SPI_MSG_CTL_WIDTH]	= SPI_6348_MSG_CTL_WIDTH,
	[SPI_MSG_DATA_SIZE]	= SPI_6348_MSG_DATA_SIZE,
};

static const unsigned long bcm6358_spi_reg_offsets[] = {
	[SPI_CMD]		= SPI_6358_CMD,
	[SPI_INT_STATUS]	= SPI_6358_INT_STATUS,
	[SPI_INT_MASK_ST]	= SPI_6358_INT_MASK_ST,
	[SPI_INT_MASK]		= SPI_6358_INT_MASK,
	[SPI_ST]		= SPI_6358_ST,
	[SPI_CLK_CFG]		= SPI_6358_CLK_CFG,
	[SPI_FILL_BYTE]		= SPI_6358_FILL_BYTE,
	[SPI_MSG_TAIL]		= SPI_6358_MSG_TAIL,
	[SPI_RX_TAIL]		= SPI_6358_RX_TAIL,
	[SPI_MSG_CTL]		= SPI_6358_MSG_CTL,
	[SPI_MSG_DATA]		= SPI_6358_MSG_DATA,
	[SPI_RX_DATA]		= SPI_6358_RX_DATA,
	[SPI_MSG_TYPE_SHIFT]	= SPI_6358_MSG_TYPE_SHIFT,
	[SPI_MSG_CTL_WIDTH]	= SPI_6358_MSG_CTL_WIDTH,
	[SPI_MSG_DATA_SIZE]	= SPI_6358_MSG_DATA_SIZE,
};

static const struct platform_device_id bcm63xx_spi_dev_match[] = {
	{
		.name = "bcm6348-spi",
		.driver_data = (unsigned long)bcm6348_spi_reg_offsets,
	},
	{
		.name = "bcm6358-spi",
		.driver_data = (unsigned long)bcm6358_spi_reg_offsets,
	},
	{
	},
};

static const struct of_device_id bcm63xx_spi_of_match[] = {
	{ .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
	{ .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
	{ },
};

static int bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	const unsigned long *bcm63xx_spireg;
	struct device *dev = &pdev->dev;
	int irq, bus_num;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;
	u32 num_cs = BCM63XX_SPI_MAX_CS;

	if (dev->of_node) {
		const struct of_device_id *match;

		match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
		if (!match)
			return -EINVAL;
		bcm63xx_spireg = match->data;

		of_property_read_u32(dev->of_node, "num-cs", &num_cs);
		if (num_cs > BCM63XX_SPI_MAX_CS) {
			dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
				 num_cs);
			num_cs = BCM63XX_SPI_MAX_CS;
		}

		bus_num = -1;
	} else if (pdev->id_entry->driver_data) {
		const struct platform_device_id *match = pdev->id_entry;

		bcm63xx_spireg = (const unsigned long *)match->driver_data;
		bus_num = BCM63XX_SPI_BUS_NUM;
	} else {
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq: %d\n", irq);
		return irq;
	}

	clk = devm_clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		return PTR_ERR(clk);
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		return -ENOMEM;
	}

	bs = spi_master_get_devdata(master);
	init_completion(&bs->done);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(bs->regs)) {
		ret = PTR_ERR(bs->regs);
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->reg_offsets = bcm63xx_spireg;
	bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->dev.of_node = dev->of_node;
	master->bus_num = bus_num;
	master->num_chipselect = num_cs;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->max_transfer_size = bcm63xx_spi_max_length;
	master->max_message_size = bcm63xx_spi_max_length;
	master->auto_runtime_pm = true;
	bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
	bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
	bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
	bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);

	/* Initialize hardware */
	ret = clk_prepare_enable(bs->clk);
	if (ret)
		goto out_err;

	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
		 r, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable_unprepare(clk);
out_err:
	spi_master_put(master);
	return ret;
}

static int bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	spi_master_resume(master);

	return 0;
}
#endif

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
};

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.pm	= &bcm63xx_spi_pm_ops,
		.of_match_table = bcm63xx_spi_of_match,
	},
	.id_table	= bcm63xx_spi_dev_match,
	.probe		= bcm63xx_spi_probe,
	.remove		= bcm63xx_spi_remove,
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
b42dfed8 FF	2	/*
	3	* Broadcom BCM63xx SPI controller support
	4	*
cde4384e	5	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8	6	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
b42dfed8 FF	7	*/
	8
	9	#include <linux/kernel.h>
b42dfed8 FF	10	#include <linux/clk.h>
	11	#include <linux/io.h>
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/delay.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/spi/spi.h>
	17	#include <linux/completion.h>
	18	#include <linux/err.h>
cde4384e	19	#include <linux/pm_runtime.h>
c29f0889	20	#include <linux/of.h>
b42dfed8	21
44d8fb30 JG	22	/* BCM 6338/6348 SPI core */
	23	#define SPI_6348_RSET_SIZE 64
	24	#define SPI_6348_CMD 0x00 /* 16-bits register */
	25	#define SPI_6348_INT_STATUS 0x02
	26	#define SPI_6348_INT_MASK_ST 0x03
	27	#define SPI_6348_INT_MASK 0x04
	28	#define SPI_6348_ST 0x05
	29	#define SPI_6348_CLK_CFG 0x06
	30	#define SPI_6348_FILL_BYTE 0x07
	31	#define SPI_6348_MSG_TAIL 0x09
	32	#define SPI_6348_RX_TAIL 0x0b
	33	#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
	34	#define SPI_6348_MSG_CTL_WIDTH 8
	35	#define SPI_6348_MSG_DATA 0x41
	36	#define SPI_6348_MSG_DATA_SIZE 0x3f
	37	#define SPI_6348_RX_DATA 0x80
	38	#define SPI_6348_RX_DATA_SIZE 0x3f
	39
	40	/* BCM 3368/6358/6262/6368 SPI core */
	41	#define SPI_6358_RSET_SIZE 1804
	42	#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
	43	#define SPI_6358_MSG_CTL_WIDTH 16
	44	#define SPI_6358_MSG_DATA 0x02
	45	#define SPI_6358_MSG_DATA_SIZE 0x21e
	46	#define SPI_6358_RX_DATA 0x400
	47	#define SPI_6358_RX_DATA_SIZE 0x220
	48	#define SPI_6358_CMD 0x700 /* 16-bits register */
	49	#define SPI_6358_INT_STATUS 0x702
	50	#define SPI_6358_INT_MASK_ST 0x703
	51	#define SPI_6358_INT_MASK 0x704
	52	#define SPI_6358_ST 0x705
	53	#define SPI_6358_CLK_CFG 0x706
	54	#define SPI_6358_FILL_BYTE 0x707
	55	#define SPI_6358_MSG_TAIL 0x709
	56	#define SPI_6358_RX_TAIL 0x70B
	57
	58	/* Shared SPI definitions */
	59
	60	/* Message configuration */
	61	#define SPI_FD_RW 0x00
	62	#define SPI_HD_W 0x01
	63	#define SPI_HD_R 0x02
	64	#define SPI_BYTE_CNT_SHIFT 0
	65	#define SPI_6348_MSG_TYPE_SHIFT 6
	66	#define SPI_6358_MSG_TYPE_SHIFT 14
	67
	68	/* Command */
	69	#define SPI_CMD_NOOP 0x00
	70	#define SPI_CMD_SOFT_RESET 0x01
	71	#define SPI_CMD_HARD_RESET 0x02
	72	#define SPI_CMD_START_IMMEDIATE 0x03
	73	#define SPI_CMD_COMMAND_SHIFT 0
	74	#define SPI_CMD_COMMAND_MASK 0x000f
	75	#define SPI_CMD_DEVICE_ID_SHIFT 4
	76	#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
	77	#define SPI_CMD_ONE_BYTE_SHIFT 11
	78	#define SPI_CMD_ONE_WIRE_SHIFT 12
	79	#define SPI_DEV_ID_0 0
	80	#define SPI_DEV_ID_1 1
	81	#define SPI_DEV_ID_2 2
	82	#define SPI_DEV_ID_3 3
	83
	84	/* Interrupt mask */
	85	#define SPI_INTR_CMD_DONE 0x01
86	#define SPI_INTR_RX_OVERFLOW 0x02
87	#define SPI_INTR_TX_UNDERFLOW 0x04
88	#define SPI_INTR_TX_OVERFLOW 0x08
89	#define SPI_INTR_RX_UNDERFLOW 0x10
90	#define SPI_INTR_CLEAR_ALL 0x1f
91
92	/* Status */
93	#define SPI_RX_EMPTY 0x02
94	#define SPI_CMD_BUSY 0x04
95	#define SPI_SERIAL_BUSY 0x08
96
97	/* Clock configuration */
98	#define SPI_CLK_20MHZ 0x00
99	#define SPI_CLK_0_391MHZ 0x01
100	#define SPI_CLK_0_781MHZ 0x02 /* default */
101	#define SPI_CLK_1_563MHZ 0x03
102	#define SPI_CLK_3_125MHZ 0x04
103	#define SPI_CLK_6_250MHZ 0x05
104	#define SPI_CLK_12_50MHZ 0x06
105	#define SPI_CLK_MASK 0x07
106	#define SPI_SSOFFTIME_MASK 0x38
107	#define SPI_SSOFFTIME_SHIFT 3
108	#define SPI_BYTE_SWAP 0x80
109
110	enum bcm63xx_regs_spi {
111	SPI_CMD,
112	SPI_INT_STATUS,
113	SPI_INT_MASK_ST,
114	SPI_INT_MASK,
115	SPI_ST,
116	SPI_CLK_CFG,
117	SPI_FILL_BYTE,
118	SPI_MSG_TAIL,
119	SPI_RX_TAIL,
120	SPI_MSG_CTL,
121	SPI_MSG_DATA,
122	SPI_RX_DATA,
123	SPI_MSG_TYPE_SHIFT,
124	SPI_MSG_CTL_WIDTH,
125	SPI_MSG_DATA_SIZE,
126	};
b42dfed8	127
b17de076 JG	128	#define BCM63XX_SPI_MAX_PREPEND 15
b17de076 JG	129
65059997	130	#define BCM63XX_SPI_MAX_CS 8
a45fcea5	131	#define BCM63XX_SPI_BUS_NUM 0
65059997	132
b42dfed8	133	struct bcm63xx_spi {
b42dfed8 FF	134	struct completion done;
	135
	136	void __iomem *regs;
	137	int irq;
	138
	139	/* Platform data */
44d8fb30	140	const unsigned long *reg_offsets;
b85d65dd	141	unsigned int fifo_size;
5a670445 FF	142	unsigned int msg_type_shift;
5a670445 FF	143	unsigned int msg_ctl_width;
b42dfed8	144
b42dfed8 FF	145	/* data iomem */
	146	u8 __iomem *tx_io;
	147	const u8 __iomem *rx_io;
	148
b42dfed8 FF	149	struct clk *clk;
	150	struct platform_device *pdev;
	151	};
	152
	153	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
44d8fb30	154	unsigned int offset)
b42dfed8	155	{
44d8fb30	156	return readb(bs->regs + bs->reg_offsets[offset]);
b42dfed8 FF	157	}
	158
	159	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	160	unsigned int offset)
	161	{
682b5280	162	#ifdef CONFIG_CPU_BIG_ENDIAN
44d8fb30	163	return ioread16be(bs->regs + bs->reg_offsets[offset]);
158fcc4e	164	#else
44d8fb30	165	return readw(bs->regs + bs->reg_offsets[offset]);
158fcc4e	166	#endif
b42dfed8 FF	167	}
	168
	169	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	170	u8 value, unsigned int offset)
	171	{
44d8fb30	172	writeb(value, bs->regs + bs->reg_offsets[offset]);
b42dfed8 FF	173	}
	174
	175	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	176	u16 value, unsigned int offset)
	177	{
682b5280	178	#ifdef CONFIG_CPU_BIG_ENDIAN
44d8fb30	179	iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
158fcc4e	180	#else
44d8fb30	181	writew(value, bs->regs + bs->reg_offsets[offset]);
158fcc4e	182	#endif
b42dfed8 FF	183	}
b42dfed8 FF	184
b85d65dd	185	static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
b42dfed8 FF	186	{ 20000000, SPI_CLK_20MHZ },
	187	{ 12500000, SPI_CLK_12_50MHZ },
	188	{ 6250000, SPI_CLK_6_250MHZ },
	189	{ 3125000, SPI_CLK_3_125MHZ },
	190	{ 1563000, SPI_CLK_1_563MHZ },
	191	{ 781000, SPI_CLK_0_781MHZ },
	192	{ 391000, SPI_CLK_0_391MHZ }
	193	};
	194
cde4384e FF	195	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	196	struct spi_transfer *t)
	197	{
	198	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
cde4384e FF	199	u8 clk_cfg, reg;
	200	int i;
	201
4dde99bd GU	202	/* Default to lowest clock configuration */
	203	clk_cfg = SPI_CLK_0_391MHZ;
	204
b42dfed8 FF	205	/* Find the closest clock configuration */
b42dfed8 FF	206	for (i = 0; i < SPI_CLK_MASK; i++) {
68792e2a	207	if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	208	clk_cfg = bcm63xx_spi_freq_table[i][1];
	209	break;
	210	}
	211	}
	212
b42dfed8 FF	213	/* clear existing clock configuration bits of the register */
	214	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	215	reg &= ~SPI_CLK_MASK;
	216	reg \|= clk_cfg;
	217
	218	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	219	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
68792e2a	220	clk_cfg, t->speed_hz);
b42dfed8 FF	221	}
	222
	223	/* the spi->mode bits understood by this driver: */
	224	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	225
b17de076 JG	226	static int bcm63xx_txrx_bufs(struct spi_device spi, struct spi_transfer first,
b17de076 JG	227	unsigned int num_transfers)
b42dfed8 FF	228	{
	229	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	230	u16 msg_ctl;
	231	u16 cmd;
b17de076 JG	232	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	233	struct spi_transfer *t = first;
	234	bool do_rx = false;
	235	bool do_tx = false;
b42dfed8	236
cde4384e FF	237	/* Disable the CMD_DONE interrupt */
	238	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	239
b42dfed8 FF	240	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	241	t->tx_buf, t->rx_buf, t->len);
	242
b17de076 JG	243	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
	244	prepend_len = t->len;
	245
	246	/* prepare the buffer */
	247	for (i = 0; i < num_transfers; i++) {
	248	if (t->tx_buf) {
	249	do_tx = true;
	250	memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
	251
	252	/* don't prepend more than one tx */
	253	if (t != first)
	254	prepend_len = 0;
	255	}
	256
	257	if (t->rx_buf) {
	258	do_rx = true;
	259	/* prepend is half-duplex write only */
	260	if (t == first)
	261	prepend_len = 0;
	262	}
	263
	264	len += t->len;
	265
	266	t = list_entry(t->transfer_list.next, struct spi_transfer,
	267	transfer_list);
	268	}
	269
aa0fe826	270	reinit_completion(&bs->done);
b42dfed8 FF	271
b42dfed8 FF	272	/* Fill in the Message control register */
b17de076	273	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
b42dfed8	274
b17de076	275	if (do_rx && do_tx && prepend_len == 0)
5a670445	276	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b17de076	277	else if (do_rx)
5a670445	278	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b17de076	279	else if (do_tx)
5a670445 FF	280	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	281
	282	switch (bs->msg_ctl_width) {
	283	case 8:
	284	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	285	break;
	286	case 16:
	287	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	288	break;
	289	}
b42dfed8 FF	290
	291	/* Issue the transfer */
	292	cmd = SPI_CMD_START_IMMEDIATE;
b17de076	293	cmd \|= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
b42dfed8 FF	294	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
b42dfed8 FF	295	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	296
cde4384e FF	297	/* Enable the CMD_DONE interrupt */
cde4384e FF	298	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8	299
c0fde3ba JG	300	timeout = wait_for_completion_timeout(&bs->done, HZ);
	301	if (!timeout)
	302	return -ETIMEDOUT;
	303
20e9e78f	304	if (!do_rx)
b17de076 JG	305	return 0;
	306
	307	len = 0;
	308	t = first;
c0fde3ba	309	/* Read out all the data */
b17de076 JG	310	for (i = 0; i < num_transfers; i++) {
	311	if (t->rx_buf)
	312	memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
	313
	314	if (t != first \|\| prepend_len == 0)
	315	len += t->len;
	316
	317	t = list_entry(t->transfer_list.next, struct spi_transfer,
	318	transfer_list);
	319	}
c0fde3ba JG	320
c0fde3ba JG	321	return 0;
b42dfed8 FF	322	}
b42dfed8 FF	323
cde4384e FF	324	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	325	struct spi_message *m)
	326	{
	327	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b17de076	328	struct spi_transfer t, first = NULL;
cde4384e FF	329	struct spi_device *spi = m->spi;
cde4384e FF	330	int status = 0;
b17de076 JG	331	unsigned int n_transfers = 0, total_len = 0;
	332	bool can_use_prepend = false;
	333
	334	/*
	335	* This SPI controller does not support keeping CS active after a
	336	* transfer.
	337	* Work around this by merging as many transfers we can into one big
	338	* full-duplex transfers.
	339	*/
b42dfed8	340	list_for_each_entry(t, &m->transfers, transfer_list) {
b17de076 JG	341	if (!first)
	342	first = t;
	343
	344	n_transfers++;
	345	total_len += t->len;
	346
	347	if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
	348	first->len <= BCM63XX_SPI_MAX_PREPEND)
	349	can_use_prepend = true;
	350	else if (can_use_prepend && t->tx_buf)
	351	can_use_prepend = false;
	352
c0fde3ba	353	/* we can only transfer one fifo worth of data */
b17de076 JG	354	if ((can_use_prepend &&
	355	total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) \|\|
	356	(!can_use_prepend && total_len > bs->fifo_size)) {
c0fde3ba	357	dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
b17de076	358	total_len, bs->fifo_size);
c0fde3ba JG	359	status = -EINVAL;
	360	goto exit;
	361	}
cde4384e	362
b17de076 JG	363	/* all combined transfers have to have the same speed */
	364	if (t->speed_hz != first->speed_hz) {
	365	dev_err(&spi->dev, "unable to change speed between transfers\n");
c0fde3ba JG	366	status = -EINVAL;
	367	goto exit;
	368	}
cde4384e	369
b17de076 JG	370	/* CS will be deasserted directly after transfer */
	371	if (t->delay_usecs) {
	372	dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
c0fde3ba JG	373	status = -EINVAL;
	374	goto exit;
	375	}
cde4384e	376
b17de076 JG	377	if (t->cs_change \|\|
	378	list_is_last(&t->transfer_list, &m->transfers)) {
	379	/* configure adapter for a new transfer */
	380	bcm63xx_spi_setup_transfer(spi, first);
cde4384e	381
b17de076 JG	382	/* send the data */
	383	status = bcm63xx_txrx_bufs(spi, first, n_transfers);
	384	if (status)
	385	goto exit;
	386
	387	m->actual_length += total_len;
b42dfed8	388
b17de076 JG	389	first = NULL;
	390	n_transfers = 0;
	391	total_len = 0;
	392	can_use_prepend = false;
	393	}
cde4384e FF	394	}
	395	exit:
	396	m->status = status;
	397	spi_finalize_current_message(master);
b42dfed8	398
cde4384e	399	return 0;
b42dfed8 FF	400	}
	401
	402	/* This driver supports single master mode only. Hence
	403	* CMD_DONE is the only interrupt we care about
	404	*/
	405	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	406	{
	407	struct spi_master master = (struct spi_master )dev_id;
	408	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	409	u8 intr;
b42dfed8 FF	410
	411	/* Read interupts and clear them immediately */
	412	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	413	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	414	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	415
cde4384e FF	416	/* A transfer completed */
	417	if (intr & SPI_INTR_CMD_DONE)
	418	complete(&bs->done);
b42dfed8 FF	419
	420	return IRQ_HANDLED;
	421	}
	422
ccd0657c	423	static size_t bcm63xx_spi_max_length(struct spi_device *spi)
0135c03d JG	424	{
	425	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	426
	427	return bs->fifo_size;
	428	}
	429
44d8fb30 JG	430	static const unsigned long bcm6348_spi_reg_offsets[] = {
	431	[SPI_CMD] = SPI_6348_CMD,
	432	[SPI_INT_STATUS] = SPI_6348_INT_STATUS,
	433	[SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
	434	[SPI_INT_MASK] = SPI_6348_INT_MASK,
	435	[SPI_ST] = SPI_6348_ST,
	436	[SPI_CLK_CFG] = SPI_6348_CLK_CFG,
	437	[SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
	438	[SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
	439	[SPI_RX_TAIL] = SPI_6348_RX_TAIL,
	440	[SPI_MSG_CTL] = SPI_6348_MSG_CTL,
	441	[SPI_MSG_DATA] = SPI_6348_MSG_DATA,
	442	[SPI_RX_DATA] = SPI_6348_RX_DATA,
	443	[SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
	444	[SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
	445	[SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
	446	};
	447
	448	static const unsigned long bcm6358_spi_reg_offsets[] = {
	449	[SPI_CMD] = SPI_6358_CMD,
	450	[SPI_INT_STATUS] = SPI_6358_INT_STATUS,
	451	[SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
	452	[SPI_INT_MASK] = SPI_6358_INT_MASK,
	453	[SPI_ST] = SPI_6358_ST,
	454	[SPI_CLK_CFG] = SPI_6358_CLK_CFG,
	455	[SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
	456	[SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
	457	[SPI_RX_TAIL] = SPI_6358_RX_TAIL,
	458	[SPI_MSG_CTL] = SPI_6358_MSG_CTL,
	459	[SPI_MSG_DATA] = SPI_6358_MSG_DATA,
	460	[SPI_RX_DATA] = SPI_6358_RX_DATA,
	461	[SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
	462	[SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
	463	[SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
	464	};
	465
	466	static const struct platform_device_id bcm63xx_spi_dev_match[] = {
	467	{
	468	.name = "bcm6348-spi",
	469	.driver_data = (unsigned long)bcm6348_spi_reg_offsets,
	470	},
	471	{
	472	.name = "bcm6358-spi",
	473	.driver_data = (unsigned long)bcm6358_spi_reg_offsets,
	474	},
	475	{
	476	},
	477	};
b42dfed8	478
c29f0889 JG	479	static const struct of_device_id bcm63xx_spi_of_match[] = {
	480	{ .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
	481	{ .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
	482	{ },
	483	};
	484
fd4a319b	485	static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8 FF	486	{
b42dfed8 FF	487	struct resource *r;
44d8fb30	488	const unsigned long *bcm63xx_spireg;
b42dfed8	489	struct device *dev = &pdev->dev;
c29f0889	490	int irq, bus_num;
b42dfed8 FF	491	struct spi_master *master;
	492	struct clk *clk;
	493	struct bcm63xx_spi *bs;
	494	int ret;
c29f0889	495	u32 num_cs = BCM63XX_SPI_MAX_CS;
b42dfed8	496
c29f0889 JG	497	if (dev->of_node) {
c29f0889 JG	498	const struct of_device_id *match;
44d8fb30	499
c29f0889 JG	500	match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
	501	if (!match)
	502	return -EINVAL;
	503	bcm63xx_spireg = match->data;
	504
	505	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	506	if (num_cs > BCM63XX_SPI_MAX_CS) {
	507	dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
	508	num_cs);
	509	num_cs = BCM63XX_SPI_MAX_CS;
	510	}
	511
	512	bus_num = -1;
	513	} else if (pdev->id_entry->driver_data) {
	514	const struct platform_device_id *match = pdev->id_entry;
	515
	516	bcm63xx_spireg = (const unsigned long *)match->driver_data;
	517	bus_num = BCM63XX_SPI_BUS_NUM;
	518	} else {
	519	return -EINVAL;
	520	}
44d8fb30	521
b42dfed8 FF	522	irq = platform_get_irq(pdev, 0);
b42dfed8 FF	523	if (irq < 0) {
ba8afe94 GS	524	dev_err(dev, "no irq: %d\n", irq);
ba8afe94 GS	525	return irq;
b42dfed8 FF	526	}
b42dfed8 FF	527
acf4fc6f	528	clk = devm_clk_get(dev, "spi");
b42dfed8 FF	529	if (IS_ERR(clk)) {
b42dfed8 FF	530	dev_err(dev, "no clock for device\n");
acf4fc6f	531	return PTR_ERR(clk);
b42dfed8 FF	532	}
	533
	534	master = spi_alloc_master(dev, sizeof(*bs));
	535	if (!master) {
	536	dev_err(dev, "out of memory\n");
acf4fc6f	537	return -ENOMEM;
b42dfed8 FF	538	}
	539
	540	bs = spi_master_get_devdata(master);
aa0fe826	541	init_completion(&bs->done);
b42dfed8 FF	542
	543	platform_set_drvdata(pdev, master);
	544	bs->pdev = pdev;
	545
de0fa83c	546	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b66c7730 JG	547	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	548	if (IS_ERR(bs->regs)) {
	549	ret = PTR_ERR(bs->regs);
b42dfed8 FF	550	goto out_err;
	551	}
	552
	553	bs->irq = irq;
	554	bs->clk = clk;
44d8fb30 JG	555	bs->reg_offsets = bcm63xx_spireg;
44d8fb30 JG	556	bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
b42dfed8 FF	557
	558	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	559	pdev->name, master);
	560	if (ret) {
	561	dev_err(dev, "unable to request irq\n");
	562	goto out_err;
	563	}
	564
c29f0889 JG	565	master->dev.of_node = dev->of_node;
	566	master->bus_num = bus_num;
	567	master->num_chipselect = num_cs;
cde4384e	568	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	569	master->mode_bits = MODEBITS;
24778be2	570	master->bits_per_word_mask = SPI_BPW_MASK(8);
0135c03d JG	571	master->max_transfer_size = bcm63xx_spi_max_length;
0135c03d JG	572	master->max_message_size = bcm63xx_spi_max_length;
5355d96d	573	master->auto_runtime_pm = true;
44d8fb30 JG	574	bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
	575	bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
	576	bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
	577	bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
5a670445	578
b42dfed8	579	/* Initialize hardware */
ea01e8a4 JG	580	ret = clk_prepare_enable(bs->clk);
	581	if (ret)
	582	goto out_err;
	583
b42dfed8 FF	584	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	585
	586	/* register and we are done */
bca76931	587	ret = devm_spi_register_master(dev, master);
b42dfed8 FF	588	if (ret) {
	589	dev_err(dev, "spi register failed\n");
	590	goto out_clk_disable;
	591	}
	592
0ba2cf70 AB	593	dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
0ba2cf70 AB	594	r, irq, bs->fifo_size);
b42dfed8 FF	595
	596	return 0;
	597
	598	out_clk_disable:
4fbb82a7	599	clk_disable_unprepare(clk);
b42dfed8	600	out_err:
b42dfed8	601	spi_master_put(master);
b42dfed8 FF	602	return ret;
	603	}
	604
fd4a319b	605	static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8	606	{
9637b86f	607	struct spi_master *master = platform_get_drvdata(pdev);
b42dfed8 FF	608	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	609
	610	/* reset spi block */
	611	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	612
b42dfed8 FF	613	/* HW shutdown */
4fbb82a7	614	clk_disable_unprepare(bs->clk);
b42dfed8	615
b42dfed8 FF	616	return 0;
	617	}
	618
1bae2028	619	#ifdef CONFIG_PM_SLEEP
b42dfed8 FF	620	static int bcm63xx_spi_suspend(struct device *dev)
b42dfed8 FF	621	{
a1216394	622	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8 FF	623	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	624
96519957 FF	625	spi_master_suspend(master);
96519957 FF	626
4fbb82a7	627	clk_disable_unprepare(bs->clk);
b42dfed8 FF	628
	629	return 0;
	630	}
	631
	632	static int bcm63xx_spi_resume(struct device *dev)
	633	{
a1216394	634	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8	635	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
ea01e8a4	636	int ret;
b42dfed8	637
ea01e8a4 JG	638	ret = clk_prepare_enable(bs->clk);
	639	if (ret)
	640	return ret;
b42dfed8	641
96519957 FF	642	spi_master_resume(master);
96519957 FF	643
b42dfed8 FF	644	return 0;
b42dfed8 FF	645	}
1bae2028	646	#endif
b42dfed8 FF	647
b42dfed8 FF	648	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
1bae2028	649	SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
b42dfed8 FF	650	};
b42dfed8 FF	651
b42dfed8 FF	652	static struct platform_driver bcm63xx_spi_driver = {
	653	.driver = {
	654	.name = "bcm63xx-spi",
1bae2028	655	.pm = &bcm63xx_spi_pm_ops,
c29f0889	656	.of_match_table = bcm63xx_spi_of_match,
b42dfed8	657	},
44d8fb30	658	.id_table = bcm63xx_spi_dev_match,
b42dfed8	659	.probe = bcm63xx_spi_probe,
fd4a319b	660	.remove = bcm63xx_spi_remove,
b42dfed8 FF	661	};
	662
	663	module_platform_driver(bcm63xx_spi_driver);
	664
	665	MODULE_ALIAS("platform:bcm63xx_spi");
	666	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
	667	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
	668	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	669	MODULE_LICENSE("GPL");