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Merge tag 'pci-v5.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[linux-2.6-block.git] / drivers / spi / spi-bcm63xx.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
b42dfed8
FF		 2/*
3 * Broadcom BCM63xx SPI controller support
4 *
cde4384e 5 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8 6 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
b42dfed8
FF		 7 */
8
9#include <linux/kernel.h>
b42dfed8
FF		 10#include <linux/clk.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/spi/spi.h>
17#include <linux/completion.h>
18#include <linux/err.h>
cde4384e 19#include <linux/pm_runtime.h>
c29f0889 20#include <linux/of.h>
38807ade 21#include <linux/reset.h>
b42dfed8 22
44d8fb30
JG		 23/* BCM 6338/6348 SPI core */
24#define SPI_6348_RSET_SIZE 64
25#define SPI_6348_CMD 0x00 /* 16-bits register */
26#define SPI_6348_INT_STATUS 0x02
27#define SPI_6348_INT_MASK_ST 0x03
28#define SPI_6348_INT_MASK 0x04
29#define SPI_6348_ST 0x05
30#define SPI_6348_CLK_CFG 0x06
31#define SPI_6348_FILL_BYTE 0x07
32#define SPI_6348_MSG_TAIL 0x09
33#define SPI_6348_RX_TAIL 0x0b
34#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
35#define SPI_6348_MSG_CTL_WIDTH 8
36#define SPI_6348_MSG_DATA 0x41
37#define SPI_6348_MSG_DATA_SIZE 0x3f
38#define SPI_6348_RX_DATA 0x80
39#define SPI_6348_RX_DATA_SIZE 0x3f
40
41/* BCM 3368/6358/6262/6368 SPI core */
42#define SPI_6358_RSET_SIZE 1804
43#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
44#define SPI_6358_MSG_CTL_WIDTH 16
45#define SPI_6358_MSG_DATA 0x02
46#define SPI_6358_MSG_DATA_SIZE 0x21e
47#define SPI_6358_RX_DATA 0x400
48#define SPI_6358_RX_DATA_SIZE 0x220
49#define SPI_6358_CMD 0x700 /* 16-bits register */
50#define SPI_6358_INT_STATUS 0x702
51#define SPI_6358_INT_MASK_ST 0x703
52#define SPI_6358_INT_MASK 0x704
53#define SPI_6358_ST 0x705
54#define SPI_6358_CLK_CFG 0x706
55#define SPI_6358_FILL_BYTE 0x707
56#define SPI_6358_MSG_TAIL 0x709
57#define SPI_6358_RX_TAIL 0x70B
58
59/* Shared SPI definitions */
60
61/* Message configuration */
62#define SPI_FD_RW 0x00
63#define SPI_HD_W 0x01
64#define SPI_HD_R 0x02
65#define SPI_BYTE_CNT_SHIFT 0
66#define SPI_6348_MSG_TYPE_SHIFT 6
67#define SPI_6358_MSG_TYPE_SHIFT 14
68
69/* Command */
70#define SPI_CMD_NOOP 0x00
71#define SPI_CMD_SOFT_RESET 0x01
72#define SPI_CMD_HARD_RESET 0x02
73#define SPI_CMD_START_IMMEDIATE 0x03
74#define SPI_CMD_COMMAND_SHIFT 0
75#define SPI_CMD_COMMAND_MASK 0x000f
76#define SPI_CMD_DEVICE_ID_SHIFT 4
77#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
78#define SPI_CMD_ONE_BYTE_SHIFT 11
79#define SPI_CMD_ONE_WIRE_SHIFT 12
80#define SPI_DEV_ID_0 0
81#define SPI_DEV_ID_1 1
82#define SPI_DEV_ID_2 2
83#define SPI_DEV_ID_3 3
84
85/* Interrupt mask */
86#define SPI_INTR_CMD_DONE 0x01
87#define SPI_INTR_RX_OVERFLOW 0x02
88#define SPI_INTR_TX_UNDERFLOW 0x04
89#define SPI_INTR_TX_OVERFLOW 0x08
90#define SPI_INTR_RX_UNDERFLOW 0x10
91#define SPI_INTR_CLEAR_ALL 0x1f
92
93/* Status */
94#define SPI_RX_EMPTY 0x02
95#define SPI_CMD_BUSY 0x04
96#define SPI_SERIAL_BUSY 0x08
97
98/* Clock configuration */
99#define SPI_CLK_20MHZ 0x00
100#define SPI_CLK_0_391MHZ 0x01
101#define SPI_CLK_0_781MHZ 0x02 /* default */
102#define SPI_CLK_1_563MHZ 0x03
103#define SPI_CLK_3_125MHZ 0x04
104#define SPI_CLK_6_250MHZ 0x05
105#define SPI_CLK_12_50MHZ 0x06
106#define SPI_CLK_MASK 0x07
107#define SPI_SSOFFTIME_MASK 0x38
108#define SPI_SSOFFTIME_SHIFT 3
109#define SPI_BYTE_SWAP 0x80
110
111enum bcm63xx_regs_spi {
112 SPI_CMD,
113 SPI_INT_STATUS,
114 SPI_INT_MASK_ST,
115 SPI_INT_MASK,
116 SPI_ST,
117 SPI_CLK_CFG,
118 SPI_FILL_BYTE,
119 SPI_MSG_TAIL,
120 SPI_RX_TAIL,
121 SPI_MSG_CTL,
122 SPI_MSG_DATA,
123 SPI_RX_DATA,
124 SPI_MSG_TYPE_SHIFT,
125 SPI_MSG_CTL_WIDTH,
126 SPI_MSG_DATA_SIZE,
127};
b42dfed8 128
b17de076
JG		 129#define BCM63XX_SPI_MAX_PREPEND 15
130
65059997 131#define BCM63XX_SPI_MAX_CS 8
a45fcea5 132#define BCM63XX_SPI_BUS_NUM 0
65059997 133
b42dfed8 134struct bcm63xx_spi {
b42dfed8
FF		 135 struct completion done;
136
137 void __iomem *regs;
138 int irq;
139
140 /* Platform data */
44d8fb30 141 const unsigned long *reg_offsets;
b85d65dd 142 unsigned int fifo_size;
5a670445
FF		 143 unsigned int msg_type_shift;
144 unsigned int msg_ctl_width;
b42dfed8 145
b42dfed8
FF		 146 /* data iomem */
147 u8 __iomem *tx_io;
148 const u8 __iomem *rx_io;
149
b42dfed8
FF		 150 struct clk *clk;
151 struct platform_device *pdev;
152};
153
154static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
44d8fb30 155 unsigned int offset)
b42dfed8 156{
44d8fb30 157 return readb(bs->regs + bs->reg_offsets[offset]);
b42dfed8
FF		 158}
159
160static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
161 unsigned int offset)
162{
682b5280 163#ifdef CONFIG_CPU_BIG_ENDIAN
44d8fb30 164 return ioread16be(bs->regs + bs->reg_offsets[offset]);
158fcc4e 165#else
44d8fb30 166 return readw(bs->regs + bs->reg_offsets[offset]);
158fcc4e 167#endif
b42dfed8
FF		 168}
169
170static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
171 u8 value, unsigned int offset)
172{
44d8fb30 173 writeb(value, bs->regs + bs->reg_offsets[offset]);
b42dfed8
FF		 174}
175
176static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
177 u16 value, unsigned int offset)
178{
682b5280 179#ifdef CONFIG_CPU_BIG_ENDIAN
44d8fb30 180 iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
158fcc4e 181#else
44d8fb30 182 writew(value, bs->regs + bs->reg_offsets[offset]);
158fcc4e 183#endif
b42dfed8
FF		 184}
185
b85d65dd 186static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
b42dfed8
FF		 187 { 20000000, SPI_CLK_20MHZ },
188 { 12500000, SPI_CLK_12_50MHZ },
189 { 6250000, SPI_CLK_6_250MHZ },
190 { 3125000, SPI_CLK_3_125MHZ },
191 { 1563000, SPI_CLK_1_563MHZ },
192 { 781000, SPI_CLK_0_781MHZ },
193 { 391000, SPI_CLK_0_391MHZ }
194};
195
cde4384e
FF		 196static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
197 struct spi_transfer *t)
198{
199 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
cde4384e
FF		 200 u8 clk_cfg, reg;
201 int i;
202
4dde99bd
GU		 203 /* Default to lowest clock configuration */
204 clk_cfg = SPI_CLK_0_391MHZ;
205
b42dfed8
FF		 206 /* Find the closest clock configuration */
207 for (i = 0; i < SPI_CLK_MASK; i++) {
68792e2a 208 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8
FF		 209 clk_cfg = bcm63xx_spi_freq_table[i][1];
210 break;
211 }
212 }
213
b42dfed8
FF		 214 /* clear existing clock configuration bits of the register */
215 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
216 reg &= ~SPI_CLK_MASK;
217 reg |= clk_cfg;
218
219 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
220 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
68792e2a 221 clk_cfg, t->speed_hz);
b42dfed8
FF		 222}
223
224/* the spi->mode bits understood by this driver: */
225#define MODEBITS (SPI_CPOL | SPI_CPHA)
226
b17de076
JG		 227static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
228 unsigned int num_transfers)
b42dfed8
FF		 229{
230 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
231 u16 msg_ctl;
232 u16 cmd;
b17de076
JG		 233 unsigned int i, timeout = 0, prepend_len = 0, len = 0;
234 struct spi_transfer *t = first;
235 bool do_rx = false;
236 bool do_tx = false;
b42dfed8 237
cde4384e
FF		 238 /* Disable the CMD_DONE interrupt */
239 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
240
b42dfed8
FF		 241 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
242 t->tx_buf, t->rx_buf, t->len);
243
b17de076
JG		 244 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
245 prepend_len = t->len;
246
247 /* prepare the buffer */
248 for (i = 0; i < num_transfers; i++) {
249 if (t->tx_buf) {
250 do_tx = true;
251 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
252
253 /* don't prepend more than one tx */
254 if (t != first)
255 prepend_len = 0;
256 }
257
258 if (t->rx_buf) {
259 do_rx = true;
260 /* prepend is half-duplex write only */
261 if (t == first)
262 prepend_len = 0;
263 }
264
265 len += t->len;
266
267 t = list_entry(t->transfer_list.next, struct spi_transfer,
268 transfer_list);
269 }
270
aa0fe826 271 reinit_completion(&bs->done);
b42dfed8
FF		 272
273 /* Fill in the Message control register */
b17de076 274 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
b42dfed8 275
b17de076 276 if (do_rx && do_tx && prepend_len == 0)
5a670445 277 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
b17de076 278 else if (do_rx)
5a670445 279 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
b17de076 280 else if (do_tx)
5a670445
FF		 281 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
282
283 switch (bs->msg_ctl_width) {
284 case 8:
285 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
286 break;
287 case 16:
288 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
289 break;
290 }
b42dfed8
FF		 291
292 /* Issue the transfer */
293 cmd = SPI_CMD_START_IMMEDIATE;
b17de076 294 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
b42dfed8
FF		 295 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
296 bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8 297
cde4384e
FF		 298 /* Enable the CMD_DONE interrupt */
299 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8 300
c0fde3ba
JG		 301 timeout = wait_for_completion_timeout(&bs->done, HZ);
302 if (!timeout)
303 return -ETIMEDOUT;
304
20e9e78f 305 if (!do_rx)
b17de076
JG		 306 return 0;
307
308 len = 0;
309 t = first;
c0fde3ba 310 /* Read out all the data */
b17de076
JG		 311 for (i = 0; i < num_transfers; i++) {
312 if (t->rx_buf)
313 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
314
315 if (t != first || prepend_len == 0)
316 len += t->len;
317
318 t = list_entry(t->transfer_list.next, struct spi_transfer,
319 transfer_list);
320 }
c0fde3ba
JG		 321
322 return 0;
b42dfed8
FF		 323}
324
cde4384e
FF		 325static int bcm63xx_spi_transfer_one(struct spi_master *master,
326 struct spi_message *m)
327{
328 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b17de076 329 struct spi_transfer *t, *first = NULL;
cde4384e
FF		 330 struct spi_device *spi = m->spi;
331 int status = 0;
b17de076
JG		 332 unsigned int n_transfers = 0, total_len = 0;
333 bool can_use_prepend = false;
334
335 /*
336 * This SPI controller does not support keeping CS active after a
337 * transfer.
338 * Work around this by merging as many transfers we can into one big
339 * full-duplex transfers.
340 */
b42dfed8 341 list_for_each_entry(t, &m->transfers, transfer_list) {
b17de076
JG		 342 if (!first)
343 first = t;
344
345 n_transfers++;
346 total_len += t->len;
347
348 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
349 first->len <= BCM63XX_SPI_MAX_PREPEND)
350 can_use_prepend = true;
351 else if (can_use_prepend && t->tx_buf)
352 can_use_prepend = false;
353
c0fde3ba 354 /* we can only transfer one fifo worth of data */
b17de076
JG		 355 if ((can_use_prepend &&
356 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
357 (!can_use_prepend && total_len > bs->fifo_size)) {
c0fde3ba 358 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
b17de076 359 total_len, bs->fifo_size);
c0fde3ba
JG		 360 status = -EINVAL;
361 goto exit;
362 }
cde4384e 363
b17de076
JG		 364 /* all combined transfers have to have the same speed */
365 if (t->speed_hz != first->speed_hz) {
366 dev_err(&spi->dev, "unable to change speed between transfers\n");
c0fde3ba
JG		 367 status = -EINVAL;
368 goto exit;
369 }
cde4384e 370
b17de076 371 /* CS will be deasserted directly after transfer */
c5751ba0 372 if (t->delay_usecs || t->delay.value) {
b17de076 373 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
c0fde3ba
JG		 374 status = -EINVAL;
375 goto exit;
376 }
cde4384e 377
b17de076
JG		 378 if (t->cs_change ||
379 list_is_last(&t->transfer_list, &m->transfers)) {
380 /* configure adapter for a new transfer */
381 bcm63xx_spi_setup_transfer(spi, first);
cde4384e 382
b17de076
JG		 383 /* send the data */
384 status = bcm63xx_txrx_bufs(spi, first, n_transfers);
385 if (status)
386 goto exit;
387
388 m->actual_length += total_len;
b42dfed8 389
b17de076
JG		 390 first = NULL;
391 n_transfers = 0;
392 total_len = 0;
393 can_use_prepend = false;
394 }
cde4384e
FF		 395 }
396exit:
397 m->status = status;
398 spi_finalize_current_message(master);
b42dfed8 399
cde4384e 400 return 0;
b42dfed8
FF		 401}
402
403/* This driver supports single master mode only. Hence
404 * CMD_DONE is the only interrupt we care about
405 */
406static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
407{
408 struct spi_master *master = (struct spi_master *)dev_id;
409 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
410 u8 intr;
b42dfed8
FF		 411
412 /* Read interupts and clear them immediately */
413 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
414 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
415 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
416
cde4384e
FF		 417 /* A transfer completed */
418 if (intr & SPI_INTR_CMD_DONE)
419 complete(&bs->done);
b42dfed8
FF		 420
421 return IRQ_HANDLED;
422}
423
ccd0657c 424static size_t bcm63xx_spi_max_length(struct spi_device *spi)
0135c03d
JG		 425{
426 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
427
428 return bs->fifo_size;
429}
430
44d8fb30
JG		 431static const unsigned long bcm6348_spi_reg_offsets[] = {
432 [SPI_CMD] = SPI_6348_CMD,
433 [SPI_INT_STATUS] = SPI_6348_INT_STATUS,
434 [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
435 [SPI_INT_MASK] = SPI_6348_INT_MASK,
436 [SPI_ST] = SPI_6348_ST,
437 [SPI_CLK_CFG] = SPI_6348_CLK_CFG,
438 [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
439 [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
440 [SPI_RX_TAIL] = SPI_6348_RX_TAIL,
441 [SPI_MSG_CTL] = SPI_6348_MSG_CTL,
442 [SPI_MSG_DATA] = SPI_6348_MSG_DATA,
443 [SPI_RX_DATA] = SPI_6348_RX_DATA,
444 [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
445 [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
446 [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
447};
448
449static const unsigned long bcm6358_spi_reg_offsets[] = {
450 [SPI_CMD] = SPI_6358_CMD,
451 [SPI_INT_STATUS] = SPI_6358_INT_STATUS,
452 [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
453 [SPI_INT_MASK] = SPI_6358_INT_MASK,
454 [SPI_ST] = SPI_6358_ST,
455 [SPI_CLK_CFG] = SPI_6358_CLK_CFG,
456 [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
457 [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
458 [SPI_RX_TAIL] = SPI_6358_RX_TAIL,
459 [SPI_MSG_CTL] = SPI_6358_MSG_CTL,
460 [SPI_MSG_DATA] = SPI_6358_MSG_DATA,
461 [SPI_RX_DATA] = SPI_6358_RX_DATA,
462 [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
463 [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
464 [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
465};
466
467static const struct platform_device_id bcm63xx_spi_dev_match[] = {
468 {
469 .name = "bcm6348-spi",
470 .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
471 },
472 {
473 .name = "bcm6358-spi",
474 .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
475 },
476 {
477 },
478};
b42dfed8 479
c29f0889
JG		 480static const struct of_device_id bcm63xx_spi_of_match[] = {
481 { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
482 { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
483 { },
484};
485
fd4a319b 486static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8
FF		 487{
488 struct resource *r;
44d8fb30 489 const unsigned long *bcm63xx_spireg;
b42dfed8 490 struct device *dev = &pdev->dev;
c29f0889 491 int irq, bus_num;
b42dfed8
FF		 492 struct spi_master *master;
493 struct clk *clk;
494 struct bcm63xx_spi *bs;
495 int ret;
c29f0889 496 u32 num_cs = BCM63XX_SPI_MAX_CS;
38807ade 497 struct reset_control *reset;
b42dfed8 498
c29f0889
JG		 499 if (dev->of_node) {
500 const struct of_device_id *match;
44d8fb30 501
c29f0889
JG		 502 match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
503 if (!match)
504 return -EINVAL;
505 bcm63xx_spireg = match->data;
506
507 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
508 if (num_cs > BCM63XX_SPI_MAX_CS) {
509 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
510 num_cs);
511 num_cs = BCM63XX_SPI_MAX_CS;
512 }
513
514 bus_num = -1;
515 } else if (pdev->id_entry->driver_data) {
516 const struct platform_device_id *match = pdev->id_entry;
517
518 bcm63xx_spireg = (const unsigned long *)match->driver_data;
519 bus_num = BCM63XX_SPI_BUS_NUM;
520 } else {
521 return -EINVAL;
522 }
44d8fb30 523
b42dfed8 524 irq = platform_get_irq(pdev, 0);
6b8ac10e 525 if (irq < 0)
ba8afe94 526 return irq;
b42dfed8 527
acf4fc6f 528 clk = devm_clk_get(dev, "spi");
b42dfed8
FF		 529 if (IS_ERR(clk)) {
530 dev_err(dev, "no clock for device\n");
acf4fc6f 531 return PTR_ERR(clk);
b42dfed8
FF		 532 }
533
38807ade
ÁFR		 534 reset = devm_reset_control_get_optional_exclusive(dev, NULL);
535 if (IS_ERR(reset))
536 return PTR_ERR(reset);
537
b42dfed8
FF		 538 master = spi_alloc_master(dev, sizeof(*bs));
539 if (!master) {
540 dev_err(dev, "out of memory\n");
acf4fc6f 541 return -ENOMEM;
b42dfed8
FF		 542 }
543
544 bs = spi_master_get_devdata(master);
aa0fe826 545 init_completion(&bs->done);
b42dfed8
FF		 546
547 platform_set_drvdata(pdev, master);
548 bs->pdev = pdev;
549
de0fa83c 550 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b66c7730
JG		 551 bs->regs = devm_ioremap_resource(&pdev->dev, r);
552 if (IS_ERR(bs->regs)) {
553 ret = PTR_ERR(bs->regs);
b42dfed8
FF		 554 goto out_err;
555 }
556
557 bs->irq = irq;
558 bs->clk = clk;
44d8fb30
JG		 559 bs->reg_offsets = bcm63xx_spireg;
560 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
b42dfed8
FF		 561
562 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
563 pdev->name, master);
564 if (ret) {
565 dev_err(dev, "unable to request irq\n");
566 goto out_err;
567 }
568
c29f0889
JG		 569 master->dev.of_node = dev->of_node;
570 master->bus_num = bus_num;
571 master->num_chipselect = num_cs;
cde4384e 572 master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255 573 master->mode_bits = MODEBITS;
24778be2 574 master->bits_per_word_mask = SPI_BPW_MASK(8);
0135c03d
JG		 575 master->max_transfer_size = bcm63xx_spi_max_length;
576 master->max_message_size = bcm63xx_spi_max_length;
5355d96d 577 master->auto_runtime_pm = true;
44d8fb30
JG		 578 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
579 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
580 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
581 bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
5a670445 582
b42dfed8 583 /* Initialize hardware */
ea01e8a4
JG		 584 ret = clk_prepare_enable(bs->clk);
585 if (ret)
586 goto out_err;
587
38807ade
ÁFR		 588 ret = reset_control_reset(reset);
589 if (ret) {
590 dev_err(dev, "unable to reset device: %d\n", ret);
591 goto out_clk_disable;
592 }
593
b42dfed8
FF		 594 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
595
596 /* register and we are done */
bca76931 597 ret = devm_spi_register_master(dev, master);
b42dfed8
FF		 598 if (ret) {
599 dev_err(dev, "spi register failed\n");
600 goto out_clk_disable;
601 }
602
0ba2cf70
AB		 603 dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
604 r, irq, bs->fifo_size);
b42dfed8
FF		 605
606 return 0;
607
608out_clk_disable:
4fbb82a7 609 clk_disable_unprepare(clk);
b42dfed8 610out_err:
b42dfed8 611 spi_master_put(master);
b42dfed8
FF		 612 return ret;
613}
614
fd4a319b 615static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8 616{
9637b86f 617 struct spi_master *master = platform_get_drvdata(pdev);
b42dfed8
FF		 618 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
619
620 /* reset spi block */
621 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8
FF		 622
623 /* HW shutdown */
4fbb82a7 624 clk_disable_unprepare(bs->clk);
b42dfed8 625
b42dfed8
FF		 626 return 0;
627}
628
1bae2028 629#ifdef CONFIG_PM_SLEEP
b42dfed8
FF		 630static int bcm63xx_spi_suspend(struct device *dev)
631{
a1216394 632 struct spi_master *master = dev_get_drvdata(dev);
b42dfed8
FF		 633 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
634
96519957
FF		 635 spi_master_suspend(master);
636
4fbb82a7 637 clk_disable_unprepare(bs->clk);
b42dfed8
FF		 638
639 return 0;
640}
641
642static int bcm63xx_spi_resume(struct device *dev)
643{
a1216394 644 struct spi_master *master = dev_get_drvdata(dev);
b42dfed8 645 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
ea01e8a4 646 int ret;
b42dfed8 647
ea01e8a4
JG		 648 ret = clk_prepare_enable(bs->clk);
649 if (ret)
650 return ret;
b42dfed8 651
96519957
FF		 652 spi_master_resume(master);
653
b42dfed8
FF		 654 return 0;
655}
1bae2028 656#endif
b42dfed8
FF		 657
658static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
1bae2028 659 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
b42dfed8
FF		 660};
661
b42dfed8
FF		 662static struct platform_driver bcm63xx_spi_driver = {
663 .driver = {
664 .name = "bcm63xx-spi",
1bae2028 665 .pm = &bcm63xx_spi_pm_ops,
c29f0889 666 .of_match_table = bcm63xx_spi_of_match,
b42dfed8 667 },
44d8fb30 668 .id_table = bcm63xx_spi_dev_match,
b42dfed8 669 .probe = bcm63xx_spi_probe,
fd4a319b 670 .remove = bcm63xx_spi_remove,
b42dfed8
FF		 671};
672
673module_platform_driver(bcm63xx_spi_driver);
674
675MODULE_ALIAS("platform:bcm63xx_spi");
676MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
677MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
678MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
679MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)