[linux-2.6-block.git] / drivers / spi / spi-bcm63xx-hsspi.c

/*
 * Broadcom BCM63XX High Speed SPI Controller driver
 *
 * Copyright 2000-2010 Broadcom Corporation
 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/reset.h>
#include <linux/pm_runtime.h>

#define HSSPI_GLOBAL_CTRL_REG			0x0
#define GLOBAL_CTRL_CS_POLARITY_SHIFT		0
#define GLOBAL_CTRL_CS_POLARITY_MASK		0x000000ff
#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT		8
#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK		0x0000ff00
#define GLOBAL_CTRL_CLK_GATE_SSOFF		BIT(16)
#define GLOBAL_CTRL_CLK_POLARITY		BIT(17)
#define GLOBAL_CTRL_MOSI_IDLE			BIT(18)

#define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4

#define HSSPI_INT_STATUS_REG			0x8
#define HSSPI_INT_STATUS_MASKED_REG		0xc
#define HSSPI_INT_MASK_REG			0x10

#define HSSPI_PINGx_CMD_DONE(i)			BIT((i * 8) + 0)
#define HSSPI_PINGx_RX_OVER(i)			BIT((i * 8) + 1)
#define HSSPI_PINGx_TX_UNDER(i)			BIT((i * 8) + 2)
#define HSSPI_PINGx_POLL_TIMEOUT(i)		BIT((i * 8) + 3)
#define HSSPI_PINGx_CTRL_INVAL(i)		BIT((i * 8) + 4)

#define HSSPI_INT_CLEAR_ALL			0xff001f1f

#define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
#define PINGPONG_CMD_COMMAND_MASK		0xf
#define PINGPONG_COMMAND_NOOP			0
#define PINGPONG_COMMAND_START_NOW		1
#define PINGPONG_COMMAND_START_TRIGGER		2
#define PINGPONG_COMMAND_HALT			3
#define PINGPONG_COMMAND_FLUSH			4
#define PINGPONG_CMD_PROFILE_SHIFT		8
#define PINGPONG_CMD_SS_SHIFT			12

#define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)

#define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
#define CLK_CTRL_FREQ_CTRL_MASK			0x0000ffff
#define CLK_CTRL_SPI_CLK_2X_SEL			BIT(14)
#define CLK_CTRL_ACCUM_RST_ON_LOOP		BIT(15)

#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
#define SIGNAL_CTRL_LATCH_RISING		BIT(12)
#define SIGNAL_CTRL_LAUNCH_RISING		BIT(13)
#define SIGNAL_CTRL_ASYNC_INPUT_PATH		BIT(16)

#define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
#define MODE_CTRL_MODE_3WIRE			BIT(20)
#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24

#define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)


#define HSSPI_OP_MULTIBIT			BIT(11)
#define HSSPI_OP_CODE_SHIFT			13
#define HSSPI_OP_SLEEP				(0 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ_WRITE			(1 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_WRITE				(2 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ				(3 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_SETIRQ				(4 << HSSPI_OP_CODE_SHIFT)

#define HSSPI_BUFFER_LEN			512
#define HSSPI_OPCODE_LEN			2

#define HSSPI_MAX_PREPEND_LEN			15

#define HSSPI_MAX_SYNC_CLOCK			30000000

#define HSSPI_SPI_MAX_CS			8
#define HSSPI_BUS_NUM				1 /* 0 is legacy SPI */

struct bcm63xx_hsspi {
	struct completion done;
	struct mutex bus_mutex;

	struct platform_device *pdev;
	struct clk *clk;
	struct clk *pll_clk;
	void __iomem *regs;
	u8 __iomem *fifo;

	u32 speed_hz;
	u8 cs_polarity;
};

static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
				 bool active)
{
	u32 reg;

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

	reg &= ~BIT(cs);
	if (active == !(bs->cs_polarity & BIT(cs)))
		reg |= BIT(cs);

	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);
}

static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
				  struct spi_device *spi, int hz)
{
	unsigned int profile = spi->chip_select;
	u32 reg;

	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
		     bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));

	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	if (hz > HSSPI_MAX_SYNC_CLOCK)
		reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
	else
		reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));

	mutex_lock(&bs->bus_mutex);
	/* setup clock polarity */
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
	if (spi->mode & SPI_CPOL)
		reg |= GLOBAL_CTRL_CLK_POLARITY;
	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);
}

static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	unsigned int chip_select = spi->chip_select;
	u16 opcode = 0;
	int pending = t->len;
	int step_size = HSSPI_BUFFER_LEN;
	const u8 *tx = t->tx_buf;
	u8 *rx = t->rx_buf;

	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);

	if (tx && rx)
		opcode = HSSPI_OP_READ_WRITE;
	else if (tx)
		opcode = HSSPI_OP_WRITE;
	else if (rx)
		opcode = HSSPI_OP_READ;

	if (opcode != HSSPI_OP_READ)
		step_size -= HSSPI_OPCODE_LEN;

	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
	    (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
		opcode |= HSSPI_OP_MULTIBIT;

	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
		     1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
		     bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));

	while (pending > 0) {
		int curr_step = min_t(int, step_size, pending);

		reinit_completion(&bs->done);
		if (tx) {
			memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
			tx += curr_step;
		}

		__raw_writew(opcode | curr_step, bs->fifo);

		/* enable interrupt */
		__raw_writel(HSSPI_PINGx_CMD_DONE(0),
			     bs->regs + HSSPI_INT_MASK_REG);

		/* start the transfer */
		__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
			     chip_select << PINGPONG_CMD_PROFILE_SHIFT |
			     PINGPONG_COMMAND_START_NOW,
			     bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));

		if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
			dev_err(&bs->pdev->dev, "transfer timed out!\n");
			return -ETIMEDOUT;
		}

		if (rx) {
			memcpy_fromio(rx, bs->fifo, curr_step);
			rx += curr_step;
		}

		pending -= curr_step;
	}

	return 0;
}

static int bcm63xx_hsspi_setup(struct spi_device *spi)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	u32 reg;

	reg = __raw_readl(bs->regs +
			  HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
	if (spi->mode & SPI_CPHA)
		reg |= SIGNAL_CTRL_LAUNCH_RISING;
	else
		reg |= SIGNAL_CTRL_LATCH_RISING;
	__raw_writel(reg, bs->regs +
		     HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

	/* only change actual polarities if there is no transfer */
	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
		if (spi->mode & SPI_CS_HIGH)
			reg |= BIT(spi->chip_select);
		else
			reg &= ~BIT(spi->chip_select);
		__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	}

	if (spi->mode & SPI_CS_HIGH)
		bs->cs_polarity |= BIT(spi->chip_select);
	else
		bs->cs_polarity &= ~BIT(spi->chip_select);

	mutex_unlock(&bs->bus_mutex);

	return 0;
}

static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
				      struct spi_message *msg)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t;
	struct spi_device *spi = msg->spi;
	int status = -EINVAL;
	int dummy_cs;
	u32 reg;

	/* This controller does not support keeping CS active during idle.
	 * To work around this, we use the following ugly hack:
	 *
	 * a. Invert the target chip select's polarity so it will be active.
	 * b. Select a "dummy" chip select to use as the hardware target.
	 * c. Invert the dummy chip select's polarity so it will be inactive
	 *    during the actual transfers.
	 * d. Tell the hardware to send to the dummy chip select. Thanks to
	 *    the multiplexed nature of SPI the actual target will receive
	 *    the transfer and we see its response.
	 *
	 * e. At the end restore the polarities again to their default values.
	 */

	dummy_cs = !spi->chip_select;
	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);

	list_for_each_entry(t, &msg->transfers, transfer_list) {
		status = bcm63xx_hsspi_do_txrx(spi, t);
		if (status)
			break;

		msg->actual_length += t->len;

		spi_transfer_delay_exec(t);

		if (t->cs_change)
			bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
	}

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
	reg |= bs->cs_polarity;
	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);

	msg->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
{
	struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;

	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
		return IRQ_NONE;

	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);

	complete(&bs->done);

	return IRQ_HANDLED;
}

static int bcm63xx_hsspi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm63xx_hsspi *bs;
	void __iomem *regs;
	struct device *dev = &pdev->dev;
	struct clk *clk, *pll_clk = NULL;
	int irq, ret;
	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
	struct reset_control *reset;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	clk = devm_clk_get(dev, "hsspi");

	if (IS_ERR(clk))
		return PTR_ERR(clk);

	reset = devm_reset_control_get_optional_exclusive(dev, NULL);
	if (IS_ERR(reset))
		return PTR_ERR(reset);

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	ret = reset_control_reset(reset);
	if (ret) {
		dev_err(dev, "unable to reset device: %d\n", ret);
		goto out_disable_clk;
	}

	rate = clk_get_rate(clk);
	if (!rate) {
		pll_clk = devm_clk_get(dev, "pll");

		if (IS_ERR(pll_clk)) {
			ret = PTR_ERR(pll_clk);
			goto out_disable_clk;
		}

		ret = clk_prepare_enable(pll_clk);
		if (ret)
			goto out_disable_clk;

		rate = clk_get_rate(pll_clk);
		if (!rate) {
			ret = -EINVAL;
			goto out_disable_pll_clk;
		}
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		ret = -ENOMEM;
		goto out_disable_pll_clk;
	}

	bs = spi_master_get_devdata(master);
	bs->pdev = pdev;
	bs->clk = clk;
	bs->pll_clk = pll_clk;
	bs->regs = regs;
	bs->speed_hz = rate;
	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));

	mutex_init(&bs->bus_mutex);
	init_completion(&bs->done);

	master->dev.of_node = dev->of_node;
	if (!dev->of_node)
		master->bus_num = HSSPI_BUS_NUM;

	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	if (num_cs > 8) {
		dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
			 num_cs);
		num_cs = HSSPI_SPI_MAX_CS;
	}
	master->num_chipselect = num_cs;
	master->setup = bcm63xx_hsspi_setup;
	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
			    SPI_RX_DUAL | SPI_TX_DUAL;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);

	/* Initialize the hardware */
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);

	/* clean up any pending interrupts */
	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);

	/* read out default CS polarities */
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
	__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
		     bs->regs + HSSPI_GLOBAL_CTRL_REG);

	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
			       pdev->name, bs);

	if (ret)
		goto out_put_master;

	pm_runtime_enable(&pdev->dev);

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret)
		goto out_pm_disable;

	return 0;

out_pm_disable:
	pm_runtime_disable(&pdev->dev);
out_put_master:
	spi_master_put(master);
out_disable_pll_clk:
	clk_disable_unprepare(pll_clk);
out_disable_clk:
	clk_disable_unprepare(clk);
	return ret;
}


static int bcm63xx_hsspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);

	/* reset the hardware and block queue progress */
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	clk_disable_unprepare(bs->pll_clk);
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bcm63xx_hsspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(bs->pll_clk);
	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_hsspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	if (bs->pll_clk) {
		ret = clk_prepare_enable(bs->pll_clk);
		if (ret) {
			clk_disable_unprepare(bs->clk);
			return ret;
		}
	}

	spi_master_resume(master);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
			 bcm63xx_hsspi_resume);

static const struct of_device_id bcm63xx_hsspi_of_match[] = {
	{ .compatible = "brcm,bcm6328-hsspi", },
	{ },
};
MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);

static struct platform_driver bcm63xx_hsspi_driver = {
	.driver = {
		.name	= "bcm63xx-hsspi",
		.pm	= &bcm63xx_hsspi_pm_ops,
		.of_match_table = bcm63xx_hsspi_of_match,
	},
	.probe		= bcm63xx_hsspi_probe,
	.remove		= bcm63xx_hsspi_remove,
};

module_platform_driver(bcm63xx_hsspi_driver);

MODULE_ALIAS("platform:bcm63xx_hsspi");
MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
142168eb JG	1	/*
	2	* Broadcom BCM63XX High Speed SPI Controller driver
	3	*
	4	* Copyright 2000-2010 Broadcom Corporation
	5	* Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
	6	*
	7	* Licensed under the GNU/GPL. See COPYING for details.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/io.h>
	13	#include <linux/clk.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/delay.h>
	17	#include <linux/dma-mapping.h>
	18	#include <linux/err.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/spi/spi.h>
142168eb	21	#include <linux/mutex.h>
7ab24635	22	#include <linux/of.h>
0eeadddb	23	#include <linux/reset.h>
fb8695e3	24	#include <linux/pm_runtime.h>
142168eb JG	25
	26	#define HSSPI_GLOBAL_CTRL_REG 0x0
	27	#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
	28	#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
	29	#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
	30	#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
	31	#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
	32	#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
	33	#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
	34
	35	#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
	36
	37	#define HSSPI_INT_STATUS_REG 0x8
	38	#define HSSPI_INT_STATUS_MASKED_REG 0xc
	39	#define HSSPI_INT_MASK_REG 0x10
	40
	41	#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
	42	#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
	43	#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
	44	#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
	45	#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
	46
	47	#define HSSPI_INT_CLEAR_ALL 0xff001f1f
	48
	49	#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
	50	#define PINGPONG_CMD_COMMAND_MASK 0xf
	51	#define PINGPONG_COMMAND_NOOP 0
	52	#define PINGPONG_COMMAND_START_NOW 1
	53	#define PINGPONG_COMMAND_START_TRIGGER 2
	54	#define PINGPONG_COMMAND_HALT 3
	55	#define PINGPONG_COMMAND_FLUSH 4
	56	#define PINGPONG_CMD_PROFILE_SHIFT 8
	57	#define PINGPONG_CMD_SS_SHIFT 12
	58
	59	#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
	60
	61	#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
	62	#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
	63	#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
	64	#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
	65
	66	#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
	67	#define SIGNAL_CTRL_LATCH_RISING BIT(12)
	68	#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
	69	#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
	70
	71	#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
	72	#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
	73	#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
	74	#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
	75	#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
	76	#define MODE_CTRL_MODE_3WIRE BIT(20)
	77	#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
	78
	79	#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
	80
	81
f4d86223	82	#define HSSPI_OP_MULTIBIT BIT(11)
142168eb JG	83	#define HSSPI_OP_CODE_SHIFT 13
	84	#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
	85	#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
	86	#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
	87	#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
	88	#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
	89
	90	#define HSSPI_BUFFER_LEN 512
	91	#define HSSPI_OPCODE_LEN 2
	92
	93	#define HSSPI_MAX_PREPEND_LEN 15
	94
	95	#define HSSPI_MAX_SYNC_CLOCK 30000000
	96
7ab24635	97	#define HSSPI_SPI_MAX_CS 8
142168eb JG	98	#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
	99
	100	struct bcm63xx_hsspi {
	101	struct completion done;
	102	struct mutex bus_mutex;
	103
	104	struct platform_device *pdev;
	105	struct clk *clk;
0fd85869	106	struct clk *pll_clk;
142168eb JG	107	void __iomem *regs;
	108	u8 __iomem *fifo;
	109
	110	u32 speed_hz;
	111	u8 cs_polarity;
	112	};
	113
c3c25ea7	114	static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
142168eb JG	115	bool active)
	116	{
	117	u32 reg;
	118
	119	mutex_lock(&bs->bus_mutex);
	120	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	121
	122	reg &= ~BIT(cs);
	123	if (active == !(bs->cs_polarity & BIT(cs)))
	124	reg \|= BIT(cs);
	125
	126	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	127	mutex_unlock(&bs->bus_mutex);
	128	}
	129
	130	static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
	131	struct spi_device *spi, int hz)
	132	{
c3c25ea7	133	unsigned int profile = spi->chip_select;
142168eb JG	134	u32 reg;
	135
	136	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
	137	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP \| reg,
	138	bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
	139
	140	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	141	if (hz > HSSPI_MAX_SYNC_CLOCK)
	142	reg \|= SIGNAL_CTRL_ASYNC_INPUT_PATH;
	143	else
	144	reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
	145	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	146
	147	mutex_lock(&bs->bus_mutex);
	148	/* setup clock polarity */
	149	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	150	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
	151	if (spi->mode & SPI_CPOL)
	152	reg \|= GLOBAL_CTRL_CLK_POLARITY;
	153	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	154	mutex_unlock(&bs->bus_mutex);
	155	}
	156
	157	static int bcm63xx_hsspi_do_txrx(struct spi_device spi, struct spi_transfer t)
	158	{
	159	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
c3c25ea7	160	unsigned int chip_select = spi->chip_select;
142168eb JG	161	u16 opcode = 0;
	162	int pending = t->len;
	163	int step_size = HSSPI_BUFFER_LEN;
	164	const u8 *tx = t->tx_buf;
	165	u8 *rx = t->rx_buf;
	166
	167	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
	168	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
	169
	170	if (tx && rx)
	171	opcode = HSSPI_OP_READ_WRITE;
	172	else if (tx)
	173	opcode = HSSPI_OP_WRITE;
	174	else if (rx)
	175	opcode = HSSPI_OP_READ;
	176
	177	if (opcode != HSSPI_OP_READ)
	178	step_size -= HSSPI_OPCODE_LEN;
	179
f4d86223 JG	180	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) \|\|
	181	(opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
	182	opcode \|= HSSPI_OP_MULTIBIT;
	183
	184	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT \|
	185	1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT \| 0xff,
142168eb JG	186	bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
	187
	188	while (pending > 0) {
	189	int curr_step = min_t(int, step_size, pending);
	190
aa0fe826	191	reinit_completion(&bs->done);
142168eb JG	192	if (tx) {
	193	memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
	194	tx += curr_step;
	195	}
	196
	197	__raw_writew(opcode \| curr_step, bs->fifo);
	198
	199	/* enable interrupt */
	200	__raw_writel(HSSPI_PINGx_CMD_DONE(0),
	201	bs->regs + HSSPI_INT_MASK_REG);
	202
	203	/* start the transfer */
	204	__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT \|
	205	chip_select << PINGPONG_CMD_PROFILE_SHIFT \|
	206	PINGPONG_COMMAND_START_NOW,
	207	bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
	208
	209	if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
	210	dev_err(&bs->pdev->dev, "transfer timed out!\n");
	211	return -ETIMEDOUT;
	212	}
	213
	214	if (rx) {
	215	memcpy_fromio(rx, bs->fifo, curr_step);
	216	rx += curr_step;
	217	}
	218
	219	pending -= curr_step;
	220	}
	221
	222	return 0;
	223	}
	224
	225	static int bcm63xx_hsspi_setup(struct spi_device *spi)
	226	{
	227	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	228	u32 reg;
	229
	230	reg = __raw_readl(bs->regs +
	231	HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	232	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING \| SIGNAL_CTRL_LATCH_RISING);
	233	if (spi->mode & SPI_CPHA)
	234	reg \|= SIGNAL_CTRL_LAUNCH_RISING;
	235	else
	236	reg \|= SIGNAL_CTRL_LATCH_RISING;
	237	__raw_writel(reg, bs->regs +
	238	HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	239
	240	mutex_lock(&bs->bus_mutex);
	241	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	242
	243	/* only change actual polarities if there is no transfer */
	244	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
	245	if (spi->mode & SPI_CS_HIGH)
	246	reg \|= BIT(spi->chip_select);
	247	else
	248	reg &= ~BIT(spi->chip_select);
	249	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	250	}
	251
	252	if (spi->mode & SPI_CS_HIGH)
	253	bs->cs_polarity \|= BIT(spi->chip_select);
	254	else
	255	bs->cs_polarity &= ~BIT(spi->chip_select);
256
257	mutex_unlock(&bs->bus_mutex);
258
259	return 0;
260	}
261
262	static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
263	struct spi_message *msg)
264	{
265	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
266	struct spi_transfer *t;
267	struct spi_device *spi = msg->spi;
268	int status = -EINVAL;
269	int dummy_cs;
270	u32 reg;
271
272	/* This controller does not support keeping CS active during idle.
273	* To work around this, we use the following ugly hack:
274	*
275	* a. Invert the target chip select's polarity so it will be active.
276	* b. Select a "dummy" chip select to use as the hardware target.
277	* c. Invert the dummy chip select's polarity so it will be inactive
278	* during the actual transfers.
279	* d. Tell the hardware to send to the dummy chip select. Thanks to
280	* the multiplexed nature of SPI the actual target will receive
281	* the transfer and we see its response.
282	*
283	* e. At the end restore the polarities again to their default values.
284	*/
285
286	dummy_cs = !spi->chip_select;
287	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
288
289	list_for_each_entry(t, &msg->transfers, transfer_list) {
290	status = bcm63xx_hsspi_do_txrx(spi, t);
291	if (status)
292	break;
293
294	msg->actual_length += t->len;
295
e74dc5c7	296	spi_transfer_delay_exec(t);
142168eb JG	297
	298	if (t->cs_change)
	299	bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
	300	}
	301
	302	mutex_lock(&bs->bus_mutex);
	303	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	304	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
	305	reg \|= bs->cs_polarity;
	306	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	307	mutex_unlock(&bs->bus_mutex);
	308
	309	msg->status = status;
	310	spi_finalize_current_message(master);
	311
	312	return 0;
	313	}
	314
	315	static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
	316	{
	317	struct bcm63xx_hsspi bs = (struct bcm63xx_hsspi )dev_id;
	318
	319	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
	320	return IRQ_NONE;
	321
	322	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	323	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	324
	325	complete(&bs->done);
	326
	327	return IRQ_HANDLED;
	328	}
	329
	330	static int bcm63xx_hsspi_probe(struct platform_device *pdev)
	331	{
	332	struct spi_master *master;
	333	struct bcm63xx_hsspi *bs;
142168eb JG	334	void __iomem *regs;
142168eb JG	335	struct device *dev = &pdev->dev;
0fd85869	336	struct clk clk, pll_clk = NULL;
142168eb	337	int irq, ret;
7ab24635	338	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
0eeadddb	339	struct reset_control *reset;
142168eb JG	340
142168eb JG	341	irq = platform_get_irq(pdev, 0);
6b8ac10e	342	if (irq < 0)
378da4a6	343	return irq;
142168eb	344
e364c8c2	345	regs = devm_platform_ioremap_resource(pdev, 0);
142168eb JG	346	if (IS_ERR(regs))
	347	return PTR_ERR(regs);
	348
b1bdd4f8	349	clk = devm_clk_get(dev, "hsspi");
142168eb JG	350
	351	if (IS_ERR(clk))
	352	return PTR_ERR(clk);
	353
0eeadddb ÁFR	354	reset = devm_reset_control_get_optional_exclusive(dev, NULL);
	355	if (IS_ERR(reset))
	356	return PTR_ERR(reset);
	357
0d7412ed SP	358	ret = clk_prepare_enable(clk);
	359	if (ret)
	360	return ret;
	361
0eeadddb ÁFR	362	ret = reset_control_reset(reset);
	363	if (ret) {
	364	dev_err(dev, "unable to reset device: %d\n", ret);
	365	goto out_disable_clk;
	366	}
	367
142168eb	368	rate = clk_get_rate(clk);
ff18e1ef	369	if (!rate) {
0fd85869	370	pll_clk = devm_clk_get(dev, "pll");
ff18e1ef	371
0d7412ed SP	372	if (IS_ERR(pll_clk)) {
	373	ret = PTR_ERR(pll_clk);
	374	goto out_disable_clk;
	375	}
	376
	377	ret = clk_prepare_enable(pll_clk);
	378	if (ret)
	379	goto out_disable_clk;
ff18e1ef JG	380
ff18e1ef JG	381	rate = clk_get_rate(pll_clk);
0d7412ed SP	382	if (!rate) {
0d7412ed SP	383	ret = -EINVAL;
0fd85869	384	goto out_disable_pll_clk;
0d7412ed	385	}
ff18e1ef	386	}
142168eb	387
142168eb JG	388	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	389	if (!master) {
	390	ret = -ENOMEM;
0fd85869	391	goto out_disable_pll_clk;
142168eb JG	392	}
	393
	394	bs = spi_master_get_devdata(master);
	395	bs->pdev = pdev;
	396	bs->clk = clk;
0fd85869	397	bs->pll_clk = pll_clk;
142168eb JG	398	bs->regs = regs;
	399	bs->speed_hz = rate;
	400	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
	401
	402	mutex_init(&bs->bus_mutex);
aa0fe826	403	init_completion(&bs->done);
142168eb	404
7ab24635 JG	405	master->dev.of_node = dev->of_node;
	406	if (!dev->of_node)
	407	master->bus_num = HSSPI_BUS_NUM;
	408
	409	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	410	if (num_cs > 8) {
	411	dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
	412	num_cs);
	413	num_cs = HSSPI_SPI_MAX_CS;
	414	}
	415	master->num_chipselect = num_cs;
142168eb JG	416	master->setup = bcm63xx_hsspi_setup;
142168eb JG	417	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
f4d86223 JG	418	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \|
f4d86223 JG	419	SPI_RX_DUAL \| SPI_TX_DUAL;
142168eb JG	420	master->bits_per_word_mask = SPI_BPW_MASK(8);
	421	master->auto_runtime_pm = true;
	422
	423	platform_set_drvdata(pdev, master);
	424
	425	/* Initialize the hardware */
	426	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	427
	428	/* clean up any pending interrupts */
	429	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	430
	431	/* read out default CS polarities */
	432	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	433	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
	434	__raw_writel(reg \| GLOBAL_CTRL_CLK_GATE_SSOFF,
	435	bs->regs + HSSPI_GLOBAL_CTRL_REG);
	436
	437	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
	438	pdev->name, bs);
	439
	440	if (ret)
	441	goto out_put_master;
	442
fb8695e3 ÁFR	443	pm_runtime_enable(&pdev->dev);
fb8695e3 ÁFR	444
142168eb	445	/* register and we are done */
7d255695	446	ret = devm_spi_register_master(dev, master);
142168eb	447	if (ret)
fb8695e3	448	goto out_pm_disable;
142168eb JG	449
	450	return 0;
	451
fb8695e3 ÁFR	452	out_pm_disable:
fb8695e3 ÁFR	453	pm_runtime_disable(&pdev->dev);
142168eb JG	454	out_put_master:
142168eb JG	455	spi_master_put(master);
0fd85869 JG	456	out_disable_pll_clk:
0fd85869 JG	457	clk_disable_unprepare(pll_clk);
142168eb JG	458	out_disable_clk:
142168eb JG	459	clk_disable_unprepare(clk);
142168eb JG	460	return ret;
	461	}
	462
	463
	464	static int bcm63xx_hsspi_remove(struct platform_device *pdev)
	465	{
	466	struct spi_master *master = platform_get_drvdata(pdev);
	467	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	468
142168eb JG	469	/* reset the hardware and block queue progress */
142168eb JG	470	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
0fd85869	471	clk_disable_unprepare(bs->pll_clk);
142168eb	472	clk_disable_unprepare(bs->clk);
142168eb JG	473
	474	return 0;
	475	}
	476
937ebf9c	477	#ifdef CONFIG_PM_SLEEP
142168eb JG	478	static int bcm63xx_hsspi_suspend(struct device *dev)
	479	{
	480	struct spi_master *master = dev_get_drvdata(dev);
	481	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	482
	483	spi_master_suspend(master);
0fd85869	484	clk_disable_unprepare(bs->pll_clk);
937ebf9c	485	clk_disable_unprepare(bs->clk);
142168eb JG	486
	487	return 0;
	488	}
	489
	490	static int bcm63xx_hsspi_resume(struct device *dev)
	491	{
	492	struct spi_master *master = dev_get_drvdata(dev);
	493	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
937ebf9c JG	494	int ret;
	495
	496	ret = clk_prepare_enable(bs->clk);
	497	if (ret)
	498	return ret;
142168eb	499
0fd85869 JG	500	if (bs->pll_clk) {
0fd85869 JG	501	ret = clk_prepare_enable(bs->pll_clk);
9bb9ef2b QM	502	if (ret) {
9bb9ef2b QM	503	clk_disable_unprepare(bs->clk);
0fd85869	504	return ret;
9bb9ef2b	505	}
0fd85869 JG	506	}
0fd85869 JG	507
142168eb JG	508	spi_master_resume(master);
	509
	510	return 0;
	511	}
937ebf9c	512	#endif
142168eb	513
1480916e JH	514	static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
1480916e JH	515	bcm63xx_hsspi_resume);
142168eb	516
7ab24635 JG	517	static const struct of_device_id bcm63xx_hsspi_of_match[] = {
	518	{ .compatible = "brcm,bcm6328-hsspi", },
	519	{ },
	520	};
0b85a842	521	MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
7ab24635	522
142168eb JG	523	static struct platform_driver bcm63xx_hsspi_driver = {
	524	.driver = {
	525	.name = "bcm63xx-hsspi",
937ebf9c	526	.pm = &bcm63xx_hsspi_pm_ops,
7ab24635	527	.of_match_table = bcm63xx_hsspi_of_match,
142168eb JG	528	},
	529	.probe = bcm63xx_hsspi_probe,
	530	.remove = bcm63xx_hsspi_remove,
	531	};
	532
	533	module_platform_driver(bcm63xx_hsspi_driver);
	534
	535	MODULE_ALIAS("platform:bcm63xx_hsspi");
	536	MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
	537	MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
	538	MODULE_LICENSE("GPL");