[linux-2.6-block.git] / drivers / spi / spi-bcm63xx-hsspi.c

/*
 * Broadcom BCM63XX High Speed SPI Controller driver
 *
 * Copyright 2000-2010 Broadcom Corporation
 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/mutex.h>
#include <linux/of.h>

#define HSSPI_GLOBAL_CTRL_REG			0x0
#define GLOBAL_CTRL_CS_POLARITY_SHIFT		0
#define GLOBAL_CTRL_CS_POLARITY_MASK		0x000000ff
#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT		8
#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK		0x0000ff00
#define GLOBAL_CTRL_CLK_GATE_SSOFF		BIT(16)
#define GLOBAL_CTRL_CLK_POLARITY		BIT(17)
#define GLOBAL_CTRL_MOSI_IDLE			BIT(18)

#define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4

#define HSSPI_INT_STATUS_REG			0x8
#define HSSPI_INT_STATUS_MASKED_REG		0xc
#define HSSPI_INT_MASK_REG			0x10

#define HSSPI_PINGx_CMD_DONE(i)			BIT((i * 8) + 0)
#define HSSPI_PINGx_RX_OVER(i)			BIT((i * 8) + 1)
#define HSSPI_PINGx_TX_UNDER(i)			BIT((i * 8) + 2)
#define HSSPI_PINGx_POLL_TIMEOUT(i)		BIT((i * 8) + 3)
#define HSSPI_PINGx_CTRL_INVAL(i)		BIT((i * 8) + 4)

#define HSSPI_INT_CLEAR_ALL			0xff001f1f

#define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
#define PINGPONG_CMD_COMMAND_MASK		0xf
#define PINGPONG_COMMAND_NOOP			0
#define PINGPONG_COMMAND_START_NOW		1
#define PINGPONG_COMMAND_START_TRIGGER		2
#define PINGPONG_COMMAND_HALT			3
#define PINGPONG_COMMAND_FLUSH			4
#define PINGPONG_CMD_PROFILE_SHIFT		8
#define PINGPONG_CMD_SS_SHIFT			12

#define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)

#define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
#define CLK_CTRL_FREQ_CTRL_MASK			0x0000ffff
#define CLK_CTRL_SPI_CLK_2X_SEL			BIT(14)
#define CLK_CTRL_ACCUM_RST_ON_LOOP		BIT(15)

#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
#define SIGNAL_CTRL_LATCH_RISING		BIT(12)
#define SIGNAL_CTRL_LAUNCH_RISING		BIT(13)
#define SIGNAL_CTRL_ASYNC_INPUT_PATH		BIT(16)

#define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
#define MODE_CTRL_MODE_3WIRE			BIT(20)
#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24

#define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)


#define HSSPI_OP_MULTIBIT			BIT(11)
#define HSSPI_OP_CODE_SHIFT			13
#define HSSPI_OP_SLEEP				(0 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ_WRITE			(1 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_WRITE				(2 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ				(3 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_SETIRQ				(4 << HSSPI_OP_CODE_SHIFT)

#define HSSPI_BUFFER_LEN			512
#define HSSPI_OPCODE_LEN			2

#define HSSPI_MAX_PREPEND_LEN			15

#define HSSPI_MAX_SYNC_CLOCK			30000000

#define HSSPI_SPI_MAX_CS			8
#define HSSPI_BUS_NUM				1 /* 0 is legacy SPI */

struct bcm63xx_hsspi {
	struct completion done;
	struct mutex bus_mutex;

	struct platform_device *pdev;
	struct clk *clk;
	struct clk *pll_clk;
	void __iomem *regs;
	u8 __iomem *fifo;

	u32 speed_hz;
	u8 cs_polarity;
};

static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
				 bool active)
{
	u32 reg;

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

	reg &= ~BIT(cs);
	if (active == !(bs->cs_polarity & BIT(cs)))
		reg |= BIT(cs);

	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);
}

static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
				  struct spi_device *spi, int hz)
{
	unsigned int profile = spi->chip_select;
	u32 reg;

	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
		     bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));

	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	if (hz > HSSPI_MAX_SYNC_CLOCK)
		reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
	else
		reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));

	mutex_lock(&bs->bus_mutex);
	/* setup clock polarity */
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
	if (spi->mode & SPI_CPOL)
		reg |= GLOBAL_CTRL_CLK_POLARITY;
	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);
}

static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	unsigned int chip_select = spi->chip_select;
	u16 opcode = 0;
	int pending = t->len;
	int step_size = HSSPI_BUFFER_LEN;
	const u8 *tx = t->tx_buf;
	u8 *rx = t->rx_buf;

	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);

	if (tx && rx)
		opcode = HSSPI_OP_READ_WRITE;
	else if (tx)
		opcode = HSSPI_OP_WRITE;
	else if (rx)
		opcode = HSSPI_OP_READ;

	if (opcode != HSSPI_OP_READ)
		step_size -= HSSPI_OPCODE_LEN;

	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
	    (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
		opcode |= HSSPI_OP_MULTIBIT;

	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
		     1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
		     bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));

	while (pending > 0) {
		int curr_step = min_t(int, step_size, pending);

		reinit_completion(&bs->done);
		if (tx) {
			memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
			tx += curr_step;
		}

		__raw_writew(opcode | curr_step, bs->fifo);

		/* enable interrupt */
		__raw_writel(HSSPI_PINGx_CMD_DONE(0),
			     bs->regs + HSSPI_INT_MASK_REG);

		/* start the transfer */
		__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
			     chip_select << PINGPONG_CMD_PROFILE_SHIFT |
			     PINGPONG_COMMAND_START_NOW,
			     bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));

		if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
			dev_err(&bs->pdev->dev, "transfer timed out!\n");
			return -ETIMEDOUT;
		}

		if (rx) {
			memcpy_fromio(rx, bs->fifo, curr_step);
			rx += curr_step;
		}

		pending -= curr_step;
	}

	return 0;
}

static int bcm63xx_hsspi_setup(struct spi_device *spi)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	u32 reg;

	reg = __raw_readl(bs->regs +
			  HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
	if (spi->mode & SPI_CPHA)
		reg |= SIGNAL_CTRL_LAUNCH_RISING;
	else
		reg |= SIGNAL_CTRL_LATCH_RISING;
	__raw_writel(reg, bs->regs +
		     HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

	/* only change actual polarities if there is no transfer */
	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
		if (spi->mode & SPI_CS_HIGH)
			reg |= BIT(spi->chip_select);
		else
			reg &= ~BIT(spi->chip_select);
		__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	}

	if (spi->mode & SPI_CS_HIGH)
		bs->cs_polarity |= BIT(spi->chip_select);
	else
		bs->cs_polarity &= ~BIT(spi->chip_select);

	mutex_unlock(&bs->bus_mutex);

	return 0;
}

static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
				      struct spi_message *msg)
{
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t;
	struct spi_device *spi = msg->spi;
	int status = -EINVAL;
	int dummy_cs;
	u32 reg;

	/* This controller does not support keeping CS active during idle.
	 * To work around this, we use the following ugly hack:
	 *
	 * a. Invert the target chip select's polarity so it will be active.
	 * b. Select a "dummy" chip select to use as the hardware target.
	 * c. Invert the dummy chip select's polarity so it will be inactive
	 *    during the actual transfers.
	 * d. Tell the hardware to send to the dummy chip select. Thanks to
	 *    the multiplexed nature of SPI the actual target will receive
	 *    the transfer and we see its response.
	 *
	 * e. At the end restore the polarities again to their default values.
	 */

	dummy_cs = !spi->chip_select;
	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);

	list_for_each_entry(t, &msg->transfers, transfer_list) {
		status = bcm63xx_hsspi_do_txrx(spi, t);
		if (status)
			break;

		msg->actual_length += t->len;

		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (t->cs_change)
			bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
	}

	mutex_lock(&bs->bus_mutex);
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
	reg |= bs->cs_polarity;
	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	mutex_unlock(&bs->bus_mutex);

	msg->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
{
	struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;

	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
		return IRQ_NONE;

	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);

	complete(&bs->done);

	return IRQ_HANDLED;
}

static int bcm63xx_hsspi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm63xx_hsspi *bs;
	struct resource *res_mem;
	void __iomem *regs;
	struct device *dev = &pdev->dev;
	struct clk *clk, *pll_clk = NULL;
	int irq, ret;
	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq: %d\n", irq);
		return irq;
	}

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(dev, res_mem);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	clk = devm_clk_get(dev, "hsspi");

	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	rate = clk_get_rate(clk);
	if (!rate) {
		pll_clk = devm_clk_get(dev, "pll");

		if (IS_ERR(pll_clk)) {
			ret = PTR_ERR(pll_clk);
			goto out_disable_clk;
		}

		ret = clk_prepare_enable(pll_clk);
		if (ret)
			goto out_disable_clk;

		rate = clk_get_rate(pll_clk);
		clk_disable_unprepare(pll_clk);
		if (!rate) {
			ret = -EINVAL;
			goto out_disable_pll_clk;
		}
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		ret = -ENOMEM;
		goto out_disable_pll_clk;
	}

	bs = spi_master_get_devdata(master);
	bs->pdev = pdev;
	bs->clk = clk;
	bs->pll_clk = pll_clk;
	bs->regs = regs;
	bs->speed_hz = rate;
	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));

	mutex_init(&bs->bus_mutex);
	init_completion(&bs->done);

	master->dev.of_node = dev->of_node;
	if (!dev->of_node)
		master->bus_num = HSSPI_BUS_NUM;

	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	if (num_cs > 8) {
		dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
			 num_cs);
		num_cs = HSSPI_SPI_MAX_CS;
	}
	master->num_chipselect = num_cs;
	master->setup = bcm63xx_hsspi_setup;
	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
			    SPI_RX_DUAL | SPI_TX_DUAL;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);

	/* Initialize the hardware */
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);

	/* clean up any pending interrupts */
	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);

	/* read out default CS polarities */
	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
	__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
		     bs->regs + HSSPI_GLOBAL_CTRL_REG);

	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
			       pdev->name, bs);

	if (ret)
		goto out_put_master;

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret)
		goto out_put_master;

	return 0;

out_put_master:
	spi_master_put(master);
out_disable_pll_clk:
	clk_disable_unprepare(pll_clk);
out_disable_clk:
	clk_disable_unprepare(clk);
	return ret;
}


static int bcm63xx_hsspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);

	/* reset the hardware and block queue progress */
	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	clk_disable_unprepare(bs->pll_clk);
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bcm63xx_hsspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(bs->pll_clk);
	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_hsspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	if (bs->pll_clk) {
		ret = clk_prepare_enable(bs->pll_clk);
		if (ret)
			return ret;
	}

	spi_master_resume(master);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
			 bcm63xx_hsspi_resume);

static const struct of_device_id bcm63xx_hsspi_of_match[] = {
	{ .compatible = "brcm,bcm6328-hsspi", },
	{ },
};
MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);

static struct platform_driver bcm63xx_hsspi_driver = {
	.driver = {
		.name	= "bcm63xx-hsspi",
		.pm	= &bcm63xx_hsspi_pm_ops,
		.of_match_table = bcm63xx_hsspi_of_match,
	},
	.probe		= bcm63xx_hsspi_probe,
	.remove		= bcm63xx_hsspi_remove,
};

module_platform_driver(bcm63xx_hsspi_driver);

MODULE_ALIAS("platform:bcm63xx_hsspi");
MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
142168eb JG	1	/*
	2	* Broadcom BCM63XX High Speed SPI Controller driver
	3	*
	4	* Copyright 2000-2010 Broadcom Corporation
	5	* Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
	6	*
	7	* Licensed under the GNU/GPL. See COPYING for details.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/io.h>
	13	#include <linux/clk.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/delay.h>
	17	#include <linux/dma-mapping.h>
	18	#include <linux/err.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/spi/spi.h>
142168eb	21	#include <linux/mutex.h>
7ab24635	22	#include <linux/of.h>
142168eb JG	23
	24	#define HSSPI_GLOBAL_CTRL_REG 0x0
	25	#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
	26	#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
	27	#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
	28	#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
	29	#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
	30	#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
	31	#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
	32
	33	#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
	34
	35	#define HSSPI_INT_STATUS_REG 0x8
	36	#define HSSPI_INT_STATUS_MASKED_REG 0xc
	37	#define HSSPI_INT_MASK_REG 0x10
	38
	39	#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
	40	#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
	41	#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
	42	#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
	43	#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
	44
	45	#define HSSPI_INT_CLEAR_ALL 0xff001f1f
	46
	47	#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
	48	#define PINGPONG_CMD_COMMAND_MASK 0xf
	49	#define PINGPONG_COMMAND_NOOP 0
	50	#define PINGPONG_COMMAND_START_NOW 1
	51	#define PINGPONG_COMMAND_START_TRIGGER 2
	52	#define PINGPONG_COMMAND_HALT 3
	53	#define PINGPONG_COMMAND_FLUSH 4
	54	#define PINGPONG_CMD_PROFILE_SHIFT 8
	55	#define PINGPONG_CMD_SS_SHIFT 12
	56
	57	#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
	58
	59	#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
	60	#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
	61	#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
	62	#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
	63
	64	#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
	65	#define SIGNAL_CTRL_LATCH_RISING BIT(12)
	66	#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
	67	#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
	68
	69	#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
	70	#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
	71	#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
	72	#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
	73	#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
	74	#define MODE_CTRL_MODE_3WIRE BIT(20)
	75	#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
	76
	77	#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
	78
	79
f4d86223	80	#define HSSPI_OP_MULTIBIT BIT(11)
142168eb JG	81	#define HSSPI_OP_CODE_SHIFT 13
	82	#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
	83	#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
	84	#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
	85	#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
	86	#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
	87
	88	#define HSSPI_BUFFER_LEN 512
	89	#define HSSPI_OPCODE_LEN 2
	90
	91	#define HSSPI_MAX_PREPEND_LEN 15
	92
	93	#define HSSPI_MAX_SYNC_CLOCK 30000000
	94
7ab24635	95	#define HSSPI_SPI_MAX_CS 8
142168eb JG	96	#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
	97
	98	struct bcm63xx_hsspi {
	99	struct completion done;
	100	struct mutex bus_mutex;
	101
	102	struct platform_device *pdev;
	103	struct clk *clk;
0fd85869	104	struct clk *pll_clk;
142168eb JG	105	void __iomem *regs;
	106	u8 __iomem *fifo;
	107
	108	u32 speed_hz;
	109	u8 cs_polarity;
	110	};
	111
c3c25ea7	112	static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
142168eb JG	113	bool active)
	114	{
	115	u32 reg;
	116
	117	mutex_lock(&bs->bus_mutex);
	118	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	119
	120	reg &= ~BIT(cs);
	121	if (active == !(bs->cs_polarity & BIT(cs)))
	122	reg \|= BIT(cs);
	123
	124	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	125	mutex_unlock(&bs->bus_mutex);
	126	}
	127
	128	static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
	129	struct spi_device *spi, int hz)
	130	{
c3c25ea7	131	unsigned int profile = spi->chip_select;
142168eb JG	132	u32 reg;
	133
	134	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
	135	__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP \| reg,
	136	bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
	137
	138	reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	139	if (hz > HSSPI_MAX_SYNC_CLOCK)
	140	reg \|= SIGNAL_CTRL_ASYNC_INPUT_PATH;
	141	else
	142	reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
	143	__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
	144
	145	mutex_lock(&bs->bus_mutex);
	146	/* setup clock polarity */
	147	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	148	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
	149	if (spi->mode & SPI_CPOL)
	150	reg \|= GLOBAL_CTRL_CLK_POLARITY;
	151	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	152	mutex_unlock(&bs->bus_mutex);
	153	}
	154
	155	static int bcm63xx_hsspi_do_txrx(struct spi_device spi, struct spi_transfer t)
	156	{
	157	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
c3c25ea7	158	unsigned int chip_select = spi->chip_select;
142168eb JG	159	u16 opcode = 0;
	160	int pending = t->len;
	161	int step_size = HSSPI_BUFFER_LEN;
	162	const u8 *tx = t->tx_buf;
	163	u8 *rx = t->rx_buf;
	164
	165	bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
	166	bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
	167
	168	if (tx && rx)
	169	opcode = HSSPI_OP_READ_WRITE;
	170	else if (tx)
	171	opcode = HSSPI_OP_WRITE;
	172	else if (rx)
	173	opcode = HSSPI_OP_READ;
	174
	175	if (opcode != HSSPI_OP_READ)
	176	step_size -= HSSPI_OPCODE_LEN;
	177
f4d86223 JG	178	if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) \|\|
	179	(opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
	180	opcode \|= HSSPI_OP_MULTIBIT;
	181
	182	__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT \|
	183	1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT \| 0xff,
142168eb JG	184	bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
	185
	186	while (pending > 0) {
	187	int curr_step = min_t(int, step_size, pending);
	188
aa0fe826	189	reinit_completion(&bs->done);
142168eb JG	190	if (tx) {
	191	memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
	192	tx += curr_step;
	193	}
	194
	195	__raw_writew(opcode \| curr_step, bs->fifo);
	196
	197	/* enable interrupt */
	198	__raw_writel(HSSPI_PINGx_CMD_DONE(0),
	199	bs->regs + HSSPI_INT_MASK_REG);
	200
	201	/* start the transfer */
	202	__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT \|
	203	chip_select << PINGPONG_CMD_PROFILE_SHIFT \|
	204	PINGPONG_COMMAND_START_NOW,
	205	bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
	206
	207	if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
	208	dev_err(&bs->pdev->dev, "transfer timed out!\n");
	209	return -ETIMEDOUT;
	210	}
	211
	212	if (rx) {
	213	memcpy_fromio(rx, bs->fifo, curr_step);
	214	rx += curr_step;
	215	}
	216
	217	pending -= curr_step;
	218	}
	219
	220	return 0;
	221	}
	222
	223	static int bcm63xx_hsspi_setup(struct spi_device *spi)
	224	{
	225	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
	226	u32 reg;
	227
	228	reg = __raw_readl(bs->regs +
	229	HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	230	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING \| SIGNAL_CTRL_LATCH_RISING);
	231	if (spi->mode & SPI_CPHA)
	232	reg \|= SIGNAL_CTRL_LAUNCH_RISING;
	233	else
	234	reg \|= SIGNAL_CTRL_LATCH_RISING;
	235	__raw_writel(reg, bs->regs +
	236	HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
	237
	238	mutex_lock(&bs->bus_mutex);
	239	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	240
	241	/* only change actual polarities if there is no transfer */
	242	if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
	243	if (spi->mode & SPI_CS_HIGH)
	244	reg \|= BIT(spi->chip_select);
	245	else
	246	reg &= ~BIT(spi->chip_select);
	247	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
	248	}
	249
	250	if (spi->mode & SPI_CS_HIGH)
	251	bs->cs_polarity \|= BIT(spi->chip_select);
	252	else
	253	bs->cs_polarity &= ~BIT(spi->chip_select);
254
255	mutex_unlock(&bs->bus_mutex);
256
257	return 0;
258	}
259
260	static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
261	struct spi_message *msg)
262	{
263	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
264	struct spi_transfer *t;
265	struct spi_device *spi = msg->spi;
266	int status = -EINVAL;
267	int dummy_cs;
268	u32 reg;
269
270	/* This controller does not support keeping CS active during idle.
271	* To work around this, we use the following ugly hack:
272	*
273	* a. Invert the target chip select's polarity so it will be active.
274	* b. Select a "dummy" chip select to use as the hardware target.
275	* c. Invert the dummy chip select's polarity so it will be inactive
276	* during the actual transfers.
277	* d. Tell the hardware to send to the dummy chip select. Thanks to
278	* the multiplexed nature of SPI the actual target will receive
279	* the transfer and we see its response.
280	*
281	* e. At the end restore the polarities again to their default values.
282	*/
283
284	dummy_cs = !spi->chip_select;
285	bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
286
287	list_for_each_entry(t, &msg->transfers, transfer_list) {
288	status = bcm63xx_hsspi_do_txrx(spi, t);
289	if (status)
290	break;
291
292	msg->actual_length += t->len;
293
294	if (t->delay_usecs)
295	udelay(t->delay_usecs);
296
297	if (t->cs_change)
298	bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
299	}
300
301	mutex_lock(&bs->bus_mutex);
302	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
303	reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
304	reg \|= bs->cs_polarity;
305	__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
306	mutex_unlock(&bs->bus_mutex);
307
308	msg->status = status;
309	spi_finalize_current_message(master);
310
311	return 0;
312	}
313
314	static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
315	{
316	struct bcm63xx_hsspi bs = (struct bcm63xx_hsspi )dev_id;
317
318	if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
319	return IRQ_NONE;
320
321	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
322	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
323
324	complete(&bs->done);
325
326	return IRQ_HANDLED;
327	}
328
329	static int bcm63xx_hsspi_probe(struct platform_device *pdev)
330	{
331	struct spi_master *master;
332	struct bcm63xx_hsspi *bs;
333	struct resource *res_mem;
334	void __iomem *regs;
335	struct device *dev = &pdev->dev;
0fd85869	336	struct clk clk, pll_clk = NULL;
142168eb	337	int irq, ret;
7ab24635	338	u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
142168eb JG	339
	340	irq = platform_get_irq(pdev, 0);
	341	if (irq < 0) {
378da4a6 GS	342	dev_err(dev, "no irq: %d\n", irq);
378da4a6 GS	343	return irq;
142168eb JG	344	}
	345
	346	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
87917528	347	regs = devm_ioremap_resource(dev, res_mem);
142168eb JG	348	if (IS_ERR(regs))
	349	return PTR_ERR(regs);
	350
b1bdd4f8	351	clk = devm_clk_get(dev, "hsspi");
142168eb JG	352
	353	if (IS_ERR(clk))
	354	return PTR_ERR(clk);
	355
0d7412ed SP	356	ret = clk_prepare_enable(clk);
	357	if (ret)
	358	return ret;
	359
142168eb	360	rate = clk_get_rate(clk);
ff18e1ef	361	if (!rate) {
0fd85869	362	pll_clk = devm_clk_get(dev, "pll");
ff18e1ef	363
0d7412ed SP	364	if (IS_ERR(pll_clk)) {
	365	ret = PTR_ERR(pll_clk);
	366	goto out_disable_clk;
	367	}
	368
	369	ret = clk_prepare_enable(pll_clk);
	370	if (ret)
	371	goto out_disable_clk;
ff18e1ef JG	372
ff18e1ef JG	373	rate = clk_get_rate(pll_clk);
0d7412ed SP	374	clk_disable_unprepare(pll_clk);
	375	if (!rate) {
	376	ret = -EINVAL;
0fd85869	377	goto out_disable_pll_clk;
0d7412ed	378	}
ff18e1ef	379	}
142168eb	380
142168eb JG	381	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	382	if (!master) {
	383	ret = -ENOMEM;
0fd85869	384	goto out_disable_pll_clk;
142168eb JG	385	}
	386
	387	bs = spi_master_get_devdata(master);
	388	bs->pdev = pdev;
	389	bs->clk = clk;
0fd85869	390	bs->pll_clk = pll_clk;
142168eb JG	391	bs->regs = regs;
	392	bs->speed_hz = rate;
	393	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
	394
	395	mutex_init(&bs->bus_mutex);
aa0fe826	396	init_completion(&bs->done);
142168eb	397
7ab24635 JG	398	master->dev.of_node = dev->of_node;
	399	if (!dev->of_node)
	400	master->bus_num = HSSPI_BUS_NUM;
	401
	402	of_property_read_u32(dev->of_node, "num-cs", &num_cs);
	403	if (num_cs > 8) {
	404	dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
	405	num_cs);
	406	num_cs = HSSPI_SPI_MAX_CS;
	407	}
	408	master->num_chipselect = num_cs;
142168eb JG	409	master->setup = bcm63xx_hsspi_setup;
142168eb JG	410	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
f4d86223 JG	411	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \|
f4d86223 JG	412	SPI_RX_DUAL \| SPI_TX_DUAL;
142168eb JG	413	master->bits_per_word_mask = SPI_BPW_MASK(8);
	414	master->auto_runtime_pm = true;
	415
	416	platform_set_drvdata(pdev, master);
	417
	418	/* Initialize the hardware */
	419	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
	420
	421	/* clean up any pending interrupts */
	422	__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
	423
	424	/* read out default CS polarities */
	425	reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
	426	bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
	427	__raw_writel(reg \| GLOBAL_CTRL_CLK_GATE_SSOFF,
	428	bs->regs + HSSPI_GLOBAL_CTRL_REG);
	429
	430	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
	431	pdev->name, bs);
	432
	433	if (ret)
	434	goto out_put_master;
	435
	436	/* register and we are done */
7d255695	437	ret = devm_spi_register_master(dev, master);
142168eb JG	438	if (ret)
	439	goto out_put_master;
	440
	441	return 0;
	442
	443	out_put_master:
	444	spi_master_put(master);
0fd85869 JG	445	out_disable_pll_clk:
0fd85869 JG	446	clk_disable_unprepare(pll_clk);
142168eb JG	447	out_disable_clk:
142168eb JG	448	clk_disable_unprepare(clk);
142168eb JG	449	return ret;
	450	}
	451
	452
	453	static int bcm63xx_hsspi_remove(struct platform_device *pdev)
	454	{
	455	struct spi_master *master = platform_get_drvdata(pdev);
	456	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	457
142168eb JG	458	/* reset the hardware and block queue progress */
142168eb JG	459	__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
0fd85869	460	clk_disable_unprepare(bs->pll_clk);
142168eb	461	clk_disable_unprepare(bs->clk);
142168eb JG	462
	463	return 0;
	464	}
	465
937ebf9c	466	#ifdef CONFIG_PM_SLEEP
142168eb JG	467	static int bcm63xx_hsspi_suspend(struct device *dev)
	468	{
	469	struct spi_master *master = dev_get_drvdata(dev);
	470	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
	471
	472	spi_master_suspend(master);
0fd85869	473	clk_disable_unprepare(bs->pll_clk);
937ebf9c	474	clk_disable_unprepare(bs->clk);
142168eb JG	475
	476	return 0;
	477	}
	478
	479	static int bcm63xx_hsspi_resume(struct device *dev)
	480	{
	481	struct spi_master *master = dev_get_drvdata(dev);
	482	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
937ebf9c JG	483	int ret;
	484
	485	ret = clk_prepare_enable(bs->clk);
	486	if (ret)
	487	return ret;
142168eb	488
0fd85869 JG	489	if (bs->pll_clk) {
	490	ret = clk_prepare_enable(bs->pll_clk);
	491	if (ret)
	492	return ret;
	493	}
	494
142168eb JG	495	spi_master_resume(master);
	496
	497	return 0;
	498	}
937ebf9c	499	#endif
142168eb	500
1480916e JH	501	static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
1480916e JH	502	bcm63xx_hsspi_resume);
142168eb	503
7ab24635 JG	504	static const struct of_device_id bcm63xx_hsspi_of_match[] = {
	505	{ .compatible = "brcm,bcm6328-hsspi", },
	506	{ },
	507	};
0b85a842	508	MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
7ab24635	509
142168eb JG	510	static struct platform_driver bcm63xx_hsspi_driver = {
	511	.driver = {
	512	.name = "bcm63xx-hsspi",
937ebf9c	513	.pm = &bcm63xx_hsspi_pm_ops,
7ab24635	514	.of_match_table = bcm63xx_hsspi_of_match,
142168eb JG	515	},
	516	.probe = bcm63xx_hsspi_probe,
	517	.remove = bcm63xx_hsspi_remove,
	518	};
	519
	520	module_platform_driver(bcm63xx_hsspi_driver);
	521
	522	MODULE_ALIAS("platform:bcm63xx_hsspi");
	523	MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
	524	MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
	525	MODULE_LICENSE("GPL");