Commit | Line | Data |
---|---|---|
1ea29b39 MS |
1 | /* |
2 | * Driver for Broadcom BCM2835 auxiliary SPI Controllers | |
3 | * | |
4 | * the driver does not rely on the native chipselects at all | |
5 | * but only uses the gpio type chipselects | |
6 | * | |
7 | * Based on: spi-bcm2835.c | |
8 | * | |
9 | * Copyright (C) 2015 Martin Sperl | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
21 | ||
22 | #include <linux/clk.h> | |
23 | #include <linux/completion.h> | |
8048d151 | 24 | #include <linux/debugfs.h> |
1ea29b39 MS |
25 | #include <linux/delay.h> |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/of.h> | |
32 | #include <linux/of_address.h> | |
33 | #include <linux/of_device.h> | |
34 | #include <linux/of_gpio.h> | |
35 | #include <linux/of_irq.h> | |
36 | #include <linux/regmap.h> | |
37 | #include <linux/spi/spi.h> | |
38 | #include <linux/spinlock.h> | |
39 | ||
5fd917af | 40 | /* define polling limits */ |
1a8fa516 | 41 | static unsigned int polling_limit_us = 30; |
5fd917af MS |
42 | module_param(polling_limit_us, uint, 0664); |
43 | MODULE_PARM_DESC(polling_limit_us, | |
44 | "time in us to run a transfer in polling mode - if zero no polling is used\n"); | |
45 | ||
1ea29b39 MS |
46 | /* |
47 | * spi register defines | |
48 | * | |
49 | * note there is garbage in the "official" documentation, | |
50 | * so some data is taken from the file: | |
51 | * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h | |
52 | * inside of: | |
53 | * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz | |
54 | */ | |
55 | ||
56 | /* SPI register offsets */ | |
57 | #define BCM2835_AUX_SPI_CNTL0 0x00 | |
58 | #define BCM2835_AUX_SPI_CNTL1 0x04 | |
59 | #define BCM2835_AUX_SPI_STAT 0x08 | |
60 | #define BCM2835_AUX_SPI_PEEK 0x0C | |
61 | #define BCM2835_AUX_SPI_IO 0x20 | |
62 | #define BCM2835_AUX_SPI_TXHOLD 0x30 | |
63 | ||
64 | /* Bitfields in CNTL0 */ | |
65 | #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 | |
66 | #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF | |
67 | #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 | |
68 | #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 | |
69 | #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 | |
70 | #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 | |
71 | #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 | |
72 | #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 | |
73 | #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 | |
e9dd4edc | 74 | #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 |
1ea29b39 | 75 | #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 |
e9dd4edc | 76 | #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 |
1ea29b39 MS |
77 | #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 |
78 | #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 | |
79 | #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F | |
80 | ||
81 | /* Bitfields in CNTL1 */ | |
82 | #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 | |
fe0e2304 SO |
83 | #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 |
84 | #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 | |
1ea29b39 MS |
85 | #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 |
86 | #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 | |
87 | ||
88 | /* Bitfields in STAT */ | |
89 | #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 | |
90 | #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 | |
91 | #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 | |
92 | #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 | |
93 | #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 | |
94 | #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 | |
95 | #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 | |
96 | #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F | |
97 | ||
1ea29b39 MS |
98 | struct bcm2835aux_spi { |
99 | void __iomem *regs; | |
100 | struct clk *clk; | |
101 | int irq; | |
102 | u32 cntl[2]; | |
103 | const u8 *tx_buf; | |
104 | u8 *rx_buf; | |
105 | int tx_len; | |
106 | int rx_len; | |
72aac02b | 107 | int pending; |
8048d151 MS |
108 | |
109 | u64 count_transfer_polling; | |
110 | u64 count_transfer_irq; | |
111 | u64 count_transfer_irq_after_poll; | |
112 | ||
113 | struct dentry *debugfs_dir; | |
1ea29b39 MS |
114 | }; |
115 | ||
8048d151 MS |
116 | #if defined(CONFIG_DEBUG_FS) |
117 | static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, | |
118 | const char *dname) | |
119 | { | |
120 | char name[64]; | |
121 | struct dentry *dir; | |
122 | ||
123 | /* get full name */ | |
124 | snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); | |
125 | ||
126 | /* the base directory */ | |
127 | dir = debugfs_create_dir(name, NULL); | |
128 | bs->debugfs_dir = dir; | |
129 | ||
130 | /* the counters */ | |
131 | debugfs_create_u64("count_transfer_polling", 0444, dir, | |
132 | &bs->count_transfer_polling); | |
133 | debugfs_create_u64("count_transfer_irq", 0444, dir, | |
134 | &bs->count_transfer_irq); | |
135 | debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir, | |
136 | &bs->count_transfer_irq_after_poll); | |
137 | } | |
138 | ||
139 | static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) | |
140 | { | |
141 | debugfs_remove_recursive(bs->debugfs_dir); | |
142 | bs->debugfs_dir = NULL; | |
143 | } | |
144 | #else | |
9b186e9a Y |
145 | static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs, |
146 | const char *dname) | |
8048d151 MS |
147 | { |
148 | } | |
149 | ||
150 | static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs) | |
151 | { | |
152 | } | |
153 | #endif /* CONFIG_DEBUG_FS */ | |
154 | ||
1ea29b39 MS |
155 | static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) |
156 | { | |
157 | return readl(bs->regs + reg); | |
158 | } | |
159 | ||
160 | static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, | |
161 | u32 val) | |
162 | { | |
163 | writel(val, bs->regs + reg); | |
164 | } | |
165 | ||
166 | static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) | |
167 | { | |
168 | u32 data; | |
1ea29b39 MS |
169 | int count = min(bs->rx_len, 3); |
170 | ||
171 | data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); | |
172 | if (bs->rx_buf) { | |
72aac02b | 173 | switch (count) { |
72aac02b MS |
174 | case 3: |
175 | *bs->rx_buf++ = (data >> 16) & 0xff; | |
176 | /* fallthrough */ | |
177 | case 2: | |
178 | *bs->rx_buf++ = (data >> 8) & 0xff; | |
179 | /* fallthrough */ | |
180 | case 1: | |
181 | *bs->rx_buf++ = (data >> 0) & 0xff; | |
182 | /* fallthrough - no default */ | |
183 | } | |
1ea29b39 MS |
184 | } |
185 | bs->rx_len -= count; | |
72aac02b | 186 | bs->pending -= count; |
1ea29b39 MS |
187 | } |
188 | ||
189 | static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) | |
190 | { | |
191 | u32 data; | |
192 | u8 byte; | |
193 | int count; | |
194 | int i; | |
195 | ||
196 | /* gather up to 3 bytes to write to the FIFO */ | |
197 | count = min(bs->tx_len, 3); | |
198 | data = 0; | |
199 | for (i = 0; i < count; i++) { | |
200 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; | |
201 | data |= byte << (8 * (2 - i)); | |
202 | } | |
203 | ||
204 | /* and set the variable bit-length */ | |
205 | data |= (count * 8) << 24; | |
206 | ||
207 | /* and decrement length */ | |
208 | bs->tx_len -= count; | |
72aac02b | 209 | bs->pending += count; |
1ea29b39 MS |
210 | |
211 | /* write to the correct TX-register */ | |
212 | if (bs->tx_len) | |
213 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); | |
214 | else | |
215 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); | |
216 | } | |
217 | ||
218 | static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) | |
219 | { | |
220 | /* disable spi clearing fifo and interrupts */ | |
221 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); | |
222 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, | |
223 | BCM2835_AUX_SPI_CNTL0_CLEARFIFO); | |
224 | } | |
225 | ||
7188a6f0 | 226 | static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs) |
1ea29b39 | 227 | { |
73b114ee MS |
228 | u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); |
229 | ||
1ea29b39 | 230 | /* check if we have data to read */ |
73b114ee MS |
231 | for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL); |
232 | stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT)) | |
1ea29b39 | 233 | bcm2835aux_rd_fifo(bs); |
1ea29b39 MS |
234 | |
235 | /* check if we have data to write */ | |
236 | while (bs->tx_len && | |
72aac02b | 237 | (bs->pending < 12) && |
1ea29b39 MS |
238 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
239 | BCM2835_AUX_SPI_STAT_TX_FULL))) { | |
240 | bcm2835aux_wr_fifo(bs); | |
1ea29b39 | 241 | } |
7188a6f0 MS |
242 | } |
243 | ||
244 | static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) | |
245 | { | |
246 | struct spi_master *master = dev_id; | |
247 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
248 | ||
249 | /* IRQ may be shared, so return if our interrupts are disabled */ | |
250 | if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & | |
251 | (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) | |
252 | return IRQ_NONE; | |
253 | ||
254 | /* do common fifo handling */ | |
255 | bcm2835aux_spi_transfer_helper(bs); | |
1ea29b39 | 256 | |
f29ab184 SO |
257 | if (!bs->tx_len) { |
258 | /* disable tx fifo empty interrupt */ | |
259 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | | |
260 | BCM2835_AUX_SPI_CNTL1_IDLE); | |
261 | } | |
262 | ||
b4e2adef | 263 | /* and if rx_len is 0 then disable interrupts and wake up completion */ |
1ea29b39 | 264 | if (!bs->rx_len) { |
b4e2adef | 265 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
1ea29b39 MS |
266 | complete(&master->xfer_completion); |
267 | } | |
268 | ||
7188a6f0 | 269 | return IRQ_HANDLED; |
1ea29b39 MS |
270 | } |
271 | ||
272 | static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, | |
273 | struct spi_device *spi, | |
274 | struct spi_transfer *tfr) | |
275 | { | |
276 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
277 | ||
278 | /* enable interrupts */ | |
279 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | | |
280 | BCM2835_AUX_SPI_CNTL1_TXEMPTY | | |
281 | BCM2835_AUX_SPI_CNTL1_IDLE); | |
282 | ||
283 | /* and wait for finish... */ | |
284 | return 1; | |
285 | } | |
286 | ||
287 | static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, | |
288 | struct spi_device *spi, | |
289 | struct spi_transfer *tfr) | |
290 | { | |
291 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
292 | ||
8048d151 MS |
293 | /* update statistics */ |
294 | bs->count_transfer_irq++; | |
295 | ||
1ea29b39 MS |
296 | /* fill in registers and fifos before enabling interrupts */ |
297 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); | |
298 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); | |
299 | ||
300 | /* fill in tx fifo with data before enabling interrupts */ | |
301 | while ((bs->tx_len) && | |
72aac02b | 302 | (bs->pending < 12) && |
1ea29b39 MS |
303 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
304 | BCM2835_AUX_SPI_STAT_TX_FULL))) { | |
305 | bcm2835aux_wr_fifo(bs); | |
306 | } | |
307 | ||
308 | /* now run the interrupt mode */ | |
309 | return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); | |
310 | } | |
311 | ||
312 | static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, | |
313 | struct spi_device *spi, | |
72aac02b | 314 | struct spi_transfer *tfr) |
1ea29b39 MS |
315 | { |
316 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
317 | unsigned long timeout; | |
1ea29b39 | 318 | |
8048d151 MS |
319 | /* update statistics */ |
320 | bs->count_transfer_polling++; | |
321 | ||
1ea29b39 MS |
322 | /* configure spi */ |
323 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); | |
324 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); | |
325 | ||
5fd917af MS |
326 | /* set the timeout to at least 2 jiffies */ |
327 | timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; | |
1ea29b39 MS |
328 | |
329 | /* loop until finished the transfer */ | |
330 | while (bs->rx_len) { | |
1ea29b39 | 331 | |
7188a6f0 MS |
332 | /* do common fifo handling */ |
333 | bcm2835aux_spi_transfer_helper(bs); | |
1ea29b39 MS |
334 | |
335 | /* there is still data pending to read check the timeout */ | |
336 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
337 | dev_dbg_ratelimited(&spi->dev, | |
338 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
339 | jiffies - timeout, | |
340 | bs->tx_len, bs->rx_len); | |
341 | /* forward to interrupt handler */ | |
8048d151 | 342 | bs->count_transfer_irq_after_poll++; |
1ea29b39 MS |
343 | return __bcm2835aux_spi_transfer_one_irq(master, |
344 | spi, tfr); | |
345 | } | |
346 | } | |
347 | ||
1ea29b39 MS |
348 | /* and return without waiting for completion */ |
349 | return 0; | |
350 | } | |
351 | ||
352 | static int bcm2835aux_spi_transfer_one(struct spi_master *master, | |
353 | struct spi_device *spi, | |
354 | struct spi_transfer *tfr) | |
355 | { | |
356 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
5fd917af MS |
357 | unsigned long spi_hz, clk_hz, speed, spi_used_hz; |
358 | unsigned long hz_per_byte, byte_limit; | |
1ea29b39 MS |
359 | |
360 | /* calculate the registers to handle | |
361 | * | |
362 | * note that we use the variable data mode, which | |
363 | * is not optimal for longer transfers as we waste registers | |
364 | * resulting (potentially) in more interrupts when transferring | |
365 | * more than 12 bytes | |
366 | */ | |
1ea29b39 MS |
367 | |
368 | /* set clock */ | |
369 | spi_hz = tfr->speed_hz; | |
370 | clk_hz = clk_get_rate(bs->clk); | |
371 | ||
372 | if (spi_hz >= clk_hz / 2) { | |
373 | speed = 0; | |
374 | } else if (spi_hz) { | |
375 | speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; | |
376 | if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) | |
377 | speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; | |
378 | } else { /* the slowest we can go */ | |
379 | speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; | |
380 | } | |
b4e2adef SO |
381 | /* mask out old speed from previous spi_transfer */ |
382 | bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); | |
383 | /* set the new speed */ | |
1ea29b39 MS |
384 | bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; |
385 | ||
386 | spi_used_hz = clk_hz / (2 * (speed + 1)); | |
387 | ||
1ea29b39 MS |
388 | /* set transmit buffers and length */ |
389 | bs->tx_buf = tfr->tx_buf; | |
390 | bs->rx_buf = tfr->rx_buf; | |
391 | bs->tx_len = tfr->len; | |
392 | bs->rx_len = tfr->len; | |
72aac02b | 393 | bs->pending = 0; |
1ea29b39 | 394 | |
d704afff TP |
395 | /* Calculate the estimated time in us the transfer runs. Note that |
396 | * there are are 2 idle clocks cycles after each chunk getting | |
397 | * transferred - in our case the chunk size is 3 bytes, so we | |
398 | * approximate this by 9 cycles/byte. This is used to find the number | |
399 | * of Hz per byte per polling limit. E.g., we can transfer 1 byte in | |
400 | * 30 µs per 300,000 Hz of bus clock. | |
72aac02b | 401 | */ |
5fd917af MS |
402 | hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; |
403 | byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1; | |
404 | ||
1ea29b39 | 405 | /* run in polling mode for short transfers */ |
5fd917af | 406 | if (tfr->len < byte_limit) |
72aac02b | 407 | return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); |
1ea29b39 MS |
408 | |
409 | /* run in interrupt mode for all others */ | |
410 | return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); | |
411 | } | |
412 | ||
b4e2adef SO |
413 | static int bcm2835aux_spi_prepare_message(struct spi_master *master, |
414 | struct spi_message *msg) | |
415 | { | |
416 | struct spi_device *spi = msg->spi; | |
417 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
418 | ||
419 | bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | | |
420 | BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | | |
421 | BCM2835_AUX_SPI_CNTL0_MSBF_OUT; | |
422 | bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; | |
423 | ||
424 | /* handle all the modes */ | |
e9dd4edc | 425 | if (spi->mode & SPI_CPOL) { |
b4e2adef | 426 | bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; |
e9dd4edc SO |
427 | bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; |
428 | } else { | |
429 | bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; | |
430 | } | |
b4e2adef SO |
431 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
432 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static int bcm2835aux_spi_unprepare_message(struct spi_master *master, | |
438 | struct spi_message *msg) | |
439 | { | |
440 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
441 | ||
442 | bcm2835aux_spi_reset_hw(bs); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
1ea29b39 MS |
447 | static void bcm2835aux_spi_handle_err(struct spi_master *master, |
448 | struct spi_message *msg) | |
449 | { | |
450 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
451 | ||
452 | bcm2835aux_spi_reset_hw(bs); | |
453 | } | |
454 | ||
519f2c22 MS |
455 | static int bcm2835aux_spi_setup(struct spi_device *spi) |
456 | { | |
457 | int ret; | |
458 | ||
459 | /* sanity check for native cs */ | |
460 | if (spi->mode & SPI_NO_CS) | |
461 | return 0; | |
ccd978b7 MS |
462 | if (gpio_is_valid(spi->cs_gpio)) { |
463 | /* with gpio-cs set the GPIO to the correct level | |
464 | * and as output (in case the dt has the gpio not configured | |
465 | * as output but native cs) | |
466 | */ | |
467 | ret = gpio_direction_output(spi->cs_gpio, | |
468 | (spi->mode & SPI_CS_HIGH) ? 0 : 1); | |
469 | if (ret) | |
470 | dev_err(&spi->dev, | |
471 | "could not set gpio %i as output: %i\n", | |
472 | spi->cs_gpio, ret); | |
473 | ||
474 | return ret; | |
475 | } | |
519f2c22 MS |
476 | |
477 | /* for dt-backwards compatibility: only support native on CS0 | |
478 | * known things not supported with broken native CS: | |
479 | * * multiple chip-selects: cs0-cs2 are all | |
480 | * simultaniously asserted whenever there is a transfer | |
481 | * this even includes SPI_NO_CS | |
482 | * * SPI_CS_HIGH: cs are always asserted low | |
483 | * * cs_change: cs is deasserted after each spi_transfer | |
484 | * * cs_delay_usec: cs is always deasserted one SCK cycle | |
485 | * after the last transfer | |
486 | * probably more... | |
487 | */ | |
488 | dev_warn(&spi->dev, | |
489 | "Native CS is not supported - please configure cs-gpio in device-tree\n"); | |
490 | ||
491 | if (spi->chip_select == 0) | |
492 | return 0; | |
493 | ||
494 | dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); | |
495 | ||
496 | return -EINVAL; | |
497 | } | |
498 | ||
1ea29b39 MS |
499 | static int bcm2835aux_spi_probe(struct platform_device *pdev) |
500 | { | |
501 | struct spi_master *master; | |
502 | struct bcm2835aux_spi *bs; | |
503 | struct resource *res; | |
504 | unsigned long clk_hz; | |
505 | int err; | |
506 | ||
507 | master = spi_alloc_master(&pdev->dev, sizeof(*bs)); | |
508 | if (!master) { | |
509 | dev_err(&pdev->dev, "spi_alloc_master() failed\n"); | |
510 | return -ENOMEM; | |
511 | } | |
512 | ||
513 | platform_set_drvdata(pdev, master); | |
e9dd4edc | 514 | master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); |
1ea29b39 | 515 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
509c5836 MS |
516 | /* even though the driver never officially supported native CS |
517 | * allow a single native CS for legacy DT support purposes when | |
518 | * no cs-gpio is configured. | |
519 | * Known limitations for native cs are: | |
520 | * * multiple chip-selects: cs0-cs2 are all simultaniously asserted | |
521 | * whenever there is a transfer - this even includes SPI_NO_CS | |
522 | * * SPI_CS_HIGH: is ignores - cs are always asserted low | |
523 | * * cs_change: cs is deasserted after each spi_transfer | |
524 | * * cs_delay_usec: cs is always deasserted one SCK cycle after | |
525 | * a spi_transfer | |
526 | */ | |
527 | master->num_chipselect = 1; | |
519f2c22 | 528 | master->setup = bcm2835aux_spi_setup; |
1ea29b39 MS |
529 | master->transfer_one = bcm2835aux_spi_transfer_one; |
530 | master->handle_err = bcm2835aux_spi_handle_err; | |
b4e2adef SO |
531 | master->prepare_message = bcm2835aux_spi_prepare_message; |
532 | master->unprepare_message = bcm2835aux_spi_unprepare_message; | |
1ea29b39 MS |
533 | master->dev.of_node = pdev->dev.of_node; |
534 | ||
535 | bs = spi_master_get_devdata(master); | |
536 | ||
537 | /* the main area */ | |
538 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
539 | bs->regs = devm_ioremap_resource(&pdev->dev, res); | |
540 | if (IS_ERR(bs->regs)) { | |
541 | err = PTR_ERR(bs->regs); | |
542 | goto out_master_put; | |
543 | } | |
544 | ||
545 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
bfc7af6d | 546 | if (IS_ERR(bs->clk)) { |
1ea29b39 MS |
547 | err = PTR_ERR(bs->clk); |
548 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
549 | goto out_master_put; | |
550 | } | |
551 | ||
07bce09e | 552 | bs->irq = platform_get_irq(pdev, 0); |
1ea29b39 MS |
553 | if (bs->irq <= 0) { |
554 | dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); | |
555 | err = bs->irq ? bs->irq : -ENODEV; | |
556 | goto out_master_put; | |
557 | } | |
558 | ||
559 | /* this also enables the HW block */ | |
560 | err = clk_prepare_enable(bs->clk); | |
561 | if (err) { | |
562 | dev_err(&pdev->dev, "could not prepare clock: %d\n", err); | |
563 | goto out_master_put; | |
564 | } | |
565 | ||
566 | /* just checking if the clock returns a sane value */ | |
567 | clk_hz = clk_get_rate(bs->clk); | |
568 | if (!clk_hz) { | |
569 | dev_err(&pdev->dev, "clock returns 0 Hz\n"); | |
570 | err = -ENODEV; | |
571 | goto out_clk_disable; | |
572 | } | |
573 | ||
07bce09e MS |
574 | /* reset SPI-HW block */ |
575 | bcm2835aux_spi_reset_hw(bs); | |
576 | ||
1ea29b39 MS |
577 | err = devm_request_irq(&pdev->dev, bs->irq, |
578 | bcm2835aux_spi_interrupt, | |
579 | IRQF_SHARED, | |
580 | dev_name(&pdev->dev), master); | |
581 | if (err) { | |
582 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
583 | goto out_clk_disable; | |
584 | } | |
585 | ||
1ea29b39 MS |
586 | err = devm_spi_register_master(&pdev->dev, master); |
587 | if (err) { | |
588 | dev_err(&pdev->dev, "could not register SPI master: %d\n", err); | |
589 | goto out_clk_disable; | |
590 | } | |
591 | ||
8048d151 MS |
592 | bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev)); |
593 | ||
1ea29b39 MS |
594 | return 0; |
595 | ||
596 | out_clk_disable: | |
597 | clk_disable_unprepare(bs->clk); | |
598 | out_master_put: | |
599 | spi_master_put(master); | |
600 | return err; | |
601 | } | |
602 | ||
603 | static int bcm2835aux_spi_remove(struct platform_device *pdev) | |
604 | { | |
605 | struct spi_master *master = platform_get_drvdata(pdev); | |
606 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
607 | ||
8048d151 MS |
608 | bcm2835aux_debugfs_remove(bs); |
609 | ||
1ea29b39 MS |
610 | bcm2835aux_spi_reset_hw(bs); |
611 | ||
612 | /* disable the HW block by releasing the clock */ | |
613 | clk_disable_unprepare(bs->clk); | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static const struct of_device_id bcm2835aux_spi_match[] = { | |
619 | { .compatible = "brcm,bcm2835-aux-spi", }, | |
620 | {} | |
621 | }; | |
622 | MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); | |
623 | ||
624 | static struct platform_driver bcm2835aux_spi_driver = { | |
625 | .driver = { | |
626 | .name = "spi-bcm2835aux", | |
627 | .of_match_table = bcm2835aux_spi_match, | |
628 | }, | |
629 | .probe = bcm2835aux_spi_probe, | |
630 | .remove = bcm2835aux_spi_remove, | |
631 | }; | |
632 | module_platform_driver(bcm2835aux_spi_driver); | |
633 | ||
634 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); | |
635 | MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); | |
22bf6cd2 | 636 | MODULE_LICENSE("GPL"); |