[linux-2.6-block.git] / drivers / spi / spi-bcm2835aux.c

/*
 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
 *
 * the driver does not rely on the native chipselects at all
 * but only uses the gpio type chipselects
 *
 * Based on: spi-bcm2835.c
 *
 * Copyright (C) 2015 Martin Sperl
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/spinlock.h>

/* define polling limits */
static unsigned int polling_limit_us = 30;
module_param(polling_limit_us, uint, 0664);
MODULE_PARM_DESC(polling_limit_us,
		 "time in us to run a transfer in polling mode - if zero no polling is used\n");

/*
 * spi register defines
 *
 * note there is garbage in the "official" documentation,
 * so some data is taken from the file:
 *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
 * inside of:
 *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
 */

/* SPI register offsets */
#define BCM2835_AUX_SPI_CNTL0	0x00
#define BCM2835_AUX_SPI_CNTL1	0x04
#define BCM2835_AUX_SPI_STAT	0x08
#define BCM2835_AUX_SPI_PEEK	0x0C
#define BCM2835_AUX_SPI_IO	0x20
#define BCM2835_AUX_SPI_TXHOLD	0x30

/* Bitfields in CNTL0 */
#define BCM2835_AUX_SPI_CNTL0_SPEED	0xFFF00000
#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX	0xFFF
#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT	20
#define BCM2835_AUX_SPI_CNTL0_CS	0x000E0000
#define BCM2835_AUX_SPI_CNTL0_POSTINPUT	0x00010000
#define BCM2835_AUX_SPI_CNTL0_VAR_CS	0x00008000
#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000
#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD	0x00003000
#define BCM2835_AUX_SPI_CNTL0_ENABLE	0x00000800
#define BCM2835_AUX_SPI_CNTL0_IN_RISING	0x00000400
#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO	0x00000200
#define BCM2835_AUX_SPI_CNTL0_OUT_RISING	0x00000100
#define BCM2835_AUX_SPI_CNTL0_CPOL	0x00000080
#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT	0x00000040
#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F

/* Bitfields in CNTL1 */
#define BCM2835_AUX_SPI_CNTL1_CSHIGH	0x00000700
#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000080
#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000040
#define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002
#define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001

/* Bitfields in STAT */
#define BCM2835_AUX_SPI_STAT_TX_LVL	0xFF000000
#define BCM2835_AUX_SPI_STAT_RX_LVL	0x00FF0000
#define BCM2835_AUX_SPI_STAT_TX_FULL	0x00000400
#define BCM2835_AUX_SPI_STAT_TX_EMPTY	0x00000200
#define BCM2835_AUX_SPI_STAT_RX_FULL	0x00000100
#define BCM2835_AUX_SPI_STAT_RX_EMPTY	0x00000080
#define BCM2835_AUX_SPI_STAT_BUSY	0x00000040
#define BCM2835_AUX_SPI_STAT_BITCOUNT	0x0000003F

struct bcm2835aux_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	u32 cntl[2];
	const u8 *tx_buf;
	u8 *rx_buf;
	int tx_len;
	int rx_len;
	int pending;

	u64 count_transfer_polling;
	u64 count_transfer_irq;
	u64 count_transfer_irq_after_poll;

	struct dentry *debugfs_dir;
};

#if defined(CONFIG_DEBUG_FS)
static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
				      const char *dname)
{
	char name[64];
	struct dentry *dir;

	/* get full name */
	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);

	/* the base directory */
	dir = debugfs_create_dir(name, NULL);
	bs->debugfs_dir = dir;

	/* the counters */
	debugfs_create_u64("count_transfer_polling", 0444, dir,
			   &bs->count_transfer_polling);
	debugfs_create_u64("count_transfer_irq", 0444, dir,
			   &bs->count_transfer_irq);
	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
			   &bs->count_transfer_irq_after_poll);
}

static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
{
	debugfs_remove_recursive(bs->debugfs_dir);
	bs->debugfs_dir = NULL;
}
#else
static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs)
{
}

static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
{
}
#endif /* CONFIG_DEBUG_FS */

static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
				 u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	int count = min(bs->rx_len, 3);

	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	if (bs->rx_buf) {
		switch (count) {
		case 3:
			*bs->rx_buf++ = (data >> 16) & 0xff;
			/* fallthrough */
		case 2:
			*bs->rx_buf++ = (data >> 8) & 0xff;
			/* fallthrough */
		case 1:
			*bs->rx_buf++ = (data >> 0) & 0xff;
			/* fallthrough - no default */
		}
	}
	bs->rx_len -= count;
	bs->pending -= count;
}

static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	u8 byte;
	int count;
	int i;

	/* gather up to 3 bytes to write to the FIFO */
	count = min(bs->tx_len, 3);
	data = 0;
	for (i = 0; i < count; i++) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		data |= byte << (8 * (2 - i));
	}

	/* and set the variable bit-length */
	data |= (count * 8) << 24;

	/* and decrement length */
	bs->tx_len -= count;
	bs->pending += count;

	/* write to the correct TX-register */
	if (bs->tx_len)
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	else
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
}

static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
{
	/* disable spi clearing fifo and interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
		      BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
}

static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
{
	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);

	/* check if we have data to read */
	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
	     stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
		bcm2835aux_rd_fifo(bs);

	/* check if we have data to write */
	while (bs->tx_len &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}
}

static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* IRQ may be shared, so return if our interrupts are disabled */
	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
	      (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
		return IRQ_NONE;

	/* do common fifo handling */
	bcm2835aux_spi_transfer_helper(bs);

	if (!bs->tx_len) {
		/* disable tx fifo empty interrupt */
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
			BCM2835_AUX_SPI_CNTL1_IDLE);
	}

	/* and if rx_len is 0 then disable interrupts and wake up completion */
	if (!bs->rx_len) {
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
		complete(&master->xfer_completion);
	}

	return IRQ_HANDLED;
}

static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
					     struct spi_device *spi,
					     struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* enable interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
		BCM2835_AUX_SPI_CNTL1_TXEMPTY |
		BCM2835_AUX_SPI_CNTL1_IDLE);

	/* and wait for finish... */
	return 1;
}

static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
					   struct spi_device *spi,
					   struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* update statistics */
	bs->count_transfer_irq++;

	/* fill in registers and fifos before enabling interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* fill in tx fifo with data before enabling interrupts */
	while ((bs->tx_len) &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}

	/* now run the interrupt mode */
	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
}

static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
					    struct spi_device *spi,
					struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	unsigned long timeout;

	/* update statistics */
	bs->count_transfer_polling++;

	/* configure spi */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* set the timeout to at least 2 jiffies */
	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;

	/* loop until finished the transfer */
	while (bs->rx_len) {

		/* do common fifo handling */
		bcm2835aux_spi_transfer_helper(bs);

		/* there is still data pending to read check the timeout */
		if (bs->rx_len && time_after(jiffies, timeout)) {
			dev_dbg_ratelimited(&spi->dev,
					    "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
					    jiffies - timeout,
					    bs->tx_len, bs->rx_len);
			/* forward to interrupt handler */
			bs->count_transfer_irq_after_poll++;
			return __bcm2835aux_spi_transfer_one_irq(master,
							       spi, tfr);
		}
	}

	/* and return without waiting for completion */
	return 0;
}

static int bcm2835aux_spi_transfer_one(struct spi_master *master,
				       struct spi_device *spi,
				       struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	unsigned long spi_hz, clk_hz, speed, spi_used_hz;
	unsigned long hz_per_byte, byte_limit;

	/* calculate the registers to handle
	 *
	 * note that we use the variable data mode, which
	 * is not optimal for longer transfers as we waste registers
	 * resulting (potentially) in more interrupts when transferring
	 * more than 12 bytes
	 */

	/* set clock */
	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		speed = 0;
	} else if (spi_hz) {
		speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
		if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
			speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	} else { /* the slowest we can go */
		speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	}
	/* mask out old speed from previous spi_transfer */
	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
	/* set the new speed */
	bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;

	spi_used_hz = clk_hz / (2 * (speed + 1));

	/* set transmit buffers and length */
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->tx_len = tfr->len;
	bs->rx_len = tfr->len;
	bs->pending = 0;

	/* Calculate the estimated time in us the transfer runs.  Note that
	 * there are are 2 idle clocks cycles after each chunk getting
	 * transferred - in our case the chunk size is 3 bytes, so we
	 * approximate this by 9 cycles/byte.  This is used to find the number
	 * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
	 * 30 µs per 300,000 Hz of bus clock.
	 */
	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
	byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;

	/* run in polling mode for short transfers */
	if (tfr->len < byte_limit)
		return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);

	/* run in interrupt mode for all others */
	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
}

static int bcm2835aux_spi_prepare_message(struct spi_master *master,
					  struct spi_message *msg)
{
	struct spi_device *spi = msg->spi;
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
		      BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
		      BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;

	/* handle all the modes */
	if (spi->mode & SPI_CPOL) {
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
	} else {
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
	}
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	return 0;
}

static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
					    struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_spi_reset_hw(bs);

	return 0;
}

static void bcm2835aux_spi_handle_err(struct spi_master *master,
				      struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_spi_reset_hw(bs);
}

static int bcm2835aux_spi_setup(struct spi_device *spi)
{
	int ret;

	/* sanity check for native cs */
	if (spi->mode & SPI_NO_CS)
		return 0;
	if (gpio_is_valid(spi->cs_gpio)) {
		/* with gpio-cs set the GPIO to the correct level
		 * and as output (in case the dt has the gpio not configured
		 * as output but native cs)
		 */
		ret = gpio_direction_output(spi->cs_gpio,
					    (spi->mode & SPI_CS_HIGH) ? 0 : 1);
		if (ret)
			dev_err(&spi->dev,
				"could not set gpio %i as output: %i\n",
				spi->cs_gpio, ret);

		return ret;
	}

	/* for dt-backwards compatibility: only support native on CS0
	 * known things not supported with broken native CS:
	 * * multiple chip-selects: cs0-cs2 are all
	 *     simultaniously asserted whenever there is a transfer
	 *     this even includes SPI_NO_CS
	 * * SPI_CS_HIGH: cs are always asserted low
	 * * cs_change: cs is deasserted after each spi_transfer
	 * * cs_delay_usec: cs is always deasserted one SCK cycle
	 *     after the last transfer
	 * probably more...
	 */
	dev_warn(&spi->dev,
		 "Native CS is not supported - please configure cs-gpio in device-tree\n");

	if (spi->chip_select == 0)
		return 0;

	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");

	return -EINVAL;
}

static int bcm2835aux_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm2835aux_spi *bs;
	struct resource *res;
	unsigned long clk_hz;
	int err;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		dev_err(&pdev->dev, "spi_alloc_master() failed\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);
	master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	/* even though the driver never officially supported native CS
	 * allow a single native CS for legacy DT support purposes when
	 * no cs-gpio is configured.
	 * Known limitations for native cs are:
	 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
	 *     whenever there is a transfer -  this even includes SPI_NO_CS
	 * * SPI_CS_HIGH: is ignores - cs are always asserted low
	 * * cs_change: cs is deasserted after each spi_transfer
	 * * cs_delay_usec: cs is always deasserted one SCK cycle after
	 *     a spi_transfer
	 */
	master->num_chipselect = 1;
	master->setup = bcm2835aux_spi_setup;
	master->transfer_one = bcm2835aux_spi_transfer_one;
	master->handle_err = bcm2835aux_spi_handle_err;
	master->prepare_message = bcm2835aux_spi_prepare_message;
	master->unprepare_message = bcm2835aux_spi_unprepare_message;
	master->dev.of_node = pdev->dev.of_node;

	bs = spi_master_get_devdata(master);

	/* the main area */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(bs->regs)) {
		err = PTR_ERR(bs->regs);
		goto out_master_put;
	}

	bs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(bs->clk)) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		goto out_master_put;
	}

	bs->irq = platform_get_irq(pdev, 0);
	if (bs->irq <= 0) {
		dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
		err = bs->irq ? bs->irq : -ENODEV;
		goto out_master_put;
	}

	/* this also enables the HW block */
	err = clk_prepare_enable(bs->clk);
	if (err) {
		dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
		goto out_master_put;
	}

	/* just checking if the clock returns a sane value */
	clk_hz = clk_get_rate(bs->clk);
	if (!clk_hz) {
		dev_err(&pdev->dev, "clock returns 0 Hz\n");
		err = -ENODEV;
		goto out_clk_disable;
	}

	/* reset SPI-HW block */
	bcm2835aux_spi_reset_hw(bs);

	err = devm_request_irq(&pdev->dev, bs->irq,
			       bcm2835aux_spi_interrupt,
			       IRQF_SHARED,
			       dev_name(&pdev->dev), master);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		goto out_clk_disable;
	}

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
		goto out_clk_disable;
	}

	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));

	return 0;

out_clk_disable:
	clk_disable_unprepare(bs->clk);
out_master_put:
	spi_master_put(master);
	return err;
}

static int bcm2835aux_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_debugfs_remove(bs);

	bcm2835aux_spi_reset_hw(bs);

	/* disable the HW block by releasing the clock */
	clk_disable_unprepare(bs->clk);

	return 0;
}

static const struct of_device_id bcm2835aux_spi_match[] = {
	{ .compatible = "brcm,bcm2835-aux-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);

static struct platform_driver bcm2835aux_spi_driver = {
	.driver		= {
		.name		= "spi-bcm2835aux",
		.of_match_table	= bcm2835aux_spi_match,
	},
	.probe		= bcm2835aux_spi_probe,
	.remove		= bcm2835aux_spi_remove,
};
module_platform_driver(bcm2835aux_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1ea29b39 MS	1	/*
	2	* Driver for Broadcom BCM2835 auxiliary SPI Controllers
	3	*
	4	* the driver does not rely on the native chipselects at all
	5	* but only uses the gpio type chipselects
	6	*
	7	* Based on: spi-bcm2835.c
	8	*
	9	* Copyright (C) 2015 Martin Sperl
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*/
	21
	22	#include <linux/clk.h>
	23	#include <linux/completion.h>
8048d151	24	#include <linux/debugfs.h>
1ea29b39 MS	25	#include <linux/delay.h>
	26	#include <linux/err.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/io.h>
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/of.h>
	32	#include <linux/of_address.h>
	33	#include <linux/of_device.h>
	34	#include <linux/of_gpio.h>
	35	#include <linux/of_irq.h>
	36	#include <linux/regmap.h>
	37	#include <linux/spi/spi.h>
	38	#include <linux/spinlock.h>
	39
5fd917af	40	/* define polling limits */
1a8fa516	41	static unsigned int polling_limit_us = 30;
5fd917af MS	42	module_param(polling_limit_us, uint, 0664);
	43	MODULE_PARM_DESC(polling_limit_us,
	44	"time in us to run a transfer in polling mode - if zero no polling is used\n");
	45
1ea29b39 MS	46	/*
	47	* spi register defines
	48	*
	49	* note there is garbage in the "official" documentation,
	50	* so some data is taken from the file:
	51	* brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
	52	* inside of:
	53	* http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
	54	*/
	55
	56	/* SPI register offsets */
	57	#define BCM2835_AUX_SPI_CNTL0 0x00
	58	#define BCM2835_AUX_SPI_CNTL1 0x04
	59	#define BCM2835_AUX_SPI_STAT 0x08
	60	#define BCM2835_AUX_SPI_PEEK 0x0C
	61	#define BCM2835_AUX_SPI_IO 0x20
	62	#define BCM2835_AUX_SPI_TXHOLD 0x30
	63
	64	/* Bitfields in CNTL0 */
	65	#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
	66	#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
	67	#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
	68	#define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
	69	#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
	70	#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
	71	#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
	72	#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
	73	#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
e9dd4edc	74	#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
1ea29b39	75	#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
e9dd4edc	76	#define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100
1ea29b39 MS	77	#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
	78	#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
	79	#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
	80
	81	/* Bitfields in CNTL1 */
	82	#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
fe0e2304 SO	83	#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080
fe0e2304 SO	84	#define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040
1ea29b39 MS	85	#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
	86	#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
	87
	88	/* Bitfields in STAT */
	89	#define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
	90	#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
	91	#define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
	92	#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
	93	#define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
	94	#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
	95	#define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
	96	#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
	97
1ea29b39 MS	98	struct bcm2835aux_spi {
	99	void __iomem *regs;
	100	struct clk *clk;
	101	int irq;
	102	u32 cntl[2];
	103	const u8 *tx_buf;
	104	u8 *rx_buf;
	105	int tx_len;
	106	int rx_len;
72aac02b	107	int pending;
8048d151 MS	108
	109	u64 count_transfer_polling;
	110	u64 count_transfer_irq;
	111	u64 count_transfer_irq_after_poll;
	112
	113	struct dentry *debugfs_dir;
1ea29b39 MS	114	};
1ea29b39 MS	115
8048d151 MS	116	#if defined(CONFIG_DEBUG_FS)
	117	static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
	118	const char *dname)
	119	{
	120	char name[64];
	121	struct dentry *dir;
	122
	123	/* get full name */
	124	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
	125
	126	/* the base directory */
	127	dir = debugfs_create_dir(name, NULL);
	128	bs->debugfs_dir = dir;
	129
	130	/* the counters */
	131	debugfs_create_u64("count_transfer_polling", 0444, dir,
	132	&bs->count_transfer_polling);
	133	debugfs_create_u64("count_transfer_irq", 0444, dir,
	134	&bs->count_transfer_irq);
	135	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
	136	&bs->count_transfer_irq_after_poll);
	137	}
	138
	139	static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
	140	{
	141	debugfs_remove_recursive(bs->debugfs_dir);
	142	bs->debugfs_dir = NULL;
	143	}
	144	#else
	145	static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs)
	146	{
	147	}
	148
	149	static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
	150	{
	151	}
	152	#endif /* CONFIG_DEBUG_FS */
	153
1ea29b39 MS	154	static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
	155	{
	156	return readl(bs->regs + reg);
	157	}
	158
	159	static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
	160	u32 val)
	161	{
	162	writel(val, bs->regs + reg);
	163	}
	164
	165	static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
	166	{
	167	u32 data;
1ea29b39 MS	168	int count = min(bs->rx_len, 3);
	169
	170	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	171	if (bs->rx_buf) {
72aac02b	172	switch (count) {
72aac02b MS	173	case 3:
	174	*bs->rx_buf++ = (data >> 16) & 0xff;
	175	/* fallthrough */
	176	case 2:
	177	*bs->rx_buf++ = (data >> 8) & 0xff;
	178	/* fallthrough */
	179	case 1:
	180	*bs->rx_buf++ = (data >> 0) & 0xff;
	181	/* fallthrough - no default */
	182	}
1ea29b39 MS	183	}
1ea29b39 MS	184	bs->rx_len -= count;
72aac02b	185	bs->pending -= count;
1ea29b39 MS	186	}
	187
	188	static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
	189	{
	190	u32 data;
	191	u8 byte;
	192	int count;
	193	int i;
	194
	195	/* gather up to 3 bytes to write to the FIFO */
	196	count = min(bs->tx_len, 3);
	197	data = 0;
	198	for (i = 0; i < count; i++) {
	199	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
	200	data \|= byte << (8 * (2 - i));
	201	}
	202
	203	/* and set the variable bit-length */
	204	data \|= (count * 8) << 24;
	205
	206	/* and decrement length */
	207	bs->tx_len -= count;
72aac02b	208	bs->pending += count;
1ea29b39 MS	209
	210	/* write to the correct TX-register */
	211	if (bs->tx_len)
	212	bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	213	else
	214	bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
	215	}
	216
	217	static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
	218	{
	219	/* disable spi clearing fifo and interrupts */
	220	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	221	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
	222	BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
	223	}
	224
7188a6f0	225	static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
1ea29b39	226	{
73b114ee MS	227	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
73b114ee MS	228
1ea29b39	229	/* check if we have data to read */
73b114ee MS	230	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
73b114ee MS	231	stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
1ea29b39	232	bcm2835aux_rd_fifo(bs);
1ea29b39 MS	233
	234	/* check if we have data to write */
	235	while (bs->tx_len &&
72aac02b	236	(bs->pending < 12) &&
1ea29b39 MS	237	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	238	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	239	bcm2835aux_wr_fifo(bs);
1ea29b39	240	}
7188a6f0 MS	241	}
	242
	243	static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
	244	{
	245	struct spi_master *master = dev_id;
	246	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	247
	248	/* IRQ may be shared, so return if our interrupts are disabled */
	249	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
	250	(BCM2835_AUX_SPI_CNTL1_TXEMPTY \| BCM2835_AUX_SPI_CNTL1_IDLE)))
	251	return IRQ_NONE;
	252
	253	/* do common fifo handling */
	254	bcm2835aux_spi_transfer_helper(bs);
1ea29b39	255
f29ab184 SO	256	if (!bs->tx_len) {
	257	/* disable tx fifo empty interrupt */
	258	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	259	BCM2835_AUX_SPI_CNTL1_IDLE);
	260	}
	261
b4e2adef	262	/* and if rx_len is 0 then disable interrupts and wake up completion */
1ea29b39	263	if (!bs->rx_len) {
b4e2adef	264	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
1ea29b39 MS	265	complete(&master->xfer_completion);
	266	}
	267
7188a6f0	268	return IRQ_HANDLED;
1ea29b39 MS	269	}
	270
	271	static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
	272	struct spi_device *spi,
	273	struct spi_transfer *tfr)
	274	{
	275	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	276
	277	/* enable interrupts */
	278	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	279	BCM2835_AUX_SPI_CNTL1_TXEMPTY \|
	280	BCM2835_AUX_SPI_CNTL1_IDLE);
	281
	282	/* and wait for finish... */
	283	return 1;
	284	}
	285
	286	static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
	287	struct spi_device *spi,
	288	struct spi_transfer *tfr)
	289	{
	290	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	291
8048d151 MS	292	/* update statistics */
	293	bs->count_transfer_irq++;
	294
1ea29b39 MS	295	/* fill in registers and fifos before enabling interrupts */
	296	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	297	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	298
	299	/* fill in tx fifo with data before enabling interrupts */
	300	while ((bs->tx_len) &&
72aac02b	301	(bs->pending < 12) &&
1ea29b39 MS	302	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	303	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	304	bcm2835aux_wr_fifo(bs);
	305	}
	306
	307	/* now run the interrupt mode */
	308	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
	309	}
	310
	311	static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
	312	struct spi_device *spi,
72aac02b	313	struct spi_transfer *tfr)
1ea29b39 MS	314	{
	315	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	316	unsigned long timeout;
1ea29b39	317
8048d151 MS	318	/* update statistics */
	319	bs->count_transfer_polling++;
	320
1ea29b39 MS	321	/* configure spi */
	322	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	323	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	324
5fd917af MS	325	/* set the timeout to at least 2 jiffies */
5fd917af MS	326	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
1ea29b39 MS	327
	328	/* loop until finished the transfer */
	329	while (bs->rx_len) {
1ea29b39	330
7188a6f0 MS	331	/* do common fifo handling */
7188a6f0 MS	332	bcm2835aux_spi_transfer_helper(bs);
1ea29b39 MS	333
	334	/* there is still data pending to read check the timeout */
	335	if (bs->rx_len && time_after(jiffies, timeout)) {
	336	dev_dbg_ratelimited(&spi->dev,
	337	"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
	338	jiffies - timeout,
	339	bs->tx_len, bs->rx_len);
	340	/* forward to interrupt handler */
8048d151	341	bs->count_transfer_irq_after_poll++;
1ea29b39 MS	342	return __bcm2835aux_spi_transfer_one_irq(master,
	343	spi, tfr);
	344	}
	345	}
	346
1ea29b39 MS	347	/* and return without waiting for completion */
	348	return 0;
	349	}
	350
	351	static int bcm2835aux_spi_transfer_one(struct spi_master *master,
	352	struct spi_device *spi,
	353	struct spi_transfer *tfr)
	354	{
	355	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
5fd917af MS	356	unsigned long spi_hz, clk_hz, speed, spi_used_hz;
5fd917af MS	357	unsigned long hz_per_byte, byte_limit;
1ea29b39 MS	358
	359	/* calculate the registers to handle
	360	*
	361	* note that we use the variable data mode, which
	362	* is not optimal for longer transfers as we waste registers
	363	* resulting (potentially) in more interrupts when transferring
	364	* more than 12 bytes
	365	*/
1ea29b39 MS	366
	367	/* set clock */
	368	spi_hz = tfr->speed_hz;
	369	clk_hz = clk_get_rate(bs->clk);
	370
	371	if (spi_hz >= clk_hz / 2) {
	372	speed = 0;
	373	} else if (spi_hz) {
	374	speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
	375	if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
	376	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	377	} else { /* the slowest we can go */
	378	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	379	}
b4e2adef SO	380	/* mask out old speed from previous spi_transfer */
	381	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
	382	/* set the new speed */
1ea29b39 MS	383	bs->cntl[0] \|= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
	384
	385	spi_used_hz = clk_hz / (2 * (speed + 1));
	386
1ea29b39 MS	387	/* set transmit buffers and length */
	388	bs->tx_buf = tfr->tx_buf;
	389	bs->rx_buf = tfr->rx_buf;
	390	bs->tx_len = tfr->len;
	391	bs->rx_len = tfr->len;
72aac02b	392	bs->pending = 0;
1ea29b39	393
d704afff TP	394	/* Calculate the estimated time in us the transfer runs. Note that
	395	* there are are 2 idle clocks cycles after each chunk getting
	396	* transferred - in our case the chunk size is 3 bytes, so we
	397	* approximate this by 9 cycles/byte. This is used to find the number
	398	* of Hz per byte per polling limit. E.g., we can transfer 1 byte in
	399	* 30 µs per 300,000 Hz of bus clock.
72aac02b	400	*/
5fd917af MS	401	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
	402	byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;
	403
1ea29b39	404	/* run in polling mode for short transfers */
5fd917af	405	if (tfr->len < byte_limit)
72aac02b	406	return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
1ea29b39 MS	407
	408	/* run in interrupt mode for all others */
	409	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
	410	}
	411
b4e2adef SO	412	static int bcm2835aux_spi_prepare_message(struct spi_master *master,
	413	struct spi_message *msg)
	414	{
	415	struct spi_device *spi = msg->spi;
	416	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	417
	418	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE \|
	419	BCM2835_AUX_SPI_CNTL0_VAR_WIDTH \|
	420	BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	421	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
	422
	423	/* handle all the modes */
e9dd4edc	424	if (spi->mode & SPI_CPOL) {
b4e2adef	425	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_CPOL;
e9dd4edc SO	426	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
	427	} else {
	428	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_IN_RISING;
	429	}
b4e2adef SO	430	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	431	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	432
	433	return 0;
	434	}
	435
	436	static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
	437	struct spi_message *msg)
	438	{
	439	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	440
	441	bcm2835aux_spi_reset_hw(bs);
	442
	443	return 0;
	444	}
	445
1ea29b39 MS	446	static void bcm2835aux_spi_handle_err(struct spi_master *master,
	447	struct spi_message *msg)
	448	{
	449	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	450
	451	bcm2835aux_spi_reset_hw(bs);
	452	}
	453
519f2c22 MS	454	static int bcm2835aux_spi_setup(struct spi_device *spi)
	455	{
	456	int ret;
	457
	458	/* sanity check for native cs */
	459	if (spi->mode & SPI_NO_CS)
	460	return 0;
ccd978b7 MS	461	if (gpio_is_valid(spi->cs_gpio)) {
	462	/* with gpio-cs set the GPIO to the correct level
	463	* and as output (in case the dt has the gpio not configured
	464	* as output but native cs)
	465	*/
	466	ret = gpio_direction_output(spi->cs_gpio,
	467	(spi->mode & SPI_CS_HIGH) ? 0 : 1);
	468	if (ret)
	469	dev_err(&spi->dev,
	470	"could not set gpio %i as output: %i\n",
	471	spi->cs_gpio, ret);
	472
	473	return ret;
	474	}
519f2c22 MS	475
	476	/* for dt-backwards compatibility: only support native on CS0
	477	* known things not supported with broken native CS:
	478	* * multiple chip-selects: cs0-cs2 are all
	479	* simultaniously asserted whenever there is a transfer
	480	* this even includes SPI_NO_CS
	481	* * SPI_CS_HIGH: cs are always asserted low
	482	* * cs_change: cs is deasserted after each spi_transfer
	483	* * cs_delay_usec: cs is always deasserted one SCK cycle
	484	* after the last transfer
	485	* probably more...
	486	*/
	487	dev_warn(&spi->dev,
	488	"Native CS is not supported - please configure cs-gpio in device-tree\n");
	489
	490	if (spi->chip_select == 0)
	491	return 0;
	492
	493	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
	494
	495	return -EINVAL;
	496	}
	497
1ea29b39 MS	498	static int bcm2835aux_spi_probe(struct platform_device *pdev)
	499	{
	500	struct spi_master *master;
	501	struct bcm2835aux_spi *bs;
	502	struct resource *res;
	503	unsigned long clk_hz;
	504	int err;
	505
	506	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	507	if (!master) {
	508	dev_err(&pdev->dev, "spi_alloc_master() failed\n");
	509	return -ENOMEM;
	510	}
	511
	512	platform_set_drvdata(pdev, master);
e9dd4edc	513	master->mode_bits = (SPI_CPOL \| SPI_CS_HIGH \| SPI_NO_CS);
1ea29b39	514	master->bits_per_word_mask = SPI_BPW_MASK(8);
509c5836 MS	515	/* even though the driver never officially supported native CS
	516	* allow a single native CS for legacy DT support purposes when
	517	* no cs-gpio is configured.
	518	* Known limitations for native cs are:
	519	* * multiple chip-selects: cs0-cs2 are all simultaniously asserted
	520	* whenever there is a transfer - this even includes SPI_NO_CS
	521	* * SPI_CS_HIGH: is ignores - cs are always asserted low
	522	* * cs_change: cs is deasserted after each spi_transfer
	523	* * cs_delay_usec: cs is always deasserted one SCK cycle after
	524	* a spi_transfer
	525	*/
	526	master->num_chipselect = 1;
519f2c22	527	master->setup = bcm2835aux_spi_setup;
1ea29b39 MS	528	master->transfer_one = bcm2835aux_spi_transfer_one;
1ea29b39 MS	529	master->handle_err = bcm2835aux_spi_handle_err;
b4e2adef SO	530	master->prepare_message = bcm2835aux_spi_prepare_message;
b4e2adef SO	531	master->unprepare_message = bcm2835aux_spi_unprepare_message;
1ea29b39 MS	532	master->dev.of_node = pdev->dev.of_node;
	533
	534	bs = spi_master_get_devdata(master);
	535
	536	/* the main area */
	537	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	538	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	539	if (IS_ERR(bs->regs)) {
	540	err = PTR_ERR(bs->regs);
	541	goto out_master_put;
	542	}
	543
	544	bs->clk = devm_clk_get(&pdev->dev, NULL);
bfc7af6d	545	if (IS_ERR(bs->clk)) {
1ea29b39 MS	546	err = PTR_ERR(bs->clk);
	547	dev_err(&pdev->dev, "could not get clk: %d\n", err);
	548	goto out_master_put;
	549	}
	550
07bce09e	551	bs->irq = platform_get_irq(pdev, 0);
1ea29b39 MS	552	if (bs->irq <= 0) {
	553	dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
	554	err = bs->irq ? bs->irq : -ENODEV;
	555	goto out_master_put;
	556	}
	557
	558	/* this also enables the HW block */
	559	err = clk_prepare_enable(bs->clk);
	560	if (err) {
	561	dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
	562	goto out_master_put;
	563	}
	564
	565	/* just checking if the clock returns a sane value */
	566	clk_hz = clk_get_rate(bs->clk);
	567	if (!clk_hz) {
	568	dev_err(&pdev->dev, "clock returns 0 Hz\n");
	569	err = -ENODEV;
	570	goto out_clk_disable;
	571	}
	572
07bce09e MS	573	/* reset SPI-HW block */
	574	bcm2835aux_spi_reset_hw(bs);
	575
1ea29b39 MS	576	err = devm_request_irq(&pdev->dev, bs->irq,
	577	bcm2835aux_spi_interrupt,
	578	IRQF_SHARED,
	579	dev_name(&pdev->dev), master);
	580	if (err) {
	581	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
	582	goto out_clk_disable;
	583	}
	584
1ea29b39 MS	585	err = devm_spi_register_master(&pdev->dev, master);
	586	if (err) {
	587	dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
	588	goto out_clk_disable;
	589	}
	590
8048d151 MS	591	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
8048d151 MS	592
1ea29b39 MS	593	return 0;
	594
	595	out_clk_disable:
	596	clk_disable_unprepare(bs->clk);
	597	out_master_put:
	598	spi_master_put(master);
	599	return err;
	600	}
	601
	602	static int bcm2835aux_spi_remove(struct platform_device *pdev)
	603	{
	604	struct spi_master *master = platform_get_drvdata(pdev);
	605	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	606
8048d151 MS	607	bcm2835aux_debugfs_remove(bs);
8048d151 MS	608
1ea29b39 MS	609	bcm2835aux_spi_reset_hw(bs);
	610
	611	/* disable the HW block by releasing the clock */
	612	clk_disable_unprepare(bs->clk);
	613
	614	return 0;
	615	}
	616
	617	static const struct of_device_id bcm2835aux_spi_match[] = {
	618	{ .compatible = "brcm,bcm2835-aux-spi", },
	619	{}
	620	};
	621	MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
	622
	623	static struct platform_driver bcm2835aux_spi_driver = {
	624	.driver = {
	625	.name = "spi-bcm2835aux",
	626	.of_match_table = bcm2835aux_spi_match,
	627	},
	628	.probe = bcm2835aux_spi_probe,
	629	.remove = bcm2835aux_spi_remove,
	630	};
	631	module_platform_driver(bcm2835aux_spi_driver);
	632
	633	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
	634	MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
22bf6cd2	635	MODULE_LICENSE("GPL");