[linux-2.6-block.git] / drivers / spi / spi-bcm2835aux.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
 *
 * the driver does not rely on the native chipselects at all
 * but only uses the gpio type chipselects
 *
 * Based on: spi-bcm2835.c
 *
 * Copyright (C) 2015 Martin Sperl
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/spinlock.h>

/* define polling limits */
static unsigned int polling_limit_us = 30;
module_param(polling_limit_us, uint, 0664);
MODULE_PARM_DESC(polling_limit_us,
		 "time in us to run a transfer in polling mode - if zero no polling is used\n");

/*
 * spi register defines
 *
 * note there is garbage in the "official" documentation,
 * so some data is taken from the file:
 *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
 * inside of:
 *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
 */

/* SPI register offsets */
#define BCM2835_AUX_SPI_CNTL0	0x00
#define BCM2835_AUX_SPI_CNTL1	0x04
#define BCM2835_AUX_SPI_STAT	0x08
#define BCM2835_AUX_SPI_PEEK	0x0C
#define BCM2835_AUX_SPI_IO	0x20
#define BCM2835_AUX_SPI_TXHOLD	0x30

/* Bitfields in CNTL0 */
#define BCM2835_AUX_SPI_CNTL0_SPEED	0xFFF00000
#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX	0xFFF
#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT	20
#define BCM2835_AUX_SPI_CNTL0_CS	0x000E0000
#define BCM2835_AUX_SPI_CNTL0_POSTINPUT	0x00010000
#define BCM2835_AUX_SPI_CNTL0_VAR_CS	0x00008000
#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000
#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD	0x00003000
#define BCM2835_AUX_SPI_CNTL0_ENABLE	0x00000800
#define BCM2835_AUX_SPI_CNTL0_IN_RISING	0x00000400
#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO	0x00000200
#define BCM2835_AUX_SPI_CNTL0_OUT_RISING	0x00000100
#define BCM2835_AUX_SPI_CNTL0_CPOL	0x00000080
#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT	0x00000040
#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F

/* Bitfields in CNTL1 */
#define BCM2835_AUX_SPI_CNTL1_CSHIGH	0x00000700
#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000080
#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000040
#define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002
#define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001

/* Bitfields in STAT */
#define BCM2835_AUX_SPI_STAT_TX_LVL	0xFF000000
#define BCM2835_AUX_SPI_STAT_RX_LVL	0x00FF0000
#define BCM2835_AUX_SPI_STAT_TX_FULL	0x00000400
#define BCM2835_AUX_SPI_STAT_TX_EMPTY	0x00000200
#define BCM2835_AUX_SPI_STAT_RX_FULL	0x00000100
#define BCM2835_AUX_SPI_STAT_RX_EMPTY	0x00000080
#define BCM2835_AUX_SPI_STAT_BUSY	0x00000040
#define BCM2835_AUX_SPI_STAT_BITCOUNT	0x0000003F

struct bcm2835aux_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	u32 cntl[2];
	const u8 *tx_buf;
	u8 *rx_buf;
	int tx_len;
	int rx_len;
	int pending;

	u64 count_transfer_polling;
	u64 count_transfer_irq;
	u64 count_transfer_irq_after_poll;

	struct dentry *debugfs_dir;
};

#if defined(CONFIG_DEBUG_FS)
static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
				      const char *dname)
{
	char name[64];
	struct dentry *dir;

	/* get full name */
	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);

	/* the base directory */
	dir = debugfs_create_dir(name, NULL);
	bs->debugfs_dir = dir;

	/* the counters */
	debugfs_create_u64("count_transfer_polling", 0444, dir,
			   &bs->count_transfer_polling);
	debugfs_create_u64("count_transfer_irq", 0444, dir,
			   &bs->count_transfer_irq);
	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
			   &bs->count_transfer_irq_after_poll);
}

static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
{
	debugfs_remove_recursive(bs->debugfs_dir);
	bs->debugfs_dir = NULL;
}
#else
static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
				      const char *dname)
{
}

static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
{
}
#endif /* CONFIG_DEBUG_FS */

static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
				 u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	int count = min(bs->rx_len, 3);

	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	if (bs->rx_buf) {
		switch (count) {
		case 3:
			*bs->rx_buf++ = (data >> 16) & 0xff;
			/* fallthrough */
		case 2:
			*bs->rx_buf++ = (data >> 8) & 0xff;
			/* fallthrough */
		case 1:
			*bs->rx_buf++ = (data >> 0) & 0xff;
			/* fallthrough - no default */
		}
	}
	bs->rx_len -= count;
	bs->pending -= count;
}

static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	u8 byte;
	int count;
	int i;

	/* gather up to 3 bytes to write to the FIFO */
	count = min(bs->tx_len, 3);
	data = 0;
	for (i = 0; i < count; i++) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		data |= byte << (8 * (2 - i));
	}

	/* and set the variable bit-length */
	data |= (count * 8) << 24;

	/* and decrement length */
	bs->tx_len -= count;
	bs->pending += count;

	/* write to the correct TX-register */
	if (bs->tx_len)
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	else
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
}

static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
{
	/* disable spi clearing fifo and interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
		      BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
}

static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
{
	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);

	/* check if we have data to read */
	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
	     stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
		bcm2835aux_rd_fifo(bs);

	/* check if we have data to write */
	while (bs->tx_len &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}
}

static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* IRQ may be shared, so return if our interrupts are disabled */
	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
	      (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
		return IRQ_NONE;

	/* do common fifo handling */
	bcm2835aux_spi_transfer_helper(bs);

	if (!bs->tx_len) {
		/* disable tx fifo empty interrupt */
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
			BCM2835_AUX_SPI_CNTL1_IDLE);
	}

	/* and if rx_len is 0 then disable interrupts and wake up completion */
	if (!bs->rx_len) {
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
		complete(&master->xfer_completion);
	}

	return IRQ_HANDLED;
}

static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
					     struct spi_device *spi,
					     struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* enable interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
		BCM2835_AUX_SPI_CNTL1_TXEMPTY |
		BCM2835_AUX_SPI_CNTL1_IDLE);

	/* and wait for finish... */
	return 1;
}

static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
					   struct spi_device *spi,
					   struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* update statistics */
	bs->count_transfer_irq++;

	/* fill in registers and fifos before enabling interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* fill in tx fifo with data before enabling interrupts */
	while ((bs->tx_len) &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}

	/* now run the interrupt mode */
	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
}

static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
					    struct spi_device *spi,
					struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	unsigned long timeout;

	/* update statistics */
	bs->count_transfer_polling++;

	/* configure spi */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* set the timeout to at least 2 jiffies */
	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;

	/* loop until finished the transfer */
	while (bs->rx_len) {

		/* do common fifo handling */
		bcm2835aux_spi_transfer_helper(bs);

		/* there is still data pending to read check the timeout */
		if (bs->rx_len && time_after(jiffies, timeout)) {
			dev_dbg_ratelimited(&spi->dev,
					    "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
					    jiffies - timeout,
					    bs->tx_len, bs->rx_len);
			/* forward to interrupt handler */
			bs->count_transfer_irq_after_poll++;
			return __bcm2835aux_spi_transfer_one_irq(master,
							       spi, tfr);
		}
	}

	/* and return without waiting for completion */
	return 0;
}

static int bcm2835aux_spi_transfer_one(struct spi_master *master,
				       struct spi_device *spi,
				       struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	unsigned long spi_hz, clk_hz, speed, spi_used_hz;
	unsigned long hz_per_byte, byte_limit;

	/* calculate the registers to handle
	 *
	 * note that we use the variable data mode, which
	 * is not optimal for longer transfers as we waste registers
	 * resulting (potentially) in more interrupts when transferring
	 * more than 12 bytes
	 */

	/* set clock */
	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		speed = 0;
	} else if (spi_hz) {
		speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
		if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
			speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	} else { /* the slowest we can go */
		speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	}
	/* mask out old speed from previous spi_transfer */
	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
	/* set the new speed */
	bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;

	spi_used_hz = clk_hz / (2 * (speed + 1));

	/* set transmit buffers and length */
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->tx_len = tfr->len;
	bs->rx_len = tfr->len;
	bs->pending = 0;

	/* Calculate the estimated time in us the transfer runs.  Note that
	 * there are are 2 idle clocks cycles after each chunk getting
	 * transferred - in our case the chunk size is 3 bytes, so we
	 * approximate this by 9 cycles/byte.  This is used to find the number
	 * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
	 * 30 µs per 300,000 Hz of bus clock.
	 */
	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
	byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;

	/* run in polling mode for short transfers */
	if (tfr->len < byte_limit)
		return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);

	/* run in interrupt mode for all others */
	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
}

static int bcm2835aux_spi_prepare_message(struct spi_master *master,
					  struct spi_message *msg)
{
	struct spi_device *spi = msg->spi;
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
		      BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
		      BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;

	/* handle all the modes */
	if (spi->mode & SPI_CPOL) {
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
	} else {
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
	}
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	return 0;
}

static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
					    struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_spi_reset_hw(bs);

	return 0;
}

static void bcm2835aux_spi_handle_err(struct spi_master *master,
				      struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_spi_reset_hw(bs);
}

static int bcm2835aux_spi_setup(struct spi_device *spi)
{
	int ret;

	/* sanity check for native cs */
	if (spi->mode & SPI_NO_CS)
		return 0;
	if (gpio_is_valid(spi->cs_gpio)) {
		/* with gpio-cs set the GPIO to the correct level
		 * and as output (in case the dt has the gpio not configured
		 * as output but native cs)
		 */
		ret = gpio_direction_output(spi->cs_gpio,
					    (spi->mode & SPI_CS_HIGH) ? 0 : 1);
		if (ret)
			dev_err(&spi->dev,
				"could not set gpio %i as output: %i\n",
				spi->cs_gpio, ret);

		return ret;
	}

	/* for dt-backwards compatibility: only support native on CS0
	 * known things not supported with broken native CS:
	 * * multiple chip-selects: cs0-cs2 are all
	 *     simultaniously asserted whenever there is a transfer
	 *     this even includes SPI_NO_CS
	 * * SPI_CS_HIGH: cs are always asserted low
	 * * cs_change: cs is deasserted after each spi_transfer
	 * * cs_delay_usec: cs is always deasserted one SCK cycle
	 *     after the last transfer
	 * probably more...
	 */
	dev_warn(&spi->dev,
		 "Native CS is not supported - please configure cs-gpio in device-tree\n");

	if (spi->chip_select == 0)
		return 0;

	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");

	return -EINVAL;
}

static int bcm2835aux_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm2835aux_spi *bs;
	struct resource *res;
	unsigned long clk_hz;
	int err;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);
	master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	/* even though the driver never officially supported native CS
	 * allow a single native CS for legacy DT support purposes when
	 * no cs-gpio is configured.
	 * Known limitations for native cs are:
	 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
	 *     whenever there is a transfer -  this even includes SPI_NO_CS
	 * * SPI_CS_HIGH: is ignores - cs are always asserted low
	 * * cs_change: cs is deasserted after each spi_transfer
	 * * cs_delay_usec: cs is always deasserted one SCK cycle after
	 *     a spi_transfer
	 */
	master->num_chipselect = 1;
	master->setup = bcm2835aux_spi_setup;
	master->transfer_one = bcm2835aux_spi_transfer_one;
	master->handle_err = bcm2835aux_spi_handle_err;
	master->prepare_message = bcm2835aux_spi_prepare_message;
	master->unprepare_message = bcm2835aux_spi_unprepare_message;
	master->dev.of_node = pdev->dev.of_node;

	bs = spi_master_get_devdata(master);

	/* the main area */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(bs->regs)) {
		err = PTR_ERR(bs->regs);
		goto out_master_put;
	}

	bs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(bs->clk)) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		goto out_master_put;
	}

	bs->irq = platform_get_irq(pdev, 0);
	if (bs->irq <= 0) {
		dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
		err = bs->irq ? bs->irq : -ENODEV;
		goto out_master_put;
	}

	/* this also enables the HW block */
	err = clk_prepare_enable(bs->clk);
	if (err) {
		dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
		goto out_master_put;
	}

	/* just checking if the clock returns a sane value */
	clk_hz = clk_get_rate(bs->clk);
	if (!clk_hz) {
		dev_err(&pdev->dev, "clock returns 0 Hz\n");
		err = -ENODEV;
		goto out_clk_disable;
	}

	/* reset SPI-HW block */
	bcm2835aux_spi_reset_hw(bs);

	err = devm_request_irq(&pdev->dev, bs->irq,
			       bcm2835aux_spi_interrupt,
			       IRQF_SHARED,
			       dev_name(&pdev->dev), master);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		goto out_clk_disable;
	}

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
		goto out_clk_disable;
	}

	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));

	return 0;

out_clk_disable:
	clk_disable_unprepare(bs->clk);
out_master_put:
	spi_master_put(master);
	return err;
}

static int bcm2835aux_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_debugfs_remove(bs);

	bcm2835aux_spi_reset_hw(bs);

	/* disable the HW block by releasing the clock */
	clk_disable_unprepare(bs->clk);

	return 0;
}

static const struct of_device_id bcm2835aux_spi_match[] = {
	{ .compatible = "brcm,bcm2835-aux-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);

static struct platform_driver bcm2835aux_spi_driver = {
	.driver		= {
		.name		= "spi-bcm2835aux",
		.of_match_table	= bcm2835aux_spi_match,
	},
	.probe		= bcm2835aux_spi_probe,
	.remove		= bcm2835aux_spi_remove,
};
module_platform_driver(bcm2835aux_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
1ea29b39 MS	2	/*
	3	* Driver for Broadcom BCM2835 auxiliary SPI Controllers
	4	*
	5	* the driver does not rely on the native chipselects at all
	6	* but only uses the gpio type chipselects
	7	*
	8	* Based on: spi-bcm2835.c
	9	*
	10	* Copyright (C) 2015 Martin Sperl
1ea29b39 MS	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/completion.h>
8048d151	15	#include <linux/debugfs.h>
1ea29b39 MS	16	#include <linux/delay.h>
	17	#include <linux/err.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/io.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
	24	#include <linux/of_device.h>
	25	#include <linux/of_gpio.h>
	26	#include <linux/of_irq.h>
	27	#include <linux/regmap.h>
	28	#include <linux/spi/spi.h>
	29	#include <linux/spinlock.h>
	30
5fd917af	31	/* define polling limits */
1a8fa516	32	static unsigned int polling_limit_us = 30;
5fd917af MS	33	module_param(polling_limit_us, uint, 0664);
	34	MODULE_PARM_DESC(polling_limit_us,
	35	"time in us to run a transfer in polling mode - if zero no polling is used\n");
	36
1ea29b39 MS	37	/*
	38	* spi register defines
	39	*
	40	* note there is garbage in the "official" documentation,
	41	* so some data is taken from the file:
	42	* brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
	43	* inside of:
	44	* http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
	45	*/
	46
	47	/* SPI register offsets */
	48	#define BCM2835_AUX_SPI_CNTL0 0x00
	49	#define BCM2835_AUX_SPI_CNTL1 0x04
	50	#define BCM2835_AUX_SPI_STAT 0x08
	51	#define BCM2835_AUX_SPI_PEEK 0x0C
	52	#define BCM2835_AUX_SPI_IO 0x20
	53	#define BCM2835_AUX_SPI_TXHOLD 0x30
	54
	55	/* Bitfields in CNTL0 */
	56	#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
	57	#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
	58	#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
	59	#define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
	60	#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
	61	#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
	62	#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
	63	#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
	64	#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
e9dd4edc	65	#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
1ea29b39	66	#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
e9dd4edc	67	#define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100
1ea29b39 MS	68	#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
	69	#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
	70	#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
	71
	72	/* Bitfields in CNTL1 */
	73	#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
fe0e2304 SO	74	#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080
fe0e2304 SO	75	#define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040
1ea29b39 MS	76	#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
	77	#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
	78
	79	/* Bitfields in STAT */
	80	#define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
	81	#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
	82	#define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
	83	#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
	84	#define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
	85	#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
	86	#define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
	87	#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
	88
1ea29b39 MS	89	struct bcm2835aux_spi {
	90	void __iomem *regs;
	91	struct clk *clk;
	92	int irq;
	93	u32 cntl[2];
	94	const u8 *tx_buf;
	95	u8 *rx_buf;
	96	int tx_len;
	97	int rx_len;
72aac02b	98	int pending;
8048d151 MS	99
	100	u64 count_transfer_polling;
	101	u64 count_transfer_irq;
	102	u64 count_transfer_irq_after_poll;
	103
	104	struct dentry *debugfs_dir;
1ea29b39 MS	105	};
1ea29b39 MS	106
8048d151 MS	107	#if defined(CONFIG_DEBUG_FS)
	108	static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
	109	const char *dname)
	110	{
	111	char name[64];
	112	struct dentry *dir;
	113
	114	/* get full name */
	115	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
	116
	117	/* the base directory */
	118	dir = debugfs_create_dir(name, NULL);
	119	bs->debugfs_dir = dir;
	120
	121	/* the counters */
	122	debugfs_create_u64("count_transfer_polling", 0444, dir,
	123	&bs->count_transfer_polling);
	124	debugfs_create_u64("count_transfer_irq", 0444, dir,
	125	&bs->count_transfer_irq);
	126	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
	127	&bs->count_transfer_irq_after_poll);
	128	}
	129
	130	static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
	131	{
	132	debugfs_remove_recursive(bs->debugfs_dir);
	133	bs->debugfs_dir = NULL;
	134	}
	135	#else
9b186e9a Y	136	static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
9b186e9a Y	137	const char *dname)
8048d151 MS	138	{
	139	}
	140
	141	static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
	142	{
	143	}
	144	#endif /* CONFIG_DEBUG_FS */
	145
1ea29b39 MS	146	static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
	147	{
	148	return readl(bs->regs + reg);
	149	}
	150
	151	static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
	152	u32 val)
	153	{
	154	writel(val, bs->regs + reg);
	155	}
	156
	157	static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
	158	{
	159	u32 data;
1ea29b39 MS	160	int count = min(bs->rx_len, 3);
	161
	162	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	163	if (bs->rx_buf) {
72aac02b	164	switch (count) {
72aac02b MS	165	case 3:
	166	*bs->rx_buf++ = (data >> 16) & 0xff;
	167	/* fallthrough */
	168	case 2:
	169	*bs->rx_buf++ = (data >> 8) & 0xff;
	170	/* fallthrough */
	171	case 1:
	172	*bs->rx_buf++ = (data >> 0) & 0xff;
	173	/* fallthrough - no default */
	174	}
1ea29b39 MS	175	}
1ea29b39 MS	176	bs->rx_len -= count;
72aac02b	177	bs->pending -= count;
1ea29b39 MS	178	}
	179
	180	static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
	181	{
	182	u32 data;
	183	u8 byte;
	184	int count;
	185	int i;
	186
	187	/* gather up to 3 bytes to write to the FIFO */
	188	count = min(bs->tx_len, 3);
	189	data = 0;
	190	for (i = 0; i < count; i++) {
	191	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
	192	data \|= byte << (8 * (2 - i));
	193	}
	194
	195	/* and set the variable bit-length */
	196	data \|= (count * 8) << 24;
	197
	198	/* and decrement length */
	199	bs->tx_len -= count;
72aac02b	200	bs->pending += count;
1ea29b39 MS	201
	202	/* write to the correct TX-register */
	203	if (bs->tx_len)
	204	bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	205	else
	206	bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
	207	}
	208
	209	static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
	210	{
	211	/* disable spi clearing fifo and interrupts */
	212	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	213	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
	214	BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
	215	}
	216
7188a6f0	217	static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
1ea29b39	218	{
73b114ee MS	219	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
73b114ee MS	220
1ea29b39	221	/* check if we have data to read */
73b114ee MS	222	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
73b114ee MS	223	stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
1ea29b39	224	bcm2835aux_rd_fifo(bs);
1ea29b39 MS	225
	226	/* check if we have data to write */
	227	while (bs->tx_len &&
72aac02b	228	(bs->pending < 12) &&
1ea29b39 MS	229	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	230	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	231	bcm2835aux_wr_fifo(bs);
1ea29b39	232	}
7188a6f0 MS	233	}
	234
	235	static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
	236	{
	237	struct spi_master *master = dev_id;
	238	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	239
	240	/* IRQ may be shared, so return if our interrupts are disabled */
	241	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
	242	(BCM2835_AUX_SPI_CNTL1_TXEMPTY \| BCM2835_AUX_SPI_CNTL1_IDLE)))
	243	return IRQ_NONE;
	244
	245	/* do common fifo handling */
	246	bcm2835aux_spi_transfer_helper(bs);
1ea29b39	247
f29ab184 SO	248	if (!bs->tx_len) {
	249	/* disable tx fifo empty interrupt */
	250	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	251	BCM2835_AUX_SPI_CNTL1_IDLE);
	252	}
	253
b4e2adef	254	/* and if rx_len is 0 then disable interrupts and wake up completion */
1ea29b39	255	if (!bs->rx_len) {
b4e2adef	256	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
1ea29b39 MS	257	complete(&master->xfer_completion);
	258	}
	259
7188a6f0	260	return IRQ_HANDLED;
1ea29b39 MS	261	}
	262
	263	static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
	264	struct spi_device *spi,
	265	struct spi_transfer *tfr)
	266	{
	267	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	268
	269	/* enable interrupts */
	270	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	271	BCM2835_AUX_SPI_CNTL1_TXEMPTY \|
	272	BCM2835_AUX_SPI_CNTL1_IDLE);
	273
	274	/* and wait for finish... */
	275	return 1;
	276	}
	277
	278	static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
	279	struct spi_device *spi,
	280	struct spi_transfer *tfr)
	281	{
	282	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	283
8048d151 MS	284	/* update statistics */
	285	bs->count_transfer_irq++;
	286
1ea29b39 MS	287	/* fill in registers and fifos before enabling interrupts */
	288	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	289	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	290
	291	/* fill in tx fifo with data before enabling interrupts */
	292	while ((bs->tx_len) &&
72aac02b	293	(bs->pending < 12) &&
1ea29b39 MS	294	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	295	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	296	bcm2835aux_wr_fifo(bs);
	297	}
	298
	299	/* now run the interrupt mode */
	300	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
	301	}
	302
	303	static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
	304	struct spi_device *spi,
72aac02b	305	struct spi_transfer *tfr)
1ea29b39 MS	306	{
	307	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	308	unsigned long timeout;
1ea29b39	309
8048d151 MS	310	/* update statistics */
	311	bs->count_transfer_polling++;
	312
1ea29b39 MS	313	/* configure spi */
	314	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	315	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	316
5fd917af MS	317	/* set the timeout to at least 2 jiffies */
5fd917af MS	318	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
1ea29b39 MS	319
	320	/* loop until finished the transfer */
	321	while (bs->rx_len) {
1ea29b39	322
7188a6f0 MS	323	/* do common fifo handling */
7188a6f0 MS	324	bcm2835aux_spi_transfer_helper(bs);
1ea29b39 MS	325
	326	/* there is still data pending to read check the timeout */
	327	if (bs->rx_len && time_after(jiffies, timeout)) {
	328	dev_dbg_ratelimited(&spi->dev,
	329	"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
	330	jiffies - timeout,
	331	bs->tx_len, bs->rx_len);
	332	/* forward to interrupt handler */
8048d151	333	bs->count_transfer_irq_after_poll++;
1ea29b39 MS	334	return __bcm2835aux_spi_transfer_one_irq(master,
	335	spi, tfr);
	336	}
	337	}
	338
1ea29b39 MS	339	/* and return without waiting for completion */
	340	return 0;
	341	}
	342
	343	static int bcm2835aux_spi_transfer_one(struct spi_master *master,
	344	struct spi_device *spi,
	345	struct spi_transfer *tfr)
	346	{
	347	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
5fd917af MS	348	unsigned long spi_hz, clk_hz, speed, spi_used_hz;
5fd917af MS	349	unsigned long hz_per_byte, byte_limit;
1ea29b39 MS	350
	351	/* calculate the registers to handle
	352	*
	353	* note that we use the variable data mode, which
	354	* is not optimal for longer transfers as we waste registers
	355	* resulting (potentially) in more interrupts when transferring
	356	* more than 12 bytes
	357	*/
1ea29b39 MS	358
	359	/* set clock */
	360	spi_hz = tfr->speed_hz;
	361	clk_hz = clk_get_rate(bs->clk);
	362
	363	if (spi_hz >= clk_hz / 2) {
	364	speed = 0;
	365	} else if (spi_hz) {
	366	speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
	367	if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
	368	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	369	} else { /* the slowest we can go */
	370	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	371	}
b4e2adef SO	372	/* mask out old speed from previous spi_transfer */
	373	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
	374	/* set the new speed */
1ea29b39 MS	375	bs->cntl[0] \|= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
	376
	377	spi_used_hz = clk_hz / (2 * (speed + 1));
	378
1ea29b39 MS	379	/* set transmit buffers and length */
	380	bs->tx_buf = tfr->tx_buf;
	381	bs->rx_buf = tfr->rx_buf;
	382	bs->tx_len = tfr->len;
	383	bs->rx_len = tfr->len;
72aac02b	384	bs->pending = 0;
1ea29b39	385
d704afff TP	386	/* Calculate the estimated time in us the transfer runs. Note that
	387	* there are are 2 idle clocks cycles after each chunk getting
	388	* transferred - in our case the chunk size is 3 bytes, so we
	389	* approximate this by 9 cycles/byte. This is used to find the number
	390	* of Hz per byte per polling limit. E.g., we can transfer 1 byte in
	391	* 30 µs per 300,000 Hz of bus clock.
72aac02b	392	*/
5fd917af MS	393	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
	394	byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;
	395
1ea29b39	396	/* run in polling mode for short transfers */
5fd917af	397	if (tfr->len < byte_limit)
72aac02b	398	return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
1ea29b39 MS	399
	400	/* run in interrupt mode for all others */
	401	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
	402	}
	403
b4e2adef SO	404	static int bcm2835aux_spi_prepare_message(struct spi_master *master,
	405	struct spi_message *msg)
	406	{
	407	struct spi_device *spi = msg->spi;
	408	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	409
	410	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE \|
	411	BCM2835_AUX_SPI_CNTL0_VAR_WIDTH \|
	412	BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	413	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
	414
	415	/* handle all the modes */
e9dd4edc	416	if (spi->mode & SPI_CPOL) {
b4e2adef	417	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_CPOL;
e9dd4edc SO	418	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
	419	} else {
	420	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_IN_RISING;
	421	}
b4e2adef SO	422	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	423	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	424
	425	return 0;
	426	}
	427
	428	static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
	429	struct spi_message *msg)
	430	{
	431	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	432
	433	bcm2835aux_spi_reset_hw(bs);
	434
	435	return 0;
	436	}
	437
1ea29b39 MS	438	static void bcm2835aux_spi_handle_err(struct spi_master *master,
	439	struct spi_message *msg)
	440	{
	441	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	442
	443	bcm2835aux_spi_reset_hw(bs);
	444	}
	445
519f2c22 MS	446	static int bcm2835aux_spi_setup(struct spi_device *spi)
	447	{
	448	int ret;
	449
	450	/* sanity check for native cs */
	451	if (spi->mode & SPI_NO_CS)
	452	return 0;
ccd978b7 MS	453	if (gpio_is_valid(spi->cs_gpio)) {
	454	/* with gpio-cs set the GPIO to the correct level
	455	* and as output (in case the dt has the gpio not configured
	456	* as output but native cs)
	457	*/
	458	ret = gpio_direction_output(spi->cs_gpio,
	459	(spi->mode & SPI_CS_HIGH) ? 0 : 1);
	460	if (ret)
	461	dev_err(&spi->dev,
	462	"could not set gpio %i as output: %i\n",
	463	spi->cs_gpio, ret);
	464
	465	return ret;
	466	}
519f2c22 MS	467
	468	/* for dt-backwards compatibility: only support native on CS0
	469	* known things not supported with broken native CS:
	470	* * multiple chip-selects: cs0-cs2 are all
	471	* simultaniously asserted whenever there is a transfer
	472	* this even includes SPI_NO_CS
	473	* * SPI_CS_HIGH: cs are always asserted low
	474	* * cs_change: cs is deasserted after each spi_transfer
	475	* * cs_delay_usec: cs is always deasserted one SCK cycle
	476	* after the last transfer
	477	* probably more...
	478	*/
	479	dev_warn(&spi->dev,
	480	"Native CS is not supported - please configure cs-gpio in device-tree\n");
	481
	482	if (spi->chip_select == 0)
	483	return 0;
	484
	485	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
	486
	487	return -EINVAL;
	488	}
	489
1ea29b39 MS	490	static int bcm2835aux_spi_probe(struct platform_device *pdev)
	491	{
	492	struct spi_master *master;
	493	struct bcm2835aux_spi *bs;
	494	struct resource *res;
	495	unsigned long clk_hz;
	496	int err;
	497
	498	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
bf93b951	499	if (!master)
1ea29b39	500	return -ENOMEM;
1ea29b39 MS	501
1ea29b39 MS	502	platform_set_drvdata(pdev, master);
e9dd4edc	503	master->mode_bits = (SPI_CPOL \| SPI_CS_HIGH \| SPI_NO_CS);
1ea29b39	504	master->bits_per_word_mask = SPI_BPW_MASK(8);
509c5836 MS	505	/* even though the driver never officially supported native CS
	506	* allow a single native CS for legacy DT support purposes when
	507	* no cs-gpio is configured.
	508	* Known limitations for native cs are:
	509	* * multiple chip-selects: cs0-cs2 are all simultaniously asserted
	510	* whenever there is a transfer - this even includes SPI_NO_CS
	511	* * SPI_CS_HIGH: is ignores - cs are always asserted low
	512	* * cs_change: cs is deasserted after each spi_transfer
	513	* * cs_delay_usec: cs is always deasserted one SCK cycle after
	514	* a spi_transfer
	515	*/
	516	master->num_chipselect = 1;
519f2c22	517	master->setup = bcm2835aux_spi_setup;
1ea29b39 MS	518	master->transfer_one = bcm2835aux_spi_transfer_one;
1ea29b39 MS	519	master->handle_err = bcm2835aux_spi_handle_err;
b4e2adef SO	520	master->prepare_message = bcm2835aux_spi_prepare_message;
b4e2adef SO	521	master->unprepare_message = bcm2835aux_spi_unprepare_message;
1ea29b39 MS	522	master->dev.of_node = pdev->dev.of_node;
	523
	524	bs = spi_master_get_devdata(master);
	525
	526	/* the main area */
	527	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	528	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	529	if (IS_ERR(bs->regs)) {
	530	err = PTR_ERR(bs->regs);
	531	goto out_master_put;
	532	}
	533
	534	bs->clk = devm_clk_get(&pdev->dev, NULL);
bfc7af6d	535	if (IS_ERR(bs->clk)) {
1ea29b39 MS	536	err = PTR_ERR(bs->clk);
	537	dev_err(&pdev->dev, "could not get clk: %d\n", err);
	538	goto out_master_put;
	539	}
	540
07bce09e	541	bs->irq = platform_get_irq(pdev, 0);
1ea29b39 MS	542	if (bs->irq <= 0) {
	543	dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
	544	err = bs->irq ? bs->irq : -ENODEV;
	545	goto out_master_put;
	546	}
	547
	548	/* this also enables the HW block */
	549	err = clk_prepare_enable(bs->clk);
	550	if (err) {
	551	dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
	552	goto out_master_put;
	553	}
	554
	555	/* just checking if the clock returns a sane value */
	556	clk_hz = clk_get_rate(bs->clk);
	557	if (!clk_hz) {
	558	dev_err(&pdev->dev, "clock returns 0 Hz\n");
	559	err = -ENODEV;
	560	goto out_clk_disable;
	561	}
	562
07bce09e MS	563	/* reset SPI-HW block */
	564	bcm2835aux_spi_reset_hw(bs);
	565
1ea29b39 MS	566	err = devm_request_irq(&pdev->dev, bs->irq,
	567	bcm2835aux_spi_interrupt,
	568	IRQF_SHARED,
	569	dev_name(&pdev->dev), master);
	570	if (err) {
	571	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
	572	goto out_clk_disable;
	573	}
	574
1ea29b39 MS	575	err = devm_spi_register_master(&pdev->dev, master);
	576	if (err) {
	577	dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
	578	goto out_clk_disable;
	579	}
	580
8048d151 MS	581	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
8048d151 MS	582
1ea29b39 MS	583	return 0;
	584
	585	out_clk_disable:
	586	clk_disable_unprepare(bs->clk);
	587	out_master_put:
	588	spi_master_put(master);
	589	return err;
	590	}
	591
	592	static int bcm2835aux_spi_remove(struct platform_device *pdev)
	593	{
	594	struct spi_master *master = platform_get_drvdata(pdev);
	595	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	596
8048d151 MS	597	bcm2835aux_debugfs_remove(bs);
8048d151 MS	598
1ea29b39 MS	599	bcm2835aux_spi_reset_hw(bs);
	600
	601	/* disable the HW block by releasing the clock */
	602	clk_disable_unprepare(bs->clk);
	603
	604	return 0;
	605	}
	606
	607	static const struct of_device_id bcm2835aux_spi_match[] = {
	608	{ .compatible = "brcm,bcm2835-aux-spi", },
	609	{}
	610	};
	611	MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
	612
	613	static struct platform_driver bcm2835aux_spi_driver = {
	614	.driver = {
	615	.name = "spi-bcm2835aux",
	616	.of_match_table = bcm2835aux_spi_match,
	617	},
	618	.probe = bcm2835aux_spi_probe,
	619	.remove = bcm2835aux_spi_remove,
	620	};
	621	module_platform_driver(bcm2835aux_spi_driver);
	622
	623	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
	624	MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
22bf6cd2	625	MODULE_LICENSE("GPL");