Commit | Line | Data |
---|---|---|
1ea29b39 MS |
1 | /* |
2 | * Driver for Broadcom BCM2835 auxiliary SPI Controllers | |
3 | * | |
4 | * the driver does not rely on the native chipselects at all | |
5 | * but only uses the gpio type chipselects | |
6 | * | |
7 | * Based on: spi-bcm2835.c | |
8 | * | |
9 | * Copyright (C) 2015 Martin Sperl | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
21 | ||
22 | #include <linux/clk.h> | |
23 | #include <linux/completion.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/of.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_device.h> | |
33 | #include <linux/of_gpio.h> | |
34 | #include <linux/of_irq.h> | |
35 | #include <linux/regmap.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spinlock.h> | |
38 | ||
39 | /* | |
40 | * spi register defines | |
41 | * | |
42 | * note there is garbage in the "official" documentation, | |
43 | * so some data is taken from the file: | |
44 | * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h | |
45 | * inside of: | |
46 | * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz | |
47 | */ | |
48 | ||
49 | /* SPI register offsets */ | |
50 | #define BCM2835_AUX_SPI_CNTL0 0x00 | |
51 | #define BCM2835_AUX_SPI_CNTL1 0x04 | |
52 | #define BCM2835_AUX_SPI_STAT 0x08 | |
53 | #define BCM2835_AUX_SPI_PEEK 0x0C | |
54 | #define BCM2835_AUX_SPI_IO 0x20 | |
55 | #define BCM2835_AUX_SPI_TXHOLD 0x30 | |
56 | ||
57 | /* Bitfields in CNTL0 */ | |
58 | #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 | |
59 | #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF | |
60 | #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 | |
61 | #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000 | |
62 | #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 | |
63 | #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 | |
64 | #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 | |
65 | #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 | |
66 | #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 | |
e9dd4edc | 67 | #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400 |
1ea29b39 | 68 | #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 |
e9dd4edc | 69 | #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100 |
1ea29b39 MS |
70 | #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 |
71 | #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 | |
72 | #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F | |
73 | ||
74 | /* Bitfields in CNTL1 */ | |
75 | #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 | |
fe0e2304 SO |
76 | #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080 |
77 | #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040 | |
1ea29b39 MS |
78 | #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 |
79 | #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 | |
80 | ||
81 | /* Bitfields in STAT */ | |
82 | #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 | |
83 | #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 | |
84 | #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 | |
85 | #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 | |
86 | #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 | |
87 | #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 | |
88 | #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 | |
89 | #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F | |
90 | ||
91 | /* timeout values */ | |
92 | #define BCM2835_AUX_SPI_POLLING_LIMIT_US 30 | |
93 | #define BCM2835_AUX_SPI_POLLING_JIFFIES 2 | |
94 | ||
1ea29b39 MS |
95 | struct bcm2835aux_spi { |
96 | void __iomem *regs; | |
97 | struct clk *clk; | |
98 | int irq; | |
99 | u32 cntl[2]; | |
100 | const u8 *tx_buf; | |
101 | u8 *rx_buf; | |
102 | int tx_len; | |
103 | int rx_len; | |
72aac02b | 104 | int pending; |
1ea29b39 MS |
105 | }; |
106 | ||
107 | static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) | |
108 | { | |
109 | return readl(bs->regs + reg); | |
110 | } | |
111 | ||
112 | static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, | |
113 | u32 val) | |
114 | { | |
115 | writel(val, bs->regs + reg); | |
116 | } | |
117 | ||
118 | static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs) | |
119 | { | |
120 | u32 data; | |
1ea29b39 MS |
121 | int count = min(bs->rx_len, 3); |
122 | ||
123 | data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO); | |
124 | if (bs->rx_buf) { | |
72aac02b MS |
125 | switch (count) { |
126 | case 4: | |
127 | *bs->rx_buf++ = (data >> 24) & 0xff; | |
128 | /* fallthrough */ | |
129 | case 3: | |
130 | *bs->rx_buf++ = (data >> 16) & 0xff; | |
131 | /* fallthrough */ | |
132 | case 2: | |
133 | *bs->rx_buf++ = (data >> 8) & 0xff; | |
134 | /* fallthrough */ | |
135 | case 1: | |
136 | *bs->rx_buf++ = (data >> 0) & 0xff; | |
137 | /* fallthrough - no default */ | |
138 | } | |
1ea29b39 MS |
139 | } |
140 | bs->rx_len -= count; | |
72aac02b | 141 | bs->pending -= count; |
1ea29b39 MS |
142 | } |
143 | ||
144 | static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs) | |
145 | { | |
146 | u32 data; | |
147 | u8 byte; | |
148 | int count; | |
149 | int i; | |
150 | ||
151 | /* gather up to 3 bytes to write to the FIFO */ | |
152 | count = min(bs->tx_len, 3); | |
153 | data = 0; | |
154 | for (i = 0; i < count; i++) { | |
155 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; | |
156 | data |= byte << (8 * (2 - i)); | |
157 | } | |
158 | ||
159 | /* and set the variable bit-length */ | |
160 | data |= (count * 8) << 24; | |
161 | ||
162 | /* and decrement length */ | |
163 | bs->tx_len -= count; | |
72aac02b | 164 | bs->pending += count; |
1ea29b39 MS |
165 | |
166 | /* write to the correct TX-register */ | |
167 | if (bs->tx_len) | |
168 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data); | |
169 | else | |
170 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data); | |
171 | } | |
172 | ||
173 | static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs) | |
174 | { | |
175 | /* disable spi clearing fifo and interrupts */ | |
176 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0); | |
177 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, | |
178 | BCM2835_AUX_SPI_CNTL0_CLEARFIFO); | |
179 | } | |
180 | ||
181 | static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) | |
182 | { | |
183 | struct spi_master *master = dev_id; | |
184 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
185 | irqreturn_t ret = IRQ_NONE; | |
186 | ||
187 | /* check if we have data to read */ | |
188 | while (bs->rx_len && | |
189 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & | |
190 | BCM2835_AUX_SPI_STAT_RX_EMPTY))) { | |
191 | bcm2835aux_rd_fifo(bs); | |
192 | ret = IRQ_HANDLED; | |
193 | } | |
194 | ||
195 | /* check if we have data to write */ | |
196 | while (bs->tx_len && | |
72aac02b | 197 | (bs->pending < 12) && |
1ea29b39 MS |
198 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
199 | BCM2835_AUX_SPI_STAT_TX_FULL))) { | |
200 | bcm2835aux_wr_fifo(bs); | |
201 | ret = IRQ_HANDLED; | |
202 | } | |
203 | ||
204 | /* and check if we have reached "done" */ | |
205 | while (bs->rx_len && | |
206 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & | |
207 | BCM2835_AUX_SPI_STAT_BUSY))) { | |
208 | bcm2835aux_rd_fifo(bs); | |
209 | ret = IRQ_HANDLED; | |
210 | } | |
211 | ||
f29ab184 SO |
212 | if (!bs->tx_len) { |
213 | /* disable tx fifo empty interrupt */ | |
214 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | | |
215 | BCM2835_AUX_SPI_CNTL1_IDLE); | |
216 | } | |
217 | ||
b4e2adef | 218 | /* and if rx_len is 0 then disable interrupts and wake up completion */ |
1ea29b39 | 219 | if (!bs->rx_len) { |
b4e2adef | 220 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
1ea29b39 MS |
221 | complete(&master->xfer_completion); |
222 | } | |
223 | ||
224 | /* and return */ | |
225 | return ret; | |
226 | } | |
227 | ||
228 | static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master, | |
229 | struct spi_device *spi, | |
230 | struct spi_transfer *tfr) | |
231 | { | |
232 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
233 | ||
234 | /* enable interrupts */ | |
235 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | | |
236 | BCM2835_AUX_SPI_CNTL1_TXEMPTY | | |
237 | BCM2835_AUX_SPI_CNTL1_IDLE); | |
238 | ||
239 | /* and wait for finish... */ | |
240 | return 1; | |
241 | } | |
242 | ||
243 | static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master, | |
244 | struct spi_device *spi, | |
245 | struct spi_transfer *tfr) | |
246 | { | |
247 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
248 | ||
249 | /* fill in registers and fifos before enabling interrupts */ | |
250 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); | |
251 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); | |
252 | ||
253 | /* fill in tx fifo with data before enabling interrupts */ | |
254 | while ((bs->tx_len) && | |
72aac02b | 255 | (bs->pending < 12) && |
1ea29b39 MS |
256 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
257 | BCM2835_AUX_SPI_STAT_TX_FULL))) { | |
258 | bcm2835aux_wr_fifo(bs); | |
259 | } | |
260 | ||
261 | /* now run the interrupt mode */ | |
262 | return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr); | |
263 | } | |
264 | ||
265 | static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master, | |
266 | struct spi_device *spi, | |
72aac02b | 267 | struct spi_transfer *tfr) |
1ea29b39 MS |
268 | { |
269 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
270 | unsigned long timeout; | |
271 | u32 stat; | |
272 | ||
273 | /* configure spi */ | |
274 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); | |
275 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); | |
276 | ||
277 | /* set the timeout */ | |
278 | timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES; | |
279 | ||
280 | /* loop until finished the transfer */ | |
281 | while (bs->rx_len) { | |
282 | /* read status */ | |
283 | stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT); | |
284 | ||
285 | /* fill in tx fifo with remaining data */ | |
286 | if ((bs->tx_len) && (!(stat & BCM2835_AUX_SPI_STAT_TX_FULL))) { | |
287 | bcm2835aux_wr_fifo(bs); | |
288 | continue; | |
289 | } | |
290 | ||
291 | /* read data from fifo for both cases */ | |
292 | if (!(stat & BCM2835_AUX_SPI_STAT_RX_EMPTY)) { | |
293 | bcm2835aux_rd_fifo(bs); | |
294 | continue; | |
295 | } | |
296 | if (!(stat & BCM2835_AUX_SPI_STAT_BUSY)) { | |
297 | bcm2835aux_rd_fifo(bs); | |
298 | continue; | |
299 | } | |
300 | ||
301 | /* there is still data pending to read check the timeout */ | |
302 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
303 | dev_dbg_ratelimited(&spi->dev, | |
304 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
305 | jiffies - timeout, | |
306 | bs->tx_len, bs->rx_len); | |
307 | /* forward to interrupt handler */ | |
308 | return __bcm2835aux_spi_transfer_one_irq(master, | |
309 | spi, tfr); | |
310 | } | |
311 | } | |
312 | ||
1ea29b39 MS |
313 | /* and return without waiting for completion */ |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int bcm2835aux_spi_transfer_one(struct spi_master *master, | |
318 | struct spi_device *spi, | |
319 | struct spi_transfer *tfr) | |
320 | { | |
321 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
322 | unsigned long spi_hz, clk_hz, speed; | |
72aac02b MS |
323 | unsigned long spi_used_hz; |
324 | unsigned long long xfer_time_us; | |
1ea29b39 MS |
325 | |
326 | /* calculate the registers to handle | |
327 | * | |
328 | * note that we use the variable data mode, which | |
329 | * is not optimal for longer transfers as we waste registers | |
330 | * resulting (potentially) in more interrupts when transferring | |
331 | * more than 12 bytes | |
332 | */ | |
1ea29b39 MS |
333 | |
334 | /* set clock */ | |
335 | spi_hz = tfr->speed_hz; | |
336 | clk_hz = clk_get_rate(bs->clk); | |
337 | ||
338 | if (spi_hz >= clk_hz / 2) { | |
339 | speed = 0; | |
340 | } else if (spi_hz) { | |
341 | speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; | |
342 | if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX) | |
343 | speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; | |
344 | } else { /* the slowest we can go */ | |
345 | speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX; | |
346 | } | |
b4e2adef SO |
347 | /* mask out old speed from previous spi_transfer */ |
348 | bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED); | |
349 | /* set the new speed */ | |
1ea29b39 MS |
350 | bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; |
351 | ||
352 | spi_used_hz = clk_hz / (2 * (speed + 1)); | |
353 | ||
1ea29b39 MS |
354 | /* set transmit buffers and length */ |
355 | bs->tx_buf = tfr->tx_buf; | |
356 | bs->rx_buf = tfr->rx_buf; | |
357 | bs->tx_len = tfr->len; | |
358 | bs->rx_len = tfr->len; | |
72aac02b | 359 | bs->pending = 0; |
1ea29b39 | 360 | |
72aac02b MS |
361 | /* calculate the estimated time in us the transfer runs |
362 | * note that there are are 2 idle clocks after each | |
363 | * chunk getting transferred - in our case the chunk size | |
364 | * is 3 bytes, so we approximate this by 9 bits/byte | |
365 | */ | |
366 | xfer_time_us = tfr->len * 9 * 1000000; | |
367 | do_div(xfer_time_us, spi_used_hz); | |
1ea29b39 MS |
368 | |
369 | /* run in polling mode for short transfers */ | |
370 | if (xfer_time_us < BCM2835_AUX_SPI_POLLING_LIMIT_US) | |
72aac02b | 371 | return bcm2835aux_spi_transfer_one_poll(master, spi, tfr); |
1ea29b39 MS |
372 | |
373 | /* run in interrupt mode for all others */ | |
374 | return bcm2835aux_spi_transfer_one_irq(master, spi, tfr); | |
375 | } | |
376 | ||
b4e2adef SO |
377 | static int bcm2835aux_spi_prepare_message(struct spi_master *master, |
378 | struct spi_message *msg) | |
379 | { | |
380 | struct spi_device *spi = msg->spi; | |
381 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
382 | ||
383 | bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | | |
384 | BCM2835_AUX_SPI_CNTL0_VAR_WIDTH | | |
385 | BCM2835_AUX_SPI_CNTL0_MSBF_OUT; | |
386 | bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; | |
387 | ||
388 | /* handle all the modes */ | |
e9dd4edc | 389 | if (spi->mode & SPI_CPOL) { |
b4e2adef | 390 | bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; |
e9dd4edc SO |
391 | bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING; |
392 | } else { | |
393 | bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING; | |
394 | } | |
b4e2adef SO |
395 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); |
396 | bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int bcm2835aux_spi_unprepare_message(struct spi_master *master, | |
402 | struct spi_message *msg) | |
403 | { | |
404 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
405 | ||
406 | bcm2835aux_spi_reset_hw(bs); | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
1ea29b39 MS |
411 | static void bcm2835aux_spi_handle_err(struct spi_master *master, |
412 | struct spi_message *msg) | |
413 | { | |
414 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
415 | ||
416 | bcm2835aux_spi_reset_hw(bs); | |
417 | } | |
418 | ||
419 | static int bcm2835aux_spi_probe(struct platform_device *pdev) | |
420 | { | |
421 | struct spi_master *master; | |
422 | struct bcm2835aux_spi *bs; | |
423 | struct resource *res; | |
424 | unsigned long clk_hz; | |
425 | int err; | |
426 | ||
427 | master = spi_alloc_master(&pdev->dev, sizeof(*bs)); | |
428 | if (!master) { | |
429 | dev_err(&pdev->dev, "spi_alloc_master() failed\n"); | |
430 | return -ENOMEM; | |
431 | } | |
432 | ||
433 | platform_set_drvdata(pdev, master); | |
e9dd4edc | 434 | master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); |
1ea29b39 MS |
435 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
436 | master->num_chipselect = -1; | |
437 | master->transfer_one = bcm2835aux_spi_transfer_one; | |
438 | master->handle_err = bcm2835aux_spi_handle_err; | |
b4e2adef SO |
439 | master->prepare_message = bcm2835aux_spi_prepare_message; |
440 | master->unprepare_message = bcm2835aux_spi_unprepare_message; | |
1ea29b39 MS |
441 | master->dev.of_node = pdev->dev.of_node; |
442 | ||
443 | bs = spi_master_get_devdata(master); | |
444 | ||
445 | /* the main area */ | |
446 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
447 | bs->regs = devm_ioremap_resource(&pdev->dev, res); | |
448 | if (IS_ERR(bs->regs)) { | |
449 | err = PTR_ERR(bs->regs); | |
450 | goto out_master_put; | |
451 | } | |
452 | ||
453 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
454 | if ((!bs->clk) || (IS_ERR(bs->clk))) { | |
455 | err = PTR_ERR(bs->clk); | |
456 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
457 | goto out_master_put; | |
458 | } | |
459 | ||
07bce09e | 460 | bs->irq = platform_get_irq(pdev, 0); |
1ea29b39 MS |
461 | if (bs->irq <= 0) { |
462 | dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); | |
463 | err = bs->irq ? bs->irq : -ENODEV; | |
464 | goto out_master_put; | |
465 | } | |
466 | ||
467 | /* this also enables the HW block */ | |
468 | err = clk_prepare_enable(bs->clk); | |
469 | if (err) { | |
470 | dev_err(&pdev->dev, "could not prepare clock: %d\n", err); | |
471 | goto out_master_put; | |
472 | } | |
473 | ||
474 | /* just checking if the clock returns a sane value */ | |
475 | clk_hz = clk_get_rate(bs->clk); | |
476 | if (!clk_hz) { | |
477 | dev_err(&pdev->dev, "clock returns 0 Hz\n"); | |
478 | err = -ENODEV; | |
479 | goto out_clk_disable; | |
480 | } | |
481 | ||
07bce09e MS |
482 | /* reset SPI-HW block */ |
483 | bcm2835aux_spi_reset_hw(bs); | |
484 | ||
1ea29b39 MS |
485 | err = devm_request_irq(&pdev->dev, bs->irq, |
486 | bcm2835aux_spi_interrupt, | |
487 | IRQF_SHARED, | |
488 | dev_name(&pdev->dev), master); | |
489 | if (err) { | |
490 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
491 | goto out_clk_disable; | |
492 | } | |
493 | ||
1ea29b39 MS |
494 | err = devm_spi_register_master(&pdev->dev, master); |
495 | if (err) { | |
496 | dev_err(&pdev->dev, "could not register SPI master: %d\n", err); | |
497 | goto out_clk_disable; | |
498 | } | |
499 | ||
500 | return 0; | |
501 | ||
502 | out_clk_disable: | |
503 | clk_disable_unprepare(bs->clk); | |
504 | out_master_put: | |
505 | spi_master_put(master); | |
506 | return err; | |
507 | } | |
508 | ||
509 | static int bcm2835aux_spi_remove(struct platform_device *pdev) | |
510 | { | |
511 | struct spi_master *master = platform_get_drvdata(pdev); | |
512 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | |
513 | ||
514 | bcm2835aux_spi_reset_hw(bs); | |
515 | ||
516 | /* disable the HW block by releasing the clock */ | |
517 | clk_disable_unprepare(bs->clk); | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static const struct of_device_id bcm2835aux_spi_match[] = { | |
523 | { .compatible = "brcm,bcm2835-aux-spi", }, | |
524 | {} | |
525 | }; | |
526 | MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match); | |
527 | ||
528 | static struct platform_driver bcm2835aux_spi_driver = { | |
529 | .driver = { | |
530 | .name = "spi-bcm2835aux", | |
531 | .of_match_table = bcm2835aux_spi_match, | |
532 | }, | |
533 | .probe = bcm2835aux_spi_probe, | |
534 | .remove = bcm2835aux_spi_remove, | |
535 | }; | |
536 | module_platform_driver(bcm2835aux_spi_driver); | |
537 | ||
538 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux"); | |
539 | MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); | |
540 | MODULE_LICENSE("GPL v2"); |