Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
f8043872 CB |
2 | /* |
3 | * Driver for Broadcom BCM2835 SPI Controllers | |
4 | * | |
5 | * Copyright (C) 2012 Chris Boot | |
6 | * Copyright (C) 2013 Stephen Warren | |
e34ff011 | 7 | * Copyright (C) 2015 Martin Sperl |
f8043872 CB |
8 | * |
9 | * This driver is inspired by: | |
10 | * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> | |
11 | * spi-atmel.c, Copyright (C) 2006 Atmel Corporation | |
f8043872 CB |
12 | */ |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
154f7da5 | 16 | #include <linux/debugfs.h> |
f8043872 | 17 | #include <linux/delay.h> |
3ecd37ed MS |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/dmaengine.h> | |
f8043872 CB |
20 | #include <linux/err.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of.h> | |
3ecd37ed | 26 | #include <linux/of_address.h> |
f8043872 | 27 | #include <linux/of_device.h> |
3bd158c5 LW |
28 | #include <linux/gpio/consumer.h> |
29 | #include <linux/gpio/machine.h> /* FIXME: using chip internals */ | |
30 | #include <linux/gpio/driver.h> /* FIXME: using chip internals */ | |
3ecd37ed | 31 | #include <linux/of_irq.h> |
f8043872 CB |
32 | #include <linux/spi/spi.h> |
33 | ||
34 | /* SPI register offsets */ | |
35 | #define BCM2835_SPI_CS 0x00 | |
36 | #define BCM2835_SPI_FIFO 0x04 | |
37 | #define BCM2835_SPI_CLK 0x08 | |
38 | #define BCM2835_SPI_DLEN 0x0c | |
39 | #define BCM2835_SPI_LTOH 0x10 | |
40 | #define BCM2835_SPI_DC 0x14 | |
41 | ||
42 | /* Bitfields in CS */ | |
43 | #define BCM2835_SPI_CS_LEN_LONG 0x02000000 | |
44 | #define BCM2835_SPI_CS_DMA_LEN 0x01000000 | |
45 | #define BCM2835_SPI_CS_CSPOL2 0x00800000 | |
46 | #define BCM2835_SPI_CS_CSPOL1 0x00400000 | |
47 | #define BCM2835_SPI_CS_CSPOL0 0x00200000 | |
48 | #define BCM2835_SPI_CS_RXF 0x00100000 | |
49 | #define BCM2835_SPI_CS_RXR 0x00080000 | |
50 | #define BCM2835_SPI_CS_TXD 0x00040000 | |
51 | #define BCM2835_SPI_CS_RXD 0x00020000 | |
52 | #define BCM2835_SPI_CS_DONE 0x00010000 | |
53 | #define BCM2835_SPI_CS_LEN 0x00002000 | |
54 | #define BCM2835_SPI_CS_REN 0x00001000 | |
55 | #define BCM2835_SPI_CS_ADCS 0x00000800 | |
56 | #define BCM2835_SPI_CS_INTR 0x00000400 | |
57 | #define BCM2835_SPI_CS_INTD 0x00000200 | |
58 | #define BCM2835_SPI_CS_DMAEN 0x00000100 | |
59 | #define BCM2835_SPI_CS_TA 0x00000080 | |
60 | #define BCM2835_SPI_CS_CSPOL 0x00000040 | |
61 | #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 | |
62 | #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 | |
63 | #define BCM2835_SPI_CS_CPOL 0x00000008 | |
64 | #define BCM2835_SPI_CS_CPHA 0x00000004 | |
65 | #define BCM2835_SPI_CS_CS_10 0x00000002 | |
66 | #define BCM2835_SPI_CS_CS_01 0x00000001 | |
67 | ||
2e0733bc LW |
68 | #define BCM2835_SPI_FIFO_SIZE 64 |
69 | #define BCM2835_SPI_FIFO_SIZE_3_4 48 | |
3ecd37ed | 70 | #define BCM2835_SPI_DMA_MIN_LENGTH 96 |
571e31fa | 71 | #define BCM2835_SPI_NUM_CS 3 /* raise as necessary */ |
6935224d MS |
72 | #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
73 | | SPI_NO_CS | SPI_3WIRE) | |
f8043872 CB |
74 | |
75 | #define DRV_NAME "spi-bcm2835" | |
76 | ||
ff245d90 MS |
77 | /* define polling limits */ |
78 | unsigned int polling_limit_us = 30; | |
79 | module_param(polling_limit_us, uint, 0664); | |
80 | MODULE_PARM_DESC(polling_limit_us, | |
81 | "time in us to run a transfer in polling mode\n"); | |
82 | ||
acf0f856 LW |
83 | /** |
84 | * struct bcm2835_spi - BCM2835 SPI controller | |
85 | * @regs: base address of register map | |
86 | * @clk: core clock, divided to calculate serial clock | |
87 | * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full | |
3bd7f658 | 88 | * @tfr: SPI transfer currently processed |
acf0f856 LW |
89 | * @tx_buf: pointer whence next transmitted byte is read |
90 | * @rx_buf: pointer where next received byte is written | |
91 | * @tx_len: remaining bytes to transmit | |
92 | * @rx_len: remaining bytes to receive | |
3bd7f658 LW |
93 | * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's |
94 | * length is not a multiple of 4 (to overcome hardware limitation) | |
95 | * @rx_prologue: bytes received without DMA if first RX sglist entry's | |
96 | * length is not a multiple of 4 (to overcome hardware limitation) | |
97 | * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry | |
571e31fa LW |
98 | * @prepare_cs: precalculated CS register value for ->prepare_message() |
99 | * (uses slave-specific clock polarity and phase settings) | |
154f7da5 MS |
100 | * @debugfs_dir: the debugfs directory - neede to remove debugfs when |
101 | * unloading the module | |
102 | * @count_transfer_polling: count of how often polling mode is used | |
103 | * @count_transfer_irq: count of how often interrupt mode is used | |
104 | * @count_transfer_irq_after_polling: count of how often we fall back to | |
105 | * interrupt mode after starting in polling mode. | |
106 | * These are counted as well in @count_transfer_polling and | |
107 | * @count_transfer_irq | |
108 | * @count_transfer_dma: count how often dma mode is used | |
acf0f856 | 109 | */ |
f8043872 CB |
110 | struct bcm2835_spi { |
111 | void __iomem *regs; | |
112 | struct clk *clk; | |
113 | int irq; | |
3bd7f658 | 114 | struct spi_transfer *tfr; |
f8043872 CB |
115 | const u8 *tx_buf; |
116 | u8 *rx_buf; | |
e34ff011 MS |
117 | int tx_len; |
118 | int rx_len; | |
3bd7f658 LW |
119 | int tx_prologue; |
120 | int rx_prologue; | |
b31a9299 | 121 | unsigned int tx_spillover; |
571e31fa | 122 | u32 prepare_cs[BCM2835_SPI_NUM_CS]; |
154f7da5 MS |
123 | |
124 | struct dentry *debugfs_dir; | |
125 | u64 count_transfer_polling; | |
126 | u64 count_transfer_irq; | |
127 | u64 count_transfer_irq_after_polling; | |
128 | u64 count_transfer_dma; | |
f8043872 CB |
129 | }; |
130 | ||
154f7da5 MS |
131 | #if defined(CONFIG_DEBUG_FS) |
132 | static void bcm2835_debugfs_create(struct bcm2835_spi *bs, | |
133 | const char *dname) | |
134 | { | |
135 | char name[64]; | |
136 | struct dentry *dir; | |
137 | ||
138 | /* get full name */ | |
139 | snprintf(name, sizeof(name), "spi-bcm2835-%s", dname); | |
140 | ||
141 | /* the base directory */ | |
142 | dir = debugfs_create_dir(name, NULL); | |
143 | bs->debugfs_dir = dir; | |
144 | ||
145 | /* the counters */ | |
146 | debugfs_create_u64("count_transfer_polling", 0444, dir, | |
147 | &bs->count_transfer_polling); | |
148 | debugfs_create_u64("count_transfer_irq", 0444, dir, | |
149 | &bs->count_transfer_irq); | |
150 | debugfs_create_u64("count_transfer_irq_after_polling", 0444, dir, | |
151 | &bs->count_transfer_irq_after_polling); | |
152 | debugfs_create_u64("count_transfer_dma", 0444, dir, | |
153 | &bs->count_transfer_dma); | |
154 | } | |
155 | ||
156 | static void bcm2835_debugfs_remove(struct bcm2835_spi *bs) | |
157 | { | |
158 | debugfs_remove_recursive(bs->debugfs_dir); | |
159 | bs->debugfs_dir = NULL; | |
160 | } | |
161 | #else | |
162 | static void bcm2835_debugfs_create(struct bcm2835_spi *bs, | |
163 | const char *dname) | |
164 | { | |
165 | } | |
166 | ||
167 | static void bcm2835_debugfs_remove(struct bcm2835_spi *bs) | |
168 | { | |
169 | } | |
170 | #endif /* CONFIG_DEBUG_FS */ | |
171 | ||
f8043872 CB |
172 | static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) |
173 | { | |
174 | return readl(bs->regs + reg); | |
175 | } | |
176 | ||
177 | static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) | |
178 | { | |
179 | writel(val, bs->regs + reg); | |
180 | } | |
181 | ||
4adf3129 | 182 | static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
183 | { |
184 | u8 byte; | |
185 | ||
e34ff011 MS |
186 | while ((bs->rx_len) && |
187 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { | |
f8043872 CB |
188 | byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); |
189 | if (bs->rx_buf) | |
190 | *bs->rx_buf++ = byte; | |
e34ff011 | 191 | bs->rx_len--; |
f8043872 CB |
192 | } |
193 | } | |
194 | ||
4adf3129 | 195 | static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
196 | { |
197 | u8 byte; | |
198 | ||
e34ff011 | 199 | while ((bs->tx_len) && |
4adf3129 | 200 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { |
f8043872 CB |
201 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; |
202 | bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); | |
e34ff011 | 203 | bs->tx_len--; |
f8043872 CB |
204 | } |
205 | } | |
206 | ||
3bd7f658 LW |
207 | /** |
208 | * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO | |
209 | * @bs: BCM2835 SPI controller | |
210 | * @count: bytes to read from RX FIFO | |
211 | * | |
212 | * The caller must ensure that @bs->rx_len is greater than or equal to @count, | |
213 | * that the RX FIFO contains at least @count bytes and that the DMA Enable flag | |
214 | * in the CS register is set (such that a read from the FIFO register receives | |
b31a9299 | 215 | * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL. |
3bd7f658 LW |
216 | */ |
217 | static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count) | |
218 | { | |
219 | u32 val; | |
b31a9299 | 220 | int len; |
3bd7f658 LW |
221 | |
222 | bs->rx_len -= count; | |
223 | ||
224 | while (count > 0) { | |
225 | val = bcm2835_rd(bs, BCM2835_SPI_FIFO); | |
b31a9299 LW |
226 | len = min(count, 4); |
227 | memcpy(bs->rx_buf, &val, len); | |
228 | bs->rx_buf += len; | |
3bd7f658 LW |
229 | count -= 4; |
230 | } | |
231 | } | |
232 | ||
233 | /** | |
234 | * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO | |
235 | * @bs: BCM2835 SPI controller | |
236 | * @count: bytes to write to TX FIFO | |
237 | * | |
238 | * The caller must ensure that @bs->tx_len is greater than or equal to @count, | |
239 | * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag | |
240 | * in the CS register is set (such that a write to the FIFO register transmits | |
241 | * 32-bit instead of just 8-bit). | |
242 | */ | |
243 | static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count) | |
244 | { | |
245 | u32 val; | |
b31a9299 | 246 | int len; |
3bd7f658 LW |
247 | |
248 | bs->tx_len -= count; | |
249 | ||
250 | while (count > 0) { | |
251 | if (bs->tx_buf) { | |
b31a9299 | 252 | len = min(count, 4); |
3bd7f658 LW |
253 | memcpy(&val, bs->tx_buf, len); |
254 | bs->tx_buf += len; | |
255 | } else { | |
256 | val = 0; | |
257 | } | |
258 | bcm2835_wr(bs, BCM2835_SPI_FIFO, val); | |
259 | count -= 4; | |
260 | } | |
261 | } | |
262 | ||
263 | /** | |
264 | * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty | |
265 | * @bs: BCM2835 SPI controller | |
b31a9299 LW |
266 | * |
267 | * The caller must ensure that the RX FIFO can accommodate as many bytes | |
268 | * as have been written to the TX FIFO: Transmission is halted once the | |
269 | * RX FIFO is full, causing this function to spin forever. | |
3bd7f658 LW |
270 | */ |
271 | static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs) | |
272 | { | |
273 | while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE)) | |
274 | cpu_relax(); | |
275 | } | |
276 | ||
2e0733bc LW |
277 | /** |
278 | * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO | |
279 | * @bs: BCM2835 SPI controller | |
280 | * @count: bytes available for reading in RX FIFO | |
281 | */ | |
282 | static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count) | |
283 | { | |
284 | u8 val; | |
285 | ||
286 | count = min(count, bs->rx_len); | |
287 | bs->rx_len -= count; | |
288 | ||
289 | while (count) { | |
290 | val = bcm2835_rd(bs, BCM2835_SPI_FIFO); | |
291 | if (bs->rx_buf) | |
292 | *bs->rx_buf++ = val; | |
293 | count--; | |
294 | } | |
295 | } | |
296 | ||
297 | /** | |
298 | * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO | |
299 | * @bs: BCM2835 SPI controller | |
300 | * @count: bytes available for writing in TX FIFO | |
301 | */ | |
302 | static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count) | |
303 | { | |
304 | u8 val; | |
305 | ||
306 | count = min(count, bs->tx_len); | |
307 | bs->tx_len -= count; | |
308 | ||
309 | while (count) { | |
310 | val = bs->tx_buf ? *bs->tx_buf++ : 0; | |
311 | bcm2835_wr(bs, BCM2835_SPI_FIFO, val); | |
312 | count--; | |
313 | } | |
314 | } | |
315 | ||
5f336ea5 | 316 | static void bcm2835_spi_reset_hw(struct spi_controller *ctlr) |
e34ff011 | 317 | { |
5f336ea5 | 318 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
e34ff011 MS |
319 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
320 | ||
321 | /* Disable SPI interrupts and transfer */ | |
322 | cs &= ~(BCM2835_SPI_CS_INTR | | |
323 | BCM2835_SPI_CS_INTD | | |
3ecd37ed | 324 | BCM2835_SPI_CS_DMAEN | |
e34ff011 MS |
325 | BCM2835_SPI_CS_TA); |
326 | /* and reset RX/TX FIFOS */ | |
327 | cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; | |
328 | ||
329 | /* and reset the SPI_HW */ | |
330 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
3ecd37ed MS |
331 | /* as well as DLEN */ |
332 | bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); | |
e34ff011 MS |
333 | } |
334 | ||
f8043872 CB |
335 | static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) |
336 | { | |
5f336ea5 LW |
337 | struct spi_controller *ctlr = dev_id; |
338 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
2e0733bc LW |
339 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
340 | ||
341 | /* | |
342 | * An interrupt is signaled either if DONE is set (TX FIFO empty) | |
343 | * or if RXR is set (RX FIFO >= ¾ full). | |
344 | */ | |
345 | if (cs & BCM2835_SPI_CS_RXF) | |
346 | bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
347 | else if (cs & BCM2835_SPI_CS_RXR) | |
348 | bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4); | |
349 | ||
350 | if (bs->tx_len && cs & BCM2835_SPI_CS_DONE) | |
351 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
f8043872 | 352 | |
4adf3129 MS |
353 | /* Read as many bytes as possible from FIFO */ |
354 | bcm2835_rd_fifo(bs); | |
e34ff011 MS |
355 | /* Write as many bytes as possible to FIFO */ |
356 | bcm2835_wr_fifo(bs); | |
357 | ||
56c17234 | 358 | if (!bs->rx_len) { |
e34ff011 | 359 | /* Transfer complete - reset SPI HW */ |
5f336ea5 | 360 | bcm2835_spi_reset_hw(ctlr); |
e34ff011 | 361 | /* wake up the framework */ |
5f336ea5 | 362 | complete(&ctlr->xfer_completion); |
f8043872 CB |
363 | } |
364 | ||
4adf3129 | 365 | return IRQ_HANDLED; |
f8043872 CB |
366 | } |
367 | ||
5f336ea5 | 368 | static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr, |
704f32d4 MS |
369 | struct spi_device *spi, |
370 | struct spi_transfer *tfr, | |
2e0733bc | 371 | u32 cs, bool fifo_empty) |
704f32d4 | 372 | { |
5f336ea5 | 373 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
704f32d4 | 374 | |
154f7da5 MS |
375 | /* update usage statistics */ |
376 | bs->count_transfer_irq++; | |
377 | ||
704f32d4 | 378 | /* |
5c09e42f LW |
379 | * Enable HW block, but with interrupts still disabled. |
380 | * Otherwise the empty TX FIFO would immediately trigger an interrupt. | |
704f32d4 | 381 | */ |
5c09e42f LW |
382 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); |
383 | ||
384 | /* fill TX FIFO as much as possible */ | |
2e0733bc LW |
385 | if (fifo_empty) |
386 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
5c09e42f LW |
387 | bcm2835_wr_fifo(bs); |
388 | ||
389 | /* enable interrupts */ | |
704f32d4 MS |
390 | cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; |
391 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
392 | ||
393 | /* signal that we need to wait for completion */ | |
394 | return 1; | |
395 | } | |
396 | ||
3bd7f658 LW |
397 | /** |
398 | * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA | |
5f336ea5 | 399 | * @ctlr: SPI master controller |
3bd7f658 LW |
400 | * @tfr: SPI transfer |
401 | * @bs: BCM2835 SPI controller | |
402 | * @cs: CS register | |
403 | * | |
404 | * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks. | |
405 | * Only the final write access is permitted to transmit less than 4 bytes, the | |
406 | * SPI controller deduces its intended size from the DLEN register. | |
407 | * | |
408 | * If a TX or RX sglist contains multiple entries, one per page, and the first | |
409 | * entry starts in the middle of a page, that first entry's length may not be | |
410 | * a multiple of 4. Subsequent entries are fine because they span an entire | |
411 | * page, hence do have a length that's a multiple of 4. | |
412 | * | |
413 | * This cannot happen with kmalloc'ed buffers (which is what most clients use) | |
414 | * because they are contiguous in physical memory and therefore not split on | |
415 | * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed | |
416 | * buffers. | |
417 | * | |
418 | * The DMA engine is incapable of combining sglist entries into a continuous | |
419 | * stream of 4 byte chunks, it treats every entry separately: A TX entry is | |
420 | * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX | |
421 | * entry is rounded up by throwing away received bytes. | |
422 | * | |
423 | * Overcome this limitation by transferring the first few bytes without DMA: | |
424 | * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42, | |
425 | * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO. | |
426 | * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with | |
427 | * the rest of the first RX sglist entry it makes up a multiple of 4 bytes. | |
428 | * | |
429 | * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1, | |
430 | * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO. | |
431 | * Caution, the additional 4 bytes spill over to the second TX sglist entry | |
432 | * if the length of the first is *exactly* 1. | |
433 | * | |
434 | * At most 6 bytes are written and at most 3 bytes read. Do we know the | |
435 | * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH. | |
436 | * | |
437 | * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width | |
438 | * by the DMA engine. Toggling the DMA Enable flag in the CS register switches | |
439 | * the width but also garbles the FIFO's contents. The prologue must therefore | |
440 | * be transmitted in 32-bit width to ensure that the following DMA transfer can | |
441 | * pick up the residue in the RX FIFO in ungarbled form. | |
442 | */ | |
5f336ea5 | 443 | static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, |
3bd7f658 LW |
444 | struct spi_transfer *tfr, |
445 | struct bcm2835_spi *bs, | |
446 | u32 cs) | |
447 | { | |
448 | int tx_remaining; | |
449 | ||
450 | bs->tfr = tfr; | |
451 | bs->tx_prologue = 0; | |
452 | bs->rx_prologue = 0; | |
453 | bs->tx_spillover = false; | |
454 | ||
455 | if (!sg_is_last(&tfr->tx_sg.sgl[0])) | |
456 | bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3; | |
457 | ||
458 | if (!sg_is_last(&tfr->rx_sg.sgl[0])) { | |
459 | bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3; | |
460 | ||
461 | if (bs->rx_prologue > bs->tx_prologue) { | |
462 | if (sg_is_last(&tfr->tx_sg.sgl[0])) { | |
463 | bs->tx_prologue = bs->rx_prologue; | |
464 | } else { | |
465 | bs->tx_prologue += 4; | |
466 | bs->tx_spillover = | |
467 | !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3); | |
468 | } | |
469 | } | |
470 | } | |
471 | ||
472 | /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */ | |
473 | if (!bs->tx_prologue) | |
474 | return; | |
475 | ||
476 | /* Write and read RX prologue. Adjust first entry in RX sglist. */ | |
477 | if (bs->rx_prologue) { | |
478 | bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue); | |
479 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA | |
480 | | BCM2835_SPI_CS_DMAEN); | |
481 | bcm2835_wr_fifo_count(bs, bs->rx_prologue); | |
482 | bcm2835_wait_tx_fifo_empty(bs); | |
483 | bcm2835_rd_fifo_count(bs, bs->rx_prologue); | |
5f336ea5 | 484 | bcm2835_spi_reset_hw(ctlr); |
3bd7f658 | 485 | |
5f336ea5 | 486 | dma_sync_single_for_device(ctlr->dma_rx->device->dev, |
b31a9299 LW |
487 | sg_dma_address(&tfr->rx_sg.sgl[0]), |
488 | bs->rx_prologue, DMA_FROM_DEVICE); | |
3bd7f658 | 489 | |
b31a9299 LW |
490 | sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; |
491 | sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; | |
3bd7f658 LW |
492 | } |
493 | ||
494 | /* | |
495 | * Write remaining TX prologue. Adjust first entry in TX sglist. | |
496 | * Also adjust second entry if prologue spills over to it. | |
497 | */ | |
498 | tx_remaining = bs->tx_prologue - bs->rx_prologue; | |
499 | if (tx_remaining) { | |
500 | bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining); | |
501 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA | |
502 | | BCM2835_SPI_CS_DMAEN); | |
503 | bcm2835_wr_fifo_count(bs, tx_remaining); | |
504 | bcm2835_wait_tx_fifo_empty(bs); | |
505 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX); | |
506 | } | |
507 | ||
508 | if (likely(!bs->tx_spillover)) { | |
b31a9299 LW |
509 | sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; |
510 | sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; | |
3bd7f658 | 511 | } else { |
b31a9299 LW |
512 | sg_dma_len(&tfr->tx_sg.sgl[0]) = 0; |
513 | sg_dma_address(&tfr->tx_sg.sgl[1]) += 4; | |
514 | sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4; | |
3bd7f658 LW |
515 | } |
516 | } | |
517 | ||
518 | /** | |
519 | * bcm2835_spi_undo_prologue() - reconstruct original sglist state | |
520 | * @bs: BCM2835 SPI controller | |
521 | * | |
522 | * Undo changes which were made to an SPI transfer's sglist when transmitting | |
523 | * the prologue. This is necessary to ensure the same memory ranges are | |
524 | * unmapped that were originally mapped. | |
525 | */ | |
526 | static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs) | |
527 | { | |
528 | struct spi_transfer *tfr = bs->tfr; | |
529 | ||
530 | if (!bs->tx_prologue) | |
531 | return; | |
532 | ||
533 | if (bs->rx_prologue) { | |
b31a9299 LW |
534 | sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; |
535 | sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; | |
3bd7f658 LW |
536 | } |
537 | ||
538 | if (likely(!bs->tx_spillover)) { | |
b31a9299 LW |
539 | sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; |
540 | sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; | |
3bd7f658 | 541 | } else { |
b31a9299 LW |
542 | sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4; |
543 | sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4; | |
544 | sg_dma_len(&tfr->tx_sg.sgl[1]) += 4; | |
3bd7f658 | 545 | } |
1513ceee LW |
546 | |
547 | bs->tx_prologue = 0; | |
3bd7f658 LW |
548 | } |
549 | ||
3ecd37ed MS |
550 | static void bcm2835_spi_dma_done(void *data) |
551 | { | |
5f336ea5 LW |
552 | struct spi_controller *ctlr = data; |
553 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
3ecd37ed MS |
554 | |
555 | /* reset fifo and HW */ | |
5f336ea5 | 556 | bcm2835_spi_reset_hw(ctlr); |
3ecd37ed MS |
557 | |
558 | /* and terminate tx-dma as we do not have an irq for it | |
559 | * because when the rx dma will terminate and this callback | |
560 | * is called the tx-dma must have finished - can't get to this | |
561 | * situation otherwise... | |
562 | */ | |
1513ceee LW |
563 | dmaengine_terminate_async(ctlr->dma_tx); |
564 | bcm2835_spi_undo_prologue(bs); | |
3ecd37ed MS |
565 | |
566 | /* and mark as completed */; | |
5f336ea5 | 567 | complete(&ctlr->xfer_completion); |
3ecd37ed MS |
568 | } |
569 | ||
5f336ea5 | 570 | static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr, |
3ecd37ed MS |
571 | struct spi_transfer *tfr, |
572 | bool is_tx) | |
573 | { | |
574 | struct dma_chan *chan; | |
575 | struct scatterlist *sgl; | |
576 | unsigned int nents; | |
577 | enum dma_transfer_direction dir; | |
578 | unsigned long flags; | |
579 | ||
580 | struct dma_async_tx_descriptor *desc; | |
581 | dma_cookie_t cookie; | |
582 | ||
583 | if (is_tx) { | |
584 | dir = DMA_MEM_TO_DEV; | |
5f336ea5 | 585 | chan = ctlr->dma_tx; |
3ecd37ed MS |
586 | nents = tfr->tx_sg.nents; |
587 | sgl = tfr->tx_sg.sgl; | |
588 | flags = 0 /* no tx interrupt */; | |
589 | ||
590 | } else { | |
591 | dir = DMA_DEV_TO_MEM; | |
5f336ea5 | 592 | chan = ctlr->dma_rx; |
3ecd37ed MS |
593 | nents = tfr->rx_sg.nents; |
594 | sgl = tfr->rx_sg.sgl; | |
595 | flags = DMA_PREP_INTERRUPT; | |
596 | } | |
597 | /* prepare the channel */ | |
598 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
599 | if (!desc) | |
600 | return -EINVAL; | |
601 | ||
602 | /* set callback for rx */ | |
603 | if (!is_tx) { | |
604 | desc->callback = bcm2835_spi_dma_done; | |
5f336ea5 | 605 | desc->callback_param = ctlr; |
3ecd37ed MS |
606 | } |
607 | ||
608 | /* submit it to DMA-engine */ | |
609 | cookie = dmaengine_submit(desc); | |
610 | ||
611 | return dma_submit_error(cookie); | |
612 | } | |
613 | ||
5f336ea5 | 614 | static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr, |
3ecd37ed MS |
615 | struct spi_device *spi, |
616 | struct spi_transfer *tfr, | |
617 | u32 cs) | |
618 | { | |
5f336ea5 | 619 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
3ecd37ed MS |
620 | int ret; |
621 | ||
154f7da5 MS |
622 | /* update usage statistics */ |
623 | bs->count_transfer_dma++; | |
624 | ||
3bd7f658 LW |
625 | /* |
626 | * Transfer first few bytes without DMA if length of first TX or RX | |
627 | * sglist entry is not a multiple of 4 bytes (hardware limitation). | |
628 | */ | |
5f336ea5 | 629 | bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs); |
3ecd37ed MS |
630 | |
631 | /* setup tx-DMA */ | |
5f336ea5 | 632 | ret = bcm2835_spi_prepare_sg(ctlr, tfr, true); |
3ecd37ed | 633 | if (ret) |
3bd7f658 | 634 | goto err_reset_hw; |
3ecd37ed MS |
635 | |
636 | /* start TX early */ | |
5f336ea5 | 637 | dma_async_issue_pending(ctlr->dma_tx); |
3ecd37ed | 638 | |
3ecd37ed | 639 | /* set the DMA length */ |
3bd7f658 | 640 | bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len); |
3ecd37ed MS |
641 | |
642 | /* start the HW */ | |
643 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
644 | cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); | |
645 | ||
646 | /* setup rx-DMA late - to run transfers while | |
647 | * mapping of the rx buffers still takes place | |
648 | * this saves 10us or more. | |
649 | */ | |
5f336ea5 | 650 | ret = bcm2835_spi_prepare_sg(ctlr, tfr, false); |
3ecd37ed MS |
651 | if (ret) { |
652 | /* need to reset on errors */ | |
5f336ea5 | 653 | dmaengine_terminate_sync(ctlr->dma_tx); |
3bd7f658 | 654 | goto err_reset_hw; |
3ecd37ed MS |
655 | } |
656 | ||
657 | /* start rx dma late */ | |
5f336ea5 | 658 | dma_async_issue_pending(ctlr->dma_rx); |
3ecd37ed MS |
659 | |
660 | /* wait for wakeup in framework */ | |
661 | return 1; | |
3bd7f658 LW |
662 | |
663 | err_reset_hw: | |
5f336ea5 | 664 | bcm2835_spi_reset_hw(ctlr); |
3bd7f658 LW |
665 | bcm2835_spi_undo_prologue(bs); |
666 | return ret; | |
3ecd37ed MS |
667 | } |
668 | ||
5f336ea5 | 669 | static bool bcm2835_spi_can_dma(struct spi_controller *ctlr, |
3ecd37ed MS |
670 | struct spi_device *spi, |
671 | struct spi_transfer *tfr) | |
672 | { | |
3ecd37ed MS |
673 | /* we start DMA efforts only on bigger transfers */ |
674 | if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) | |
675 | return false; | |
676 | ||
3ecd37ed MS |
677 | /* return OK */ |
678 | return true; | |
679 | } | |
680 | ||
5f336ea5 | 681 | static void bcm2835_dma_release(struct spi_controller *ctlr) |
3ecd37ed | 682 | { |
5f336ea5 LW |
683 | if (ctlr->dma_tx) { |
684 | dmaengine_terminate_sync(ctlr->dma_tx); | |
685 | dma_release_channel(ctlr->dma_tx); | |
686 | ctlr->dma_tx = NULL; | |
3ecd37ed | 687 | } |
5f336ea5 LW |
688 | if (ctlr->dma_rx) { |
689 | dmaengine_terminate_sync(ctlr->dma_rx); | |
690 | dma_release_channel(ctlr->dma_rx); | |
691 | ctlr->dma_rx = NULL; | |
3ecd37ed MS |
692 | } |
693 | } | |
694 | ||
5f336ea5 | 695 | static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev) |
3ecd37ed MS |
696 | { |
697 | struct dma_slave_config slave_config; | |
698 | const __be32 *addr; | |
699 | dma_addr_t dma_reg_base; | |
700 | int ret; | |
701 | ||
702 | /* base address in dma-space */ | |
5f336ea5 | 703 | addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL); |
3ecd37ed MS |
704 | if (!addr) { |
705 | dev_err(dev, "could not get DMA-register address - not using dma mode\n"); | |
706 | goto err; | |
707 | } | |
708 | dma_reg_base = be32_to_cpup(addr); | |
709 | ||
710 | /* get tx/rx dma */ | |
5f336ea5 LW |
711 | ctlr->dma_tx = dma_request_slave_channel(dev, "tx"); |
712 | if (!ctlr->dma_tx) { | |
3ecd37ed MS |
713 | dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); |
714 | goto err; | |
715 | } | |
5f336ea5 LW |
716 | ctlr->dma_rx = dma_request_slave_channel(dev, "rx"); |
717 | if (!ctlr->dma_rx) { | |
3ecd37ed MS |
718 | dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); |
719 | goto err_release; | |
720 | } | |
721 | ||
722 | /* configure DMAs */ | |
3ecd37ed MS |
723 | slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); |
724 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
725 | ||
5f336ea5 | 726 | ret = dmaengine_slave_config(ctlr->dma_tx, &slave_config); |
3ecd37ed MS |
727 | if (ret) |
728 | goto err_config; | |
729 | ||
3ecd37ed MS |
730 | slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); |
731 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
732 | ||
5f336ea5 | 733 | ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config); |
3ecd37ed MS |
734 | if (ret) |
735 | goto err_config; | |
736 | ||
737 | /* all went well, so set can_dma */ | |
5f336ea5 | 738 | ctlr->can_dma = bcm2835_spi_can_dma; |
3ecd37ed | 739 | /* need to do TX AND RX DMA, so we need dummy buffers */ |
5f336ea5 | 740 | ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; |
3ecd37ed MS |
741 | |
742 | return; | |
743 | ||
744 | err_config: | |
745 | dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", | |
746 | ret); | |
747 | err_release: | |
5f336ea5 | 748 | bcm2835_dma_release(ctlr); |
3ecd37ed MS |
749 | err: |
750 | return; | |
751 | } | |
752 | ||
5f336ea5 | 753 | static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr, |
a750b124 MS |
754 | struct spi_device *spi, |
755 | struct spi_transfer *tfr, | |
9ac3f90d | 756 | u32 cs) |
a750b124 | 757 | { |
5f336ea5 | 758 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
a750b124 MS |
759 | unsigned long timeout; |
760 | ||
154f7da5 MS |
761 | /* update usage statistics */ |
762 | bs->count_transfer_polling++; | |
763 | ||
a750b124 MS |
764 | /* enable HW block without interrupts */ |
765 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); | |
766 | ||
767 | /* fill in the fifo before timeout calculations | |
768 | * if we are interrupted here, then the data is | |
769 | * getting transferred by the HW while we are interrupted | |
770 | */ | |
2e0733bc | 771 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); |
a750b124 | 772 | |
ff245d90 MS |
773 | /* set the timeout to at least 2 jiffies */ |
774 | timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; | |
a750b124 MS |
775 | |
776 | /* loop until finished the transfer */ | |
777 | while (bs->rx_len) { | |
778 | /* fill in tx fifo with remaining data */ | |
779 | bcm2835_wr_fifo(bs); | |
780 | ||
781 | /* read from fifo as much as possible */ | |
782 | bcm2835_rd_fifo(bs); | |
783 | ||
784 | /* if there is still data pending to read | |
785 | * then check the timeout | |
786 | */ | |
787 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
788 | dev_dbg_ratelimited(&spi->dev, | |
789 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
790 | jiffies - timeout, | |
791 | bs->tx_len, bs->rx_len); | |
792 | /* fall back to interrupt mode */ | |
154f7da5 MS |
793 | |
794 | /* update usage statistics */ | |
795 | bs->count_transfer_irq_after_polling++; | |
796 | ||
5f336ea5 | 797 | return bcm2835_spi_transfer_one_irq(ctlr, spi, |
2e0733bc | 798 | tfr, cs, false); |
a750b124 MS |
799 | } |
800 | } | |
801 | ||
802 | /* Transfer complete - reset SPI HW */ | |
5f336ea5 | 803 | bcm2835_spi_reset_hw(ctlr); |
a750b124 MS |
804 | /* and return without waiting for completion */ |
805 | return 0; | |
806 | } | |
807 | ||
5f336ea5 | 808 | static int bcm2835_spi_transfer_one(struct spi_controller *ctlr, |
e34ff011 MS |
809 | struct spi_device *spi, |
810 | struct spi_transfer *tfr) | |
f8043872 | 811 | { |
5f336ea5 | 812 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
ff245d90 MS |
813 | unsigned long spi_hz, clk_hz, cdiv, spi_used_hz; |
814 | unsigned long hz_per_byte, byte_limit; | |
571e31fa | 815 | u32 cs = bs->prepare_cs[spi->chip_select]; |
f8043872 | 816 | |
e34ff011 | 817 | /* set clock */ |
f8043872 CB |
818 | spi_hz = tfr->speed_hz; |
819 | clk_hz = clk_get_rate(bs->clk); | |
820 | ||
821 | if (spi_hz >= clk_hz / 2) { | |
822 | cdiv = 2; /* clk_hz/2 is the fastest we can go */ | |
823 | } else if (spi_hz) { | |
210b4923 MS |
824 | /* CDIV must be a multiple of two */ |
825 | cdiv = DIV_ROUND_UP(clk_hz, spi_hz); | |
826 | cdiv += (cdiv % 2); | |
f8043872 CB |
827 | |
828 | if (cdiv >= 65536) | |
829 | cdiv = 0; /* 0 is the slowest we can go */ | |
342f948a | 830 | } else { |
f8043872 | 831 | cdiv = 0; /* 0 is the slowest we can go */ |
342f948a | 832 | } |
704f32d4 | 833 | spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); |
e34ff011 | 834 | bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); |
f8043872 | 835 | |
acace73d | 836 | /* handle all the 3-wire mode */ |
8d8bef50 LW |
837 | if (spi->mode & SPI_3WIRE && tfr->rx_buf && |
838 | tfr->rx_buf != ctlr->dummy_rx) | |
6935224d | 839 | cs |= BCM2835_SPI_CS_REN; |
f8043872 | 840 | |
e34ff011 | 841 | /* set transmit buffers and length */ |
f8043872 CB |
842 | bs->tx_buf = tfr->tx_buf; |
843 | bs->rx_buf = tfr->rx_buf; | |
e34ff011 MS |
844 | bs->tx_len = tfr->len; |
845 | bs->rx_len = tfr->len; | |
f8043872 | 846 | |
7f1922eb MS |
847 | /* Calculate the estimated time in us the transfer runs. Note that |
848 | * there is 1 idle clocks cycles after each byte getting transferred | |
849 | * so we have 9 cycles/byte. This is used to find the number of Hz | |
850 | * per byte per polling limit. E.g., we can transfer 1 byte in 30 us | |
851 | * per 300,000 Hz of bus clock. | |
852 | */ | |
ff245d90 MS |
853 | hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; |
854 | byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1; | |
855 | ||
7f1922eb | 856 | /* run in polling mode for short transfers */ |
ff245d90 | 857 | if (tfr->len < byte_limit) |
5f336ea5 | 858 | return bcm2835_spi_transfer_one_poll(ctlr, spi, tfr, cs); |
f8043872 | 859 | |
c41d62b0 MS |
860 | /* run in dma mode if conditions are right |
861 | * Note that unlike poll or interrupt mode DMA mode does not have | |
862 | * this 1 idle clock cycle pattern but runs the spi clock without gaps | |
863 | */ | |
5f336ea5 LW |
864 | if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr)) |
865 | return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs); | |
3ecd37ed MS |
866 | |
867 | /* run in interrupt-mode */ | |
5f336ea5 | 868 | return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true); |
f8043872 CB |
869 | } |
870 | ||
5f336ea5 | 871 | static int bcm2835_spi_prepare_message(struct spi_controller *ctlr, |
acace73d MS |
872 | struct spi_message *msg) |
873 | { | |
874 | struct spi_device *spi = msg->spi; | |
5f336ea5 | 875 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
8b7bd10e MM |
876 | int ret; |
877 | ||
5f336ea5 | 878 | if (ctlr->can_dma) { |
3393f7d9 NSJ |
879 | /* |
880 | * DMA transfers are limited to 16 bit (0 to 65535 bytes) by | |
881 | * the SPI HW due to DLEN. Split up transfers (32-bit FIFO | |
882 | * aligned) if the limit is exceeded. | |
883 | */ | |
5f336ea5 | 884 | ret = spi_split_transfers_maxsize(ctlr, msg, 65532, |
3393f7d9 NSJ |
885 | GFP_KERNEL | GFP_DMA); |
886 | if (ret) | |
887 | return ret; | |
888 | } | |
acace73d | 889 | |
571e31fa LW |
890 | /* |
891 | * Set up clock polarity before spi_transfer_one_message() asserts | |
892 | * chip select to avoid a gratuitous clock signal edge. | |
893 | */ | |
894 | bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]); | |
acace73d MS |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
5f336ea5 | 899 | static void bcm2835_spi_handle_err(struct spi_controller *ctlr, |
e34ff011 | 900 | struct spi_message *msg) |
f8043872 | 901 | { |
5f336ea5 | 902 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
3ecd37ed MS |
903 | |
904 | /* if an error occurred and we have an active dma, then terminate */ | |
1513ceee LW |
905 | dmaengine_terminate_sync(ctlr->dma_tx); |
906 | dmaengine_terminate_sync(ctlr->dma_rx); | |
907 | bcm2835_spi_undo_prologue(bs); | |
908 | ||
3ecd37ed | 909 | /* and reset */ |
5f336ea5 | 910 | bcm2835_spi_reset_hw(ctlr); |
f8043872 CB |
911 | } |
912 | ||
a30a555d MS |
913 | static int chip_match_name(struct gpio_chip *chip, void *data) |
914 | { | |
915 | return !strcmp(chip->label, data); | |
916 | } | |
917 | ||
e34ff011 MS |
918 | static int bcm2835_spi_setup(struct spi_device *spi) |
919 | { | |
571e31fa | 920 | struct bcm2835_spi *bs = spi_controller_get_devdata(spi->controller); |
a30a555d | 921 | struct gpio_chip *chip; |
3bd158c5 | 922 | enum gpio_lookup_flags lflags; |
571e31fa LW |
923 | u32 cs; |
924 | ||
925 | /* | |
926 | * Precalculate SPI slave's CS register value for ->prepare_message(): | |
927 | * The driver always uses software-controlled GPIO chip select, hence | |
928 | * set the hardware-controlled native chip select to an invalid value | |
929 | * to prevent it from interfering. | |
930 | */ | |
931 | cs = BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; | |
932 | if (spi->mode & SPI_CPOL) | |
933 | cs |= BCM2835_SPI_CS_CPOL; | |
934 | if (spi->mode & SPI_CPHA) | |
935 | cs |= BCM2835_SPI_CS_CPHA; | |
936 | bs->prepare_cs[spi->chip_select] = cs; | |
3bd158c5 | 937 | |
e34ff011 MS |
938 | /* |
939 | * sanity checking the native-chipselects | |
940 | */ | |
941 | if (spi->mode & SPI_NO_CS) | |
942 | return 0; | |
3bd158c5 LW |
943 | /* |
944 | * The SPI core has successfully requested the CS GPIO line from the | |
945 | * device tree, so we are done. | |
946 | */ | |
947 | if (spi->cs_gpiod) | |
e34ff011 | 948 | return 0; |
a30a555d MS |
949 | if (spi->chip_select > 1) { |
950 | /* error in the case of native CS requested with CS > 1 | |
951 | * officially there is a CS2, but it is not documented | |
952 | * which GPIO is connected with that... | |
953 | */ | |
954 | dev_err(&spi->dev, | |
955 | "setup: only two native chip-selects are supported\n"); | |
956 | return -EINVAL; | |
957 | } | |
3bd158c5 LW |
958 | |
959 | /* | |
960 | * Translate native CS to GPIO | |
961 | * | |
962 | * FIXME: poking around in the gpiolib internals like this is | |
963 | * not very good practice. Find a way to locate the real problem | |
964 | * and fix it. Why is the GPIO descriptor in spi->cs_gpiod | |
965 | * sometimes not assigned correctly? Erroneous device trees? | |
966 | */ | |
a30a555d MS |
967 | |
968 | /* get the gpio chip for the base */ | |
969 | chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); | |
970 | if (!chip) | |
e34ff011 MS |
971 | return 0; |
972 | ||
3bd158c5 LW |
973 | /* |
974 | * Retrieve the corresponding GPIO line used for CS. | |
975 | * The inversion semantics will be handled by the GPIO core | |
976 | * code, so we pass GPIOS_OUT_LOW for "unasserted" and | |
977 | * the correct flag for inversion semantics. The SPI_CS_HIGH | |
978 | * on spi->mode cannot be checked for polarity in this case | |
979 | * as the flag use_gpio_descriptors enforces SPI_CS_HIGH. | |
980 | */ | |
981 | if (of_property_read_bool(spi->dev.of_node, "spi-cs-high")) | |
982 | lflags = GPIO_ACTIVE_HIGH; | |
983 | else | |
984 | lflags = GPIO_ACTIVE_LOW; | |
985 | spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select, | |
986 | DRV_NAME, | |
987 | lflags, | |
988 | GPIOD_OUT_LOW); | |
989 | if (IS_ERR(spi->cs_gpiod)) | |
990 | return PTR_ERR(spi->cs_gpiod); | |
a30a555d MS |
991 | |
992 | /* and set up the "mode" and level */ | |
3bd158c5 LW |
993 | dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n", |
994 | spi->chip_select); | |
a30a555d MS |
995 | |
996 | return 0; | |
f8043872 CB |
997 | } |
998 | ||
999 | static int bcm2835_spi_probe(struct platform_device *pdev) | |
1000 | { | |
5f336ea5 | 1001 | struct spi_controller *ctlr; |
f8043872 | 1002 | struct bcm2835_spi *bs; |
f8043872 CB |
1003 | int err; |
1004 | ||
5f336ea5 LW |
1005 | ctlr = spi_alloc_master(&pdev->dev, sizeof(*bs)); |
1006 | if (!ctlr) | |
f8043872 | 1007 | return -ENOMEM; |
f8043872 | 1008 | |
5f336ea5 | 1009 | platform_set_drvdata(pdev, ctlr); |
f8043872 | 1010 | |
3bd158c5 | 1011 | ctlr->use_gpio_descriptors = true; |
5f336ea5 LW |
1012 | ctlr->mode_bits = BCM2835_SPI_MODE_BITS; |
1013 | ctlr->bits_per_word_mask = SPI_BPW_MASK(8); | |
571e31fa | 1014 | ctlr->num_chipselect = BCM2835_SPI_NUM_CS; |
5f336ea5 LW |
1015 | ctlr->setup = bcm2835_spi_setup; |
1016 | ctlr->transfer_one = bcm2835_spi_transfer_one; | |
1017 | ctlr->handle_err = bcm2835_spi_handle_err; | |
1018 | ctlr->prepare_message = bcm2835_spi_prepare_message; | |
1019 | ctlr->dev.of_node = pdev->dev.of_node; | |
f8043872 | 1020 | |
5f336ea5 | 1021 | bs = spi_controller_get_devdata(ctlr); |
f8043872 | 1022 | |
6ba794df | 1023 | bs->regs = devm_platform_ioremap_resource(pdev, 0); |
2d6e75e8 LN |
1024 | if (IS_ERR(bs->regs)) { |
1025 | err = PTR_ERR(bs->regs); | |
5f336ea5 | 1026 | goto out_controller_put; |
f8043872 CB |
1027 | } |
1028 | ||
1029 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
1030 | if (IS_ERR(bs->clk)) { | |
1031 | err = PTR_ERR(bs->clk); | |
1032 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
5f336ea5 | 1033 | goto out_controller_put; |
f8043872 CB |
1034 | } |
1035 | ||
ddf0e1c2 | 1036 | bs->irq = platform_get_irq(pdev, 0); |
f8043872 | 1037 | if (bs->irq <= 0) { |
f8043872 | 1038 | err = bs->irq ? bs->irq : -ENODEV; |
5f336ea5 | 1039 | goto out_controller_put; |
f8043872 CB |
1040 | } |
1041 | ||
1042 | clk_prepare_enable(bs->clk); | |
1043 | ||
5f336ea5 | 1044 | bcm2835_dma_init(ctlr, &pdev->dev); |
ddf0e1c2 MS |
1045 | |
1046 | /* initialise the hardware with the default polarities */ | |
1047 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
1048 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
1049 | ||
08bc0544 | 1050 | err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, |
5f336ea5 | 1051 | dev_name(&pdev->dev), ctlr); |
f8043872 CB |
1052 | if (err) { |
1053 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
1054 | goto out_clk_disable; | |
1055 | } | |
1056 | ||
5f336ea5 | 1057 | err = devm_spi_register_controller(&pdev->dev, ctlr); |
f8043872 | 1058 | if (err) { |
5f336ea5 LW |
1059 | dev_err(&pdev->dev, "could not register SPI controller: %d\n", |
1060 | err); | |
08bc0544 | 1061 | goto out_clk_disable; |
f8043872 CB |
1062 | } |
1063 | ||
154f7da5 MS |
1064 | bcm2835_debugfs_create(bs, dev_name(&pdev->dev)); |
1065 | ||
f8043872 CB |
1066 | return 0; |
1067 | ||
f8043872 CB |
1068 | out_clk_disable: |
1069 | clk_disable_unprepare(bs->clk); | |
5f336ea5 LW |
1070 | out_controller_put: |
1071 | spi_controller_put(ctlr); | |
f8043872 CB |
1072 | return err; |
1073 | } | |
1074 | ||
1075 | static int bcm2835_spi_remove(struct platform_device *pdev) | |
1076 | { | |
5f336ea5 LW |
1077 | struct spi_controller *ctlr = platform_get_drvdata(pdev); |
1078 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
f8043872 | 1079 | |
154f7da5 MS |
1080 | bcm2835_debugfs_remove(bs); |
1081 | ||
f8043872 CB |
1082 | /* Clear FIFOs, and disable the HW block */ |
1083 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
1084 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
1085 | ||
1086 | clk_disable_unprepare(bs->clk); | |
f8043872 | 1087 | |
5f336ea5 | 1088 | bcm2835_dma_release(ctlr); |
3ecd37ed | 1089 | |
f8043872 CB |
1090 | return 0; |
1091 | } | |
1092 | ||
1093 | static const struct of_device_id bcm2835_spi_match[] = { | |
1094 | { .compatible = "brcm,bcm2835-spi", }, | |
1095 | {} | |
1096 | }; | |
1097 | MODULE_DEVICE_TABLE(of, bcm2835_spi_match); | |
1098 | ||
1099 | static struct platform_driver bcm2835_spi_driver = { | |
1100 | .driver = { | |
1101 | .name = DRV_NAME, | |
f8043872 CB |
1102 | .of_match_table = bcm2835_spi_match, |
1103 | }, | |
1104 | .probe = bcm2835_spi_probe, | |
1105 | .remove = bcm2835_spi_remove, | |
1106 | }; | |
1107 | module_platform_driver(bcm2835_spi_driver); | |
1108 | ||
1109 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); | |
1110 | MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); | |
22bf6cd2 | 1111 | MODULE_LICENSE("GPL"); |