spi: bcm2835: Avoid 64-bit arithmetic in xfer len calc
[linux-2.6-block.git] / drivers / spi / spi-bcm2835.c
CommitLineData
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1/*
2 * Driver for Broadcom BCM2835 SPI Controllers
3 *
4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren
e34ff011 6 * Copyright (C) 2015 Martin Sperl
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7 *
8 * This driver is inspired by:
9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
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21 */
22
23#include <linux/clk.h>
24#include <linux/completion.h>
25#include <linux/delay.h>
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26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
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28#include <linux/err.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/of.h>
3ecd37ed 34#include <linux/of_address.h>
f8043872 35#include <linux/of_device.h>
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36#include <linux/of_gpio.h>
37#include <linux/of_irq.h>
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38#include <linux/spi/spi.h>
39
40/* SPI register offsets */
41#define BCM2835_SPI_CS 0x00
42#define BCM2835_SPI_FIFO 0x04
43#define BCM2835_SPI_CLK 0x08
44#define BCM2835_SPI_DLEN 0x0c
45#define BCM2835_SPI_LTOH 0x10
46#define BCM2835_SPI_DC 0x14
47
48/* Bitfields in CS */
49#define BCM2835_SPI_CS_LEN_LONG 0x02000000
50#define BCM2835_SPI_CS_DMA_LEN 0x01000000
51#define BCM2835_SPI_CS_CSPOL2 0x00800000
52#define BCM2835_SPI_CS_CSPOL1 0x00400000
53#define BCM2835_SPI_CS_CSPOL0 0x00200000
54#define BCM2835_SPI_CS_RXF 0x00100000
55#define BCM2835_SPI_CS_RXR 0x00080000
56#define BCM2835_SPI_CS_TXD 0x00040000
57#define BCM2835_SPI_CS_RXD 0x00020000
58#define BCM2835_SPI_CS_DONE 0x00010000
59#define BCM2835_SPI_CS_LEN 0x00002000
60#define BCM2835_SPI_CS_REN 0x00001000
61#define BCM2835_SPI_CS_ADCS 0x00000800
62#define BCM2835_SPI_CS_INTR 0x00000400
63#define BCM2835_SPI_CS_INTD 0x00000200
64#define BCM2835_SPI_CS_DMAEN 0x00000100
65#define BCM2835_SPI_CS_TA 0x00000080
66#define BCM2835_SPI_CS_CSPOL 0x00000040
67#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
68#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
69#define BCM2835_SPI_CS_CPOL 0x00000008
70#define BCM2835_SPI_CS_CPHA 0x00000004
71#define BCM2835_SPI_CS_CS_10 0x00000002
72#define BCM2835_SPI_CS_CS_01 0x00000001
73
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74#define BCM2835_SPI_FIFO_SIZE 64
75#define BCM2835_SPI_FIFO_SIZE_3_4 48
704f32d4 76#define BCM2835_SPI_POLLING_LIMIT_US 30
a750b124 77#define BCM2835_SPI_POLLING_JIFFIES 2
3ecd37ed 78#define BCM2835_SPI_DMA_MIN_LENGTH 96
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79#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
80 | SPI_NO_CS | SPI_3WIRE)
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81
82#define DRV_NAME "spi-bcm2835"
83
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84/**
85 * struct bcm2835_spi - BCM2835 SPI controller
86 * @regs: base address of register map
87 * @clk: core clock, divided to calculate serial clock
88 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
3bd7f658 89 * @tfr: SPI transfer currently processed
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90 * @tx_buf: pointer whence next transmitted byte is read
91 * @rx_buf: pointer where next received byte is written
92 * @tx_len: remaining bytes to transmit
93 * @rx_len: remaining bytes to receive
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94 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
95 * length is not a multiple of 4 (to overcome hardware limitation)
96 * @rx_prologue: bytes received without DMA if first RX sglist entry's
97 * length is not a multiple of 4 (to overcome hardware limitation)
98 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
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99 * @dma_pending: whether a DMA transfer is in progress
100 */
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101struct bcm2835_spi {
102 void __iomem *regs;
103 struct clk *clk;
104 int irq;
3bd7f658 105 struct spi_transfer *tfr;
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106 const u8 *tx_buf;
107 u8 *rx_buf;
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108 int tx_len;
109 int rx_len;
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110 int tx_prologue;
111 int rx_prologue;
b31a9299 112 unsigned int tx_spillover;
29bdedfd 113 unsigned int dma_pending;
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114};
115
116static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
117{
118 return readl(bs->regs + reg);
119}
120
121static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
122{
123 writel(val, bs->regs + reg);
124}
125
4adf3129 126static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
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127{
128 u8 byte;
129
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130 while ((bs->rx_len) &&
131 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
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132 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
133 if (bs->rx_buf)
134 *bs->rx_buf++ = byte;
e34ff011 135 bs->rx_len--;
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136 }
137}
138
4adf3129 139static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
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140{
141 u8 byte;
142
e34ff011 143 while ((bs->tx_len) &&
4adf3129 144 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
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145 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
146 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
e34ff011 147 bs->tx_len--;
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148 }
149}
150
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151/**
152 * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
153 * @bs: BCM2835 SPI controller
154 * @count: bytes to read from RX FIFO
155 *
156 * The caller must ensure that @bs->rx_len is greater than or equal to @count,
157 * that the RX FIFO contains at least @count bytes and that the DMA Enable flag
158 * in the CS register is set (such that a read from the FIFO register receives
b31a9299 159 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
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160 */
161static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
162{
163 u32 val;
b31a9299 164 int len;
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165
166 bs->rx_len -= count;
167
168 while (count > 0) {
169 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
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170 len = min(count, 4);
171 memcpy(bs->rx_buf, &val, len);
172 bs->rx_buf += len;
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173 count -= 4;
174 }
175}
176
177/**
178 * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
179 * @bs: BCM2835 SPI controller
180 * @count: bytes to write to TX FIFO
181 *
182 * The caller must ensure that @bs->tx_len is greater than or equal to @count,
183 * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
184 * in the CS register is set (such that a write to the FIFO register transmits
185 * 32-bit instead of just 8-bit).
186 */
187static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
188{
189 u32 val;
b31a9299 190 int len;
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191
192 bs->tx_len -= count;
193
194 while (count > 0) {
195 if (bs->tx_buf) {
b31a9299 196 len = min(count, 4);
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197 memcpy(&val, bs->tx_buf, len);
198 bs->tx_buf += len;
199 } else {
200 val = 0;
201 }
202 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
203 count -= 4;
204 }
205}
206
207/**
208 * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
209 * @bs: BCM2835 SPI controller
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210 *
211 * The caller must ensure that the RX FIFO can accommodate as many bytes
212 * as have been written to the TX FIFO: Transmission is halted once the
213 * RX FIFO is full, causing this function to spin forever.
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214 */
215static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
216{
217 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
218 cpu_relax();
219}
220
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221/**
222 * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
223 * @bs: BCM2835 SPI controller
224 * @count: bytes available for reading in RX FIFO
225 */
226static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
227{
228 u8 val;
229
230 count = min(count, bs->rx_len);
231 bs->rx_len -= count;
232
233 while (count) {
234 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
235 if (bs->rx_buf)
236 *bs->rx_buf++ = val;
237 count--;
238 }
239}
240
241/**
242 * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
243 * @bs: BCM2835 SPI controller
244 * @count: bytes available for writing in TX FIFO
245 */
246static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
247{
248 u8 val;
249
250 count = min(count, bs->tx_len);
251 bs->tx_len -= count;
252
253 while (count) {
254 val = bs->tx_buf ? *bs->tx_buf++ : 0;
255 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
256 count--;
257 }
258}
259
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260static void bcm2835_spi_reset_hw(struct spi_master *master)
261{
262 struct bcm2835_spi *bs = spi_master_get_devdata(master);
263 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
264
265 /* Disable SPI interrupts and transfer */
266 cs &= ~(BCM2835_SPI_CS_INTR |
267 BCM2835_SPI_CS_INTD |
3ecd37ed 268 BCM2835_SPI_CS_DMAEN |
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269 BCM2835_SPI_CS_TA);
270 /* and reset RX/TX FIFOS */
271 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
272
273 /* and reset the SPI_HW */
274 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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275 /* as well as DLEN */
276 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
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277}
278
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279static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
280{
281 struct spi_master *master = dev_id;
282 struct bcm2835_spi *bs = spi_master_get_devdata(master);
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283 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
284
285 /*
286 * An interrupt is signaled either if DONE is set (TX FIFO empty)
287 * or if RXR is set (RX FIFO >= ¾ full).
288 */
289 if (cs & BCM2835_SPI_CS_RXF)
290 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
291 else if (cs & BCM2835_SPI_CS_RXR)
292 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
293
294 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
295 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
f8043872 296
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297 /* Read as many bytes as possible from FIFO */
298 bcm2835_rd_fifo(bs);
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299 /* Write as many bytes as possible to FIFO */
300 bcm2835_wr_fifo(bs);
301
56c17234 302 if (!bs->rx_len) {
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303 /* Transfer complete - reset SPI HW */
304 bcm2835_spi_reset_hw(master);
305 /* wake up the framework */
306 complete(&master->xfer_completion);
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307 }
308
4adf3129 309 return IRQ_HANDLED;
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310}
311
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312static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
313 struct spi_device *spi,
314 struct spi_transfer *tfr,
2e0733bc 315 u32 cs, bool fifo_empty)
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316{
317 struct bcm2835_spi *bs = spi_master_get_devdata(master);
318
704f32d4 319 /*
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320 * Enable HW block, but with interrupts still disabled.
321 * Otherwise the empty TX FIFO would immediately trigger an interrupt.
704f32d4 322 */
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323 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
324
325 /* fill TX FIFO as much as possible */
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326 if (fifo_empty)
327 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
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328 bcm2835_wr_fifo(bs);
329
330 /* enable interrupts */
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331 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
332 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
333
334 /* signal that we need to wait for completion */
335 return 1;
336}
337
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338/**
339 * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
340 * @master: SPI master
341 * @tfr: SPI transfer
342 * @bs: BCM2835 SPI controller
343 * @cs: CS register
344 *
345 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
346 * Only the final write access is permitted to transmit less than 4 bytes, the
347 * SPI controller deduces its intended size from the DLEN register.
348 *
349 * If a TX or RX sglist contains multiple entries, one per page, and the first
350 * entry starts in the middle of a page, that first entry's length may not be
351 * a multiple of 4. Subsequent entries are fine because they span an entire
352 * page, hence do have a length that's a multiple of 4.
353 *
354 * This cannot happen with kmalloc'ed buffers (which is what most clients use)
355 * because they are contiguous in physical memory and therefore not split on
356 * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
357 * buffers.
358 *
359 * The DMA engine is incapable of combining sglist entries into a continuous
360 * stream of 4 byte chunks, it treats every entry separately: A TX entry is
361 * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
362 * entry is rounded up by throwing away received bytes.
363 *
364 * Overcome this limitation by transferring the first few bytes without DMA:
365 * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
366 * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
367 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
368 * the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
369 *
370 * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
371 * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
372 * Caution, the additional 4 bytes spill over to the second TX sglist entry
373 * if the length of the first is *exactly* 1.
374 *
375 * At most 6 bytes are written and at most 3 bytes read. Do we know the
376 * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
377 *
378 * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
379 * by the DMA engine. Toggling the DMA Enable flag in the CS register switches
380 * the width but also garbles the FIFO's contents. The prologue must therefore
381 * be transmitted in 32-bit width to ensure that the following DMA transfer can
382 * pick up the residue in the RX FIFO in ungarbled form.
383 */
384static void bcm2835_spi_transfer_prologue(struct spi_master *master,
385 struct spi_transfer *tfr,
386 struct bcm2835_spi *bs,
387 u32 cs)
388{
389 int tx_remaining;
390
391 bs->tfr = tfr;
392 bs->tx_prologue = 0;
393 bs->rx_prologue = 0;
394 bs->tx_spillover = false;
395
396 if (!sg_is_last(&tfr->tx_sg.sgl[0]))
397 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
398
399 if (!sg_is_last(&tfr->rx_sg.sgl[0])) {
400 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
401
402 if (bs->rx_prologue > bs->tx_prologue) {
403 if (sg_is_last(&tfr->tx_sg.sgl[0])) {
404 bs->tx_prologue = bs->rx_prologue;
405 } else {
406 bs->tx_prologue += 4;
407 bs->tx_spillover =
408 !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
409 }
410 }
411 }
412
413 /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
414 if (!bs->tx_prologue)
415 return;
416
417 /* Write and read RX prologue. Adjust first entry in RX sglist. */
418 if (bs->rx_prologue) {
419 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
420 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
421 | BCM2835_SPI_CS_DMAEN);
422 bcm2835_wr_fifo_count(bs, bs->rx_prologue);
423 bcm2835_wait_tx_fifo_empty(bs);
424 bcm2835_rd_fifo_count(bs, bs->rx_prologue);
425 bcm2835_spi_reset_hw(master);
426
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427 dma_sync_single_for_device(master->dma_rx->device->dev,
428 sg_dma_address(&tfr->rx_sg.sgl[0]),
429 bs->rx_prologue, DMA_FROM_DEVICE);
3bd7f658 430
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431 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
432 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
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433 }
434
435 /*
436 * Write remaining TX prologue. Adjust first entry in TX sglist.
437 * Also adjust second entry if prologue spills over to it.
438 */
439 tx_remaining = bs->tx_prologue - bs->rx_prologue;
440 if (tx_remaining) {
441 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
442 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
443 | BCM2835_SPI_CS_DMAEN);
444 bcm2835_wr_fifo_count(bs, tx_remaining);
445 bcm2835_wait_tx_fifo_empty(bs);
446 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX);
447 }
448
449 if (likely(!bs->tx_spillover)) {
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450 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
451 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
3bd7f658 452 } else {
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453 sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
454 sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
455 sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
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456 }
457}
458
459/**
460 * bcm2835_spi_undo_prologue() - reconstruct original sglist state
461 * @bs: BCM2835 SPI controller
462 *
463 * Undo changes which were made to an SPI transfer's sglist when transmitting
464 * the prologue. This is necessary to ensure the same memory ranges are
465 * unmapped that were originally mapped.
466 */
467static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
468{
469 struct spi_transfer *tfr = bs->tfr;
470
471 if (!bs->tx_prologue)
472 return;
473
474 if (bs->rx_prologue) {
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475 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
476 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
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477 }
478
479 if (likely(!bs->tx_spillover)) {
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480 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
481 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
3bd7f658 482 } else {
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483 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
484 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
485 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
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486 }
487}
488
3ecd37ed
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489static void bcm2835_spi_dma_done(void *data)
490{
491 struct spi_master *master = data;
492 struct bcm2835_spi *bs = spi_master_get_devdata(master);
493
494 /* reset fifo and HW */
495 bcm2835_spi_reset_hw(master);
496
497 /* and terminate tx-dma as we do not have an irq for it
498 * because when the rx dma will terminate and this callback
499 * is called the tx-dma must have finished - can't get to this
500 * situation otherwise...
501 */
e82b0b38 502 if (cmpxchg(&bs->dma_pending, true, false)) {
2527704d 503 dmaengine_terminate_async(master->dma_tx);
3bd7f658 504 bcm2835_spi_undo_prologue(bs);
e82b0b38 505 }
3ecd37ed
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506
507 /* and mark as completed */;
508 complete(&master->xfer_completion);
509}
510
511static int bcm2835_spi_prepare_sg(struct spi_master *master,
512 struct spi_transfer *tfr,
513 bool is_tx)
514{
515 struct dma_chan *chan;
516 struct scatterlist *sgl;
517 unsigned int nents;
518 enum dma_transfer_direction dir;
519 unsigned long flags;
520
521 struct dma_async_tx_descriptor *desc;
522 dma_cookie_t cookie;
523
524 if (is_tx) {
525 dir = DMA_MEM_TO_DEV;
526 chan = master->dma_tx;
527 nents = tfr->tx_sg.nents;
528 sgl = tfr->tx_sg.sgl;
529 flags = 0 /* no tx interrupt */;
530
531 } else {
532 dir = DMA_DEV_TO_MEM;
533 chan = master->dma_rx;
534 nents = tfr->rx_sg.nents;
535 sgl = tfr->rx_sg.sgl;
536 flags = DMA_PREP_INTERRUPT;
537 }
538 /* prepare the channel */
539 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
540 if (!desc)
541 return -EINVAL;
542
543 /* set callback for rx */
544 if (!is_tx) {
545 desc->callback = bcm2835_spi_dma_done;
546 desc->callback_param = master;
547 }
548
549 /* submit it to DMA-engine */
550 cookie = dmaengine_submit(desc);
551
552 return dma_submit_error(cookie);
553}
554
3ecd37ed
MS
555static int bcm2835_spi_transfer_one_dma(struct spi_master *master,
556 struct spi_device *spi,
557 struct spi_transfer *tfr,
558 u32 cs)
559{
560 struct bcm2835_spi *bs = spi_master_get_devdata(master);
561 int ret;
562
3bd7f658
LW
563 /*
564 * Transfer first few bytes without DMA if length of first TX or RX
565 * sglist entry is not a multiple of 4 bytes (hardware limitation).
566 */
567 bcm2835_spi_transfer_prologue(master, tfr, bs, cs);
3ecd37ed
MS
568
569 /* setup tx-DMA */
570 ret = bcm2835_spi_prepare_sg(master, tfr, true);
571 if (ret)
3bd7f658 572 goto err_reset_hw;
3ecd37ed
MS
573
574 /* start TX early */
575 dma_async_issue_pending(master->dma_tx);
576
577 /* mark as dma pending */
578 bs->dma_pending = 1;
579
580 /* set the DMA length */
3bd7f658 581 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
3ecd37ed
MS
582
583 /* start the HW */
584 bcm2835_wr(bs, BCM2835_SPI_CS,
585 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
586
587 /* setup rx-DMA late - to run transfers while
588 * mapping of the rx buffers still takes place
589 * this saves 10us or more.
590 */
591 ret = bcm2835_spi_prepare_sg(master, tfr, false);
592 if (ret) {
593 /* need to reset on errors */
2527704d 594 dmaengine_terminate_sync(master->dma_tx);
dbc94411 595 bs->dma_pending = false;
3bd7f658 596 goto err_reset_hw;
3ecd37ed
MS
597 }
598
599 /* start rx dma late */
600 dma_async_issue_pending(master->dma_rx);
601
602 /* wait for wakeup in framework */
603 return 1;
3bd7f658
LW
604
605err_reset_hw:
606 bcm2835_spi_reset_hw(master);
607 bcm2835_spi_undo_prologue(bs);
608 return ret;
3ecd37ed
MS
609}
610
611static bool bcm2835_spi_can_dma(struct spi_master *master,
612 struct spi_device *spi,
613 struct spi_transfer *tfr)
614{
3ecd37ed
MS
615 /* we start DMA efforts only on bigger transfers */
616 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
617 return false;
618
3ecd37ed
MS
619 /* return OK */
620 return true;
621}
622
29ad1a7a 623static void bcm2835_dma_release(struct spi_master *master)
3ecd37ed
MS
624{
625 if (master->dma_tx) {
2527704d 626 dmaengine_terminate_sync(master->dma_tx);
3ecd37ed
MS
627 dma_release_channel(master->dma_tx);
628 master->dma_tx = NULL;
629 }
630 if (master->dma_rx) {
2527704d 631 dmaengine_terminate_sync(master->dma_rx);
3ecd37ed
MS
632 dma_release_channel(master->dma_rx);
633 master->dma_rx = NULL;
634 }
635}
636
29ad1a7a 637static void bcm2835_dma_init(struct spi_master *master, struct device *dev)
3ecd37ed
MS
638{
639 struct dma_slave_config slave_config;
640 const __be32 *addr;
641 dma_addr_t dma_reg_base;
642 int ret;
643
644 /* base address in dma-space */
645 addr = of_get_address(master->dev.of_node, 0, NULL, NULL);
646 if (!addr) {
647 dev_err(dev, "could not get DMA-register address - not using dma mode\n");
648 goto err;
649 }
650 dma_reg_base = be32_to_cpup(addr);
651
652 /* get tx/rx dma */
653 master->dma_tx = dma_request_slave_channel(dev, "tx");
654 if (!master->dma_tx) {
655 dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
656 goto err;
657 }
658 master->dma_rx = dma_request_slave_channel(dev, "rx");
659 if (!master->dma_rx) {
660 dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
661 goto err_release;
662 }
663
664 /* configure DMAs */
665 slave_config.direction = DMA_MEM_TO_DEV;
666 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
667 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
668
669 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
670 if (ret)
671 goto err_config;
672
673 slave_config.direction = DMA_DEV_TO_MEM;
674 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
675 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
676
677 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
678 if (ret)
679 goto err_config;
680
681 /* all went well, so set can_dma */
682 master->can_dma = bcm2835_spi_can_dma;
3ecd37ed
MS
683 /* need to do TX AND RX DMA, so we need dummy buffers */
684 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
685
686 return;
687
688err_config:
689 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
690 ret);
691err_release:
692 bcm2835_dma_release(master);
693err:
694 return;
695}
696
a750b124
MS
697static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
698 struct spi_device *spi,
699 struct spi_transfer *tfr,
9ac3f90d 700 u32 cs)
a750b124
MS
701{
702 struct bcm2835_spi *bs = spi_master_get_devdata(master);
703 unsigned long timeout;
704
705 /* enable HW block without interrupts */
706 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
707
708 /* fill in the fifo before timeout calculations
709 * if we are interrupted here, then the data is
710 * getting transferred by the HW while we are interrupted
711 */
2e0733bc 712 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
a750b124
MS
713
714 /* set the timeout */
715 timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES;
716
717 /* loop until finished the transfer */
718 while (bs->rx_len) {
719 /* fill in tx fifo with remaining data */
720 bcm2835_wr_fifo(bs);
721
722 /* read from fifo as much as possible */
723 bcm2835_rd_fifo(bs);
724
725 /* if there is still data pending to read
726 * then check the timeout
727 */
728 if (bs->rx_len && time_after(jiffies, timeout)) {
729 dev_dbg_ratelimited(&spi->dev,
730 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
731 jiffies - timeout,
732 bs->tx_len, bs->rx_len);
733 /* fall back to interrupt mode */
734 return bcm2835_spi_transfer_one_irq(master, spi,
2e0733bc 735 tfr, cs, false);
a750b124
MS
736 }
737 }
738
739 /* Transfer complete - reset SPI HW */
740 bcm2835_spi_reset_hw(master);
741 /* and return without waiting for completion */
742 return 0;
743}
744
e34ff011
MS
745static int bcm2835_spi_transfer_one(struct spi_master *master,
746 struct spi_device *spi,
747 struct spi_transfer *tfr)
f8043872 748{
e34ff011 749 struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872 750 unsigned long spi_hz, clk_hz, cdiv;
0122a518 751 unsigned long spi_used_hz;
e34ff011 752 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
f8043872 753
e34ff011 754 /* set clock */
f8043872
CB
755 spi_hz = tfr->speed_hz;
756 clk_hz = clk_get_rate(bs->clk);
757
758 if (spi_hz >= clk_hz / 2) {
759 cdiv = 2; /* clk_hz/2 is the fastest we can go */
760 } else if (spi_hz) {
210b4923
MS
761 /* CDIV must be a multiple of two */
762 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
763 cdiv += (cdiv % 2);
f8043872
CB
764
765 if (cdiv >= 65536)
766 cdiv = 0; /* 0 is the slowest we can go */
342f948a 767 } else {
f8043872 768 cdiv = 0; /* 0 is the slowest we can go */
342f948a 769 }
704f32d4 770 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
e34ff011 771 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
f8043872 772
acace73d 773 /* handle all the 3-wire mode */
6935224d
MS
774 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
775 cs |= BCM2835_SPI_CS_REN;
acace73d
MS
776 else
777 cs &= ~BCM2835_SPI_CS_REN;
f8043872 778
5c09e42f
LW
779 /*
780 * The driver always uses software-controlled GPIO Chip Select.
781 * Set the hardware-controlled native Chip Select to an invalid
782 * value to prevent it from interfering.
e34ff011 783 */
5c09e42f 784 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
f8043872 785
e34ff011 786 /* set transmit buffers and length */
f8043872
CB
787 bs->tx_buf = tfr->tx_buf;
788 bs->rx_buf = tfr->rx_buf;
e34ff011
MS
789 bs->tx_len = tfr->len;
790 bs->rx_len = tfr->len;
f8043872 791
7f1922eb
MS
792 /* Calculate the estimated time in us the transfer runs. Note that
793 * there is 1 idle clocks cycles after each byte getting transferred
794 * so we have 9 cycles/byte. This is used to find the number of Hz
795 * per byte per polling limit. E.g., we can transfer 1 byte in 30 us
796 * per 300,000 Hz of bus clock.
797 */
798#define HZ_PER_BYTE ((9 * 1000000) / BCM2835_SPI_POLLING_LIMIT_US)
799 /* run in polling mode for short transfers */
800 if (tfr->len < spi_used_hz / HZ_PER_BYTE)
9ac3f90d 801 return bcm2835_spi_transfer_one_poll(master, spi, tfr, cs);
f8043872 802
3ecd37ed
MS
803 /* run in dma mode if conditions are right */
804 if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr))
805 return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs);
806
807 /* run in interrupt-mode */
2e0733bc 808 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs, true);
f8043872
CB
809}
810
acace73d
MS
811static int bcm2835_spi_prepare_message(struct spi_master *master,
812 struct spi_message *msg)
813{
814 struct spi_device *spi = msg->spi;
815 struct bcm2835_spi *bs = spi_master_get_devdata(master);
816 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
8b7bd10e
MM
817 int ret;
818
819 /*
820 * DMA transfers are limited to 16 bit (0 to 65535 bytes) by the SPI HW
821 * due to DLEN. Split up transfers (32-bit FIFO aligned) if the limit is
822 * exceeded.
823 */
824 ret = spi_split_transfers_maxsize(master, msg, 65532,
825 GFP_KERNEL | GFP_DMA);
826 if (ret)
827 return ret;
acace73d
MS
828
829 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
830
831 if (spi->mode & SPI_CPOL)
832 cs |= BCM2835_SPI_CS_CPOL;
833 if (spi->mode & SPI_CPHA)
834 cs |= BCM2835_SPI_CS_CPHA;
835
836 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
837
838 return 0;
839}
840
e34ff011
MS
841static void bcm2835_spi_handle_err(struct spi_master *master,
842 struct spi_message *msg)
f8043872 843{
3ecd37ed
MS
844 struct bcm2835_spi *bs = spi_master_get_devdata(master);
845
846 /* if an error occurred and we have an active dma, then terminate */
e82b0b38 847 if (cmpxchg(&bs->dma_pending, true, false)) {
2527704d
LW
848 dmaengine_terminate_sync(master->dma_tx);
849 dmaengine_terminate_sync(master->dma_rx);
3bd7f658 850 bcm2835_spi_undo_prologue(bs);
3ecd37ed
MS
851 }
852 /* and reset */
e34ff011 853 bcm2835_spi_reset_hw(master);
f8043872
CB
854}
855
a30a555d
MS
856static int chip_match_name(struct gpio_chip *chip, void *data)
857{
858 return !strcmp(chip->label, data);
859}
860
e34ff011
MS
861static int bcm2835_spi_setup(struct spi_device *spi)
862{
a30a555d
MS
863 int err;
864 struct gpio_chip *chip;
e34ff011
MS
865 /*
866 * sanity checking the native-chipselects
867 */
868 if (spi->mode & SPI_NO_CS)
869 return 0;
870 if (gpio_is_valid(spi->cs_gpio))
871 return 0;
a30a555d
MS
872 if (spi->chip_select > 1) {
873 /* error in the case of native CS requested with CS > 1
874 * officially there is a CS2, but it is not documented
875 * which GPIO is connected with that...
876 */
877 dev_err(&spi->dev,
878 "setup: only two native chip-selects are supported\n");
879 return -EINVAL;
880 }
881 /* now translate native cs to GPIO */
882
883 /* get the gpio chip for the base */
884 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
885 if (!chip)
e34ff011
MS
886 return 0;
887
a30a555d
MS
888 /* and calculate the real CS */
889 spi->cs_gpio = chip->base + 8 - spi->chip_select;
890
891 /* and set up the "mode" and level */
892 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
893 spi->chip_select, spi->cs_gpio);
894
895 /* set up GPIO as output and pull to the correct level */
896 err = gpio_direction_output(spi->cs_gpio,
897 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
898 if (err) {
899 dev_err(&spi->dev,
900 "could not set CS%i gpio %i as output: %i",
901 spi->chip_select, spi->cs_gpio, err);
902 return err;
903 }
a30a555d
MS
904
905 return 0;
f8043872
CB
906}
907
908static int bcm2835_spi_probe(struct platform_device *pdev)
909{
910 struct spi_master *master;
911 struct bcm2835_spi *bs;
912 struct resource *res;
913 int err;
914
915 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
916 if (!master) {
917 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
918 return -ENOMEM;
919 }
920
921 platform_set_drvdata(pdev, master);
922
923 master->mode_bits = BCM2835_SPI_MODE_BITS;
c2b6a3a8 924 master->bits_per_word_mask = SPI_BPW_MASK(8);
f8043872 925 master->num_chipselect = 3;
e34ff011 926 master->setup = bcm2835_spi_setup;
e34ff011
MS
927 master->transfer_one = bcm2835_spi_transfer_one;
928 master->handle_err = bcm2835_spi_handle_err;
acace73d 929 master->prepare_message = bcm2835_spi_prepare_message;
f8043872
CB
930 master->dev.of_node = pdev->dev.of_node;
931
932 bs = spi_master_get_devdata(master);
933
f8043872 934 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2d6e75e8
LN
935 bs->regs = devm_ioremap_resource(&pdev->dev, res);
936 if (IS_ERR(bs->regs)) {
937 err = PTR_ERR(bs->regs);
f8043872
CB
938 goto out_master_put;
939 }
940
941 bs->clk = devm_clk_get(&pdev->dev, NULL);
942 if (IS_ERR(bs->clk)) {
943 err = PTR_ERR(bs->clk);
944 dev_err(&pdev->dev, "could not get clk: %d\n", err);
945 goto out_master_put;
946 }
947
ddf0e1c2 948 bs->irq = platform_get_irq(pdev, 0);
f8043872
CB
949 if (bs->irq <= 0) {
950 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
951 err = bs->irq ? bs->irq : -ENODEV;
952 goto out_master_put;
953 }
954
955 clk_prepare_enable(bs->clk);
956
ddf0e1c2
MS
957 bcm2835_dma_init(master, &pdev->dev);
958
959 /* initialise the hardware with the default polarities */
960 bcm2835_wr(bs, BCM2835_SPI_CS,
961 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
962
08bc0544 963 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
342f948a 964 dev_name(&pdev->dev), master);
f8043872
CB
965 if (err) {
966 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
967 goto out_clk_disable;
968 }
969
247263db 970 err = devm_spi_register_master(&pdev->dev, master);
f8043872
CB
971 if (err) {
972 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
08bc0544 973 goto out_clk_disable;
f8043872
CB
974 }
975
976 return 0;
977
f8043872
CB
978out_clk_disable:
979 clk_disable_unprepare(bs->clk);
980out_master_put:
981 spi_master_put(master);
982 return err;
983}
984
985static int bcm2835_spi_remove(struct platform_device *pdev)
986{
e0b35b89 987 struct spi_master *master = platform_get_drvdata(pdev);
f8043872
CB
988 struct bcm2835_spi *bs = spi_master_get_devdata(master);
989
f8043872
CB
990 /* Clear FIFOs, and disable the HW block */
991 bcm2835_wr(bs, BCM2835_SPI_CS,
992 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
993
994 clk_disable_unprepare(bs->clk);
f8043872 995
3ecd37ed
MS
996 bcm2835_dma_release(master);
997
f8043872
CB
998 return 0;
999}
1000
1001static const struct of_device_id bcm2835_spi_match[] = {
1002 { .compatible = "brcm,bcm2835-spi", },
1003 {}
1004};
1005MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
1006
1007static struct platform_driver bcm2835_spi_driver = {
1008 .driver = {
1009 .name = DRV_NAME,
f8043872
CB
1010 .of_match_table = bcm2835_spi_match,
1011 },
1012 .probe = bcm2835_spi_probe,
1013 .remove = bcm2835_spi_remove,
1014};
1015module_platform_driver(bcm2835_spi_driver);
1016
1017MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
1018MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
22bf6cd2 1019MODULE_LICENSE("GPL");