Commit | Line | Data |
---|---|---|
f8043872 CB |
1 | /* |
2 | * Driver for Broadcom BCM2835 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2012 Chris Boot | |
5 | * Copyright (C) 2013 Stephen Warren | |
e34ff011 | 6 | * Copyright (C) 2015 Martin Sperl |
f8043872 CB |
7 | * |
8 | * This driver is inspired by: | |
9 | * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> | |
10 | * spi-atmel.c, Copyright (C) 2006 Atmel Corporation | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
f8043872 CB |
21 | */ |
22 | ||
7e52be0d | 23 | #include <asm/page.h> |
f8043872 CB |
24 | #include <linux/clk.h> |
25 | #include <linux/completion.h> | |
26 | #include <linux/delay.h> | |
3ecd37ed MS |
27 | #include <linux/dma-mapping.h> |
28 | #include <linux/dmaengine.h> | |
f8043872 CB |
29 | #include <linux/err.h> |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/of.h> | |
3ecd37ed | 35 | #include <linux/of_address.h> |
f8043872 | 36 | #include <linux/of_device.h> |
3ecd37ed MS |
37 | #include <linux/of_gpio.h> |
38 | #include <linux/of_irq.h> | |
f8043872 CB |
39 | #include <linux/spi/spi.h> |
40 | ||
41 | /* SPI register offsets */ | |
42 | #define BCM2835_SPI_CS 0x00 | |
43 | #define BCM2835_SPI_FIFO 0x04 | |
44 | #define BCM2835_SPI_CLK 0x08 | |
45 | #define BCM2835_SPI_DLEN 0x0c | |
46 | #define BCM2835_SPI_LTOH 0x10 | |
47 | #define BCM2835_SPI_DC 0x14 | |
48 | ||
49 | /* Bitfields in CS */ | |
50 | #define BCM2835_SPI_CS_LEN_LONG 0x02000000 | |
51 | #define BCM2835_SPI_CS_DMA_LEN 0x01000000 | |
52 | #define BCM2835_SPI_CS_CSPOL2 0x00800000 | |
53 | #define BCM2835_SPI_CS_CSPOL1 0x00400000 | |
54 | #define BCM2835_SPI_CS_CSPOL0 0x00200000 | |
55 | #define BCM2835_SPI_CS_RXF 0x00100000 | |
56 | #define BCM2835_SPI_CS_RXR 0x00080000 | |
57 | #define BCM2835_SPI_CS_TXD 0x00040000 | |
58 | #define BCM2835_SPI_CS_RXD 0x00020000 | |
59 | #define BCM2835_SPI_CS_DONE 0x00010000 | |
60 | #define BCM2835_SPI_CS_LEN 0x00002000 | |
61 | #define BCM2835_SPI_CS_REN 0x00001000 | |
62 | #define BCM2835_SPI_CS_ADCS 0x00000800 | |
63 | #define BCM2835_SPI_CS_INTR 0x00000400 | |
64 | #define BCM2835_SPI_CS_INTD 0x00000200 | |
65 | #define BCM2835_SPI_CS_DMAEN 0x00000100 | |
66 | #define BCM2835_SPI_CS_TA 0x00000080 | |
67 | #define BCM2835_SPI_CS_CSPOL 0x00000040 | |
68 | #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 | |
69 | #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 | |
70 | #define BCM2835_SPI_CS_CPOL 0x00000008 | |
71 | #define BCM2835_SPI_CS_CPHA 0x00000004 | |
72 | #define BCM2835_SPI_CS_CS_10 0x00000002 | |
73 | #define BCM2835_SPI_CS_CS_01 0x00000001 | |
74 | ||
704f32d4 | 75 | #define BCM2835_SPI_POLLING_LIMIT_US 30 |
a750b124 | 76 | #define BCM2835_SPI_POLLING_JIFFIES 2 |
3ecd37ed | 77 | #define BCM2835_SPI_DMA_MIN_LENGTH 96 |
6935224d MS |
78 | #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
79 | | SPI_NO_CS | SPI_3WIRE) | |
f8043872 CB |
80 | |
81 | #define DRV_NAME "spi-bcm2835" | |
82 | ||
83 | struct bcm2835_spi { | |
84 | void __iomem *regs; | |
85 | struct clk *clk; | |
86 | int irq; | |
f8043872 CB |
87 | const u8 *tx_buf; |
88 | u8 *rx_buf; | |
e34ff011 MS |
89 | int tx_len; |
90 | int rx_len; | |
3ecd37ed | 91 | bool dma_pending; |
f8043872 CB |
92 | }; |
93 | ||
94 | static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) | |
95 | { | |
96 | return readl(bs->regs + reg); | |
97 | } | |
98 | ||
99 | static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) | |
100 | { | |
101 | writel(val, bs->regs + reg); | |
102 | } | |
103 | ||
4adf3129 | 104 | static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
105 | { |
106 | u8 byte; | |
107 | ||
e34ff011 MS |
108 | while ((bs->rx_len) && |
109 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { | |
f8043872 CB |
110 | byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); |
111 | if (bs->rx_buf) | |
112 | *bs->rx_buf++ = byte; | |
e34ff011 | 113 | bs->rx_len--; |
f8043872 CB |
114 | } |
115 | } | |
116 | ||
4adf3129 | 117 | static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
118 | { |
119 | u8 byte; | |
120 | ||
e34ff011 | 121 | while ((bs->tx_len) && |
4adf3129 | 122 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { |
f8043872 CB |
123 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; |
124 | bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); | |
e34ff011 | 125 | bs->tx_len--; |
f8043872 CB |
126 | } |
127 | } | |
128 | ||
e34ff011 MS |
129 | static void bcm2835_spi_reset_hw(struct spi_master *master) |
130 | { | |
131 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
132 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); | |
133 | ||
134 | /* Disable SPI interrupts and transfer */ | |
135 | cs &= ~(BCM2835_SPI_CS_INTR | | |
136 | BCM2835_SPI_CS_INTD | | |
3ecd37ed | 137 | BCM2835_SPI_CS_DMAEN | |
e34ff011 MS |
138 | BCM2835_SPI_CS_TA); |
139 | /* and reset RX/TX FIFOS */ | |
140 | cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; | |
141 | ||
142 | /* and reset the SPI_HW */ | |
143 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
3ecd37ed MS |
144 | /* as well as DLEN */ |
145 | bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); | |
e34ff011 MS |
146 | } |
147 | ||
f8043872 CB |
148 | static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) |
149 | { | |
150 | struct spi_master *master = dev_id; | |
151 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
f8043872 | 152 | |
4adf3129 MS |
153 | /* Read as many bytes as possible from FIFO */ |
154 | bcm2835_rd_fifo(bs); | |
e34ff011 MS |
155 | /* Write as many bytes as possible to FIFO */ |
156 | bcm2835_wr_fifo(bs); | |
157 | ||
56c17234 | 158 | if (!bs->rx_len) { |
e34ff011 MS |
159 | /* Transfer complete - reset SPI HW */ |
160 | bcm2835_spi_reset_hw(master); | |
161 | /* wake up the framework */ | |
162 | complete(&master->xfer_completion); | |
f8043872 CB |
163 | } |
164 | ||
4adf3129 | 165 | return IRQ_HANDLED; |
f8043872 CB |
166 | } |
167 | ||
704f32d4 MS |
168 | static int bcm2835_spi_transfer_one_irq(struct spi_master *master, |
169 | struct spi_device *spi, | |
170 | struct spi_transfer *tfr, | |
171 | u32 cs) | |
172 | { | |
173 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
174 | ||
704f32d4 | 175 | /* |
5c09e42f LW |
176 | * Enable HW block, but with interrupts still disabled. |
177 | * Otherwise the empty TX FIFO would immediately trigger an interrupt. | |
704f32d4 | 178 | */ |
5c09e42f LW |
179 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); |
180 | ||
181 | /* fill TX FIFO as much as possible */ | |
182 | bcm2835_wr_fifo(bs); | |
183 | ||
184 | /* enable interrupts */ | |
704f32d4 MS |
185 | cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; |
186 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
187 | ||
188 | /* signal that we need to wait for completion */ | |
189 | return 1; | |
190 | } | |
191 | ||
3ecd37ed MS |
192 | /* |
193 | * DMA support | |
194 | * | |
195 | * this implementation has currently a few issues in so far as it does | |
196 | * not work arrount limitations of the HW. | |
197 | * | |
198 | * the main one being that DMA transfers are limited to 16 bit | |
199 | * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN | |
200 | * | |
201 | * also we currently assume that the scatter-gather fragments are | |
202 | * all multiple of 4 (except the last) - otherwise we would need | |
203 | * to reset the FIFO before subsequent transfers... | |
204 | * this also means that tx/rx transfers sg's need to be of equal size! | |
205 | * | |
206 | * there may be a few more border-cases we may need to address as well | |
207 | * but unfortunately this would mean splitting up the scatter-gather | |
208 | * list making it slightly unpractical... | |
209 | */ | |
210 | static void bcm2835_spi_dma_done(void *data) | |
211 | { | |
212 | struct spi_master *master = data; | |
213 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
214 | ||
215 | /* reset fifo and HW */ | |
216 | bcm2835_spi_reset_hw(master); | |
217 | ||
218 | /* and terminate tx-dma as we do not have an irq for it | |
219 | * because when the rx dma will terminate and this callback | |
220 | * is called the tx-dma must have finished - can't get to this | |
221 | * situation otherwise... | |
222 | */ | |
e82b0b38 LW |
223 | if (cmpxchg(&bs->dma_pending, true, false)) { |
224 | dmaengine_terminate_all(master->dma_tx); | |
225 | } | |
3ecd37ed MS |
226 | |
227 | /* and mark as completed */; | |
228 | complete(&master->xfer_completion); | |
229 | } | |
230 | ||
231 | static int bcm2835_spi_prepare_sg(struct spi_master *master, | |
232 | struct spi_transfer *tfr, | |
233 | bool is_tx) | |
234 | { | |
235 | struct dma_chan *chan; | |
236 | struct scatterlist *sgl; | |
237 | unsigned int nents; | |
238 | enum dma_transfer_direction dir; | |
239 | unsigned long flags; | |
240 | ||
241 | struct dma_async_tx_descriptor *desc; | |
242 | dma_cookie_t cookie; | |
243 | ||
244 | if (is_tx) { | |
245 | dir = DMA_MEM_TO_DEV; | |
246 | chan = master->dma_tx; | |
247 | nents = tfr->tx_sg.nents; | |
248 | sgl = tfr->tx_sg.sgl; | |
249 | flags = 0 /* no tx interrupt */; | |
250 | ||
251 | } else { | |
252 | dir = DMA_DEV_TO_MEM; | |
253 | chan = master->dma_rx; | |
254 | nents = tfr->rx_sg.nents; | |
255 | sgl = tfr->rx_sg.sgl; | |
256 | flags = DMA_PREP_INTERRUPT; | |
257 | } | |
258 | /* prepare the channel */ | |
259 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
260 | if (!desc) | |
261 | return -EINVAL; | |
262 | ||
263 | /* set callback for rx */ | |
264 | if (!is_tx) { | |
265 | desc->callback = bcm2835_spi_dma_done; | |
266 | desc->callback_param = master; | |
267 | } | |
268 | ||
269 | /* submit it to DMA-engine */ | |
270 | cookie = dmaengine_submit(desc); | |
271 | ||
272 | return dma_submit_error(cookie); | |
273 | } | |
274 | ||
275 | static inline int bcm2835_check_sg_length(struct sg_table *sgt) | |
276 | { | |
277 | int i; | |
278 | struct scatterlist *sgl; | |
279 | ||
280 | /* check that the sg entries are word-sized (except for last) */ | |
281 | for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) { | |
282 | if (sg_dma_len(sgl) % 4) | |
283 | return -EFAULT; | |
284 | } | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
289 | static int bcm2835_spi_transfer_one_dma(struct spi_master *master, | |
290 | struct spi_device *spi, | |
291 | struct spi_transfer *tfr, | |
292 | u32 cs) | |
293 | { | |
294 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
295 | int ret; | |
296 | ||
297 | /* check that the scatter gather segments are all a multiple of 4 */ | |
298 | if (bcm2835_check_sg_length(&tfr->tx_sg) || | |
299 | bcm2835_check_sg_length(&tfr->rx_sg)) { | |
300 | dev_warn_once(&spi->dev, | |
301 | "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n"); | |
302 | return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); | |
303 | } | |
304 | ||
305 | /* setup tx-DMA */ | |
306 | ret = bcm2835_spi_prepare_sg(master, tfr, true); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | /* start TX early */ | |
311 | dma_async_issue_pending(master->dma_tx); | |
312 | ||
313 | /* mark as dma pending */ | |
314 | bs->dma_pending = 1; | |
315 | ||
316 | /* set the DMA length */ | |
317 | bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len); | |
318 | ||
319 | /* start the HW */ | |
320 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
321 | cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); | |
322 | ||
323 | /* setup rx-DMA late - to run transfers while | |
324 | * mapping of the rx buffers still takes place | |
325 | * this saves 10us or more. | |
326 | */ | |
327 | ret = bcm2835_spi_prepare_sg(master, tfr, false); | |
328 | if (ret) { | |
329 | /* need to reset on errors */ | |
330 | dmaengine_terminate_all(master->dma_tx); | |
dbc94411 | 331 | bs->dma_pending = false; |
3ecd37ed MS |
332 | bcm2835_spi_reset_hw(master); |
333 | return ret; | |
334 | } | |
335 | ||
336 | /* start rx dma late */ | |
337 | dma_async_issue_pending(master->dma_rx); | |
338 | ||
339 | /* wait for wakeup in framework */ | |
340 | return 1; | |
341 | } | |
342 | ||
343 | static bool bcm2835_spi_can_dma(struct spi_master *master, | |
344 | struct spi_device *spi, | |
345 | struct spi_transfer *tfr) | |
346 | { | |
3ecd37ed MS |
347 | /* we start DMA efforts only on bigger transfers */ |
348 | if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) | |
349 | return false; | |
350 | ||
351 | /* BCM2835_SPI_DLEN has defined a max transfer size as | |
352 | * 16 bit, so max is 65535 | |
353 | * we can revisit this by using an alternative transfer | |
354 | * method - ideally this would get done without any more | |
355 | * interaction... | |
356 | */ | |
357 | if (tfr->len > 65535) { | |
358 | dev_warn_once(&spi->dev, | |
359 | "transfer size of %d too big for dma-transfer\n", | |
360 | tfr->len); | |
361 | return false; | |
362 | } | |
363 | ||
364 | /* if we run rx/tx_buf with word aligned addresses then we are OK */ | |
7e52be0d MS |
365 | if ((((size_t)tfr->rx_buf & 3) == 0) && |
366 | (((size_t)tfr->tx_buf & 3) == 0)) | |
3ecd37ed MS |
367 | return true; |
368 | ||
369 | /* otherwise we only allow transfers within the same page | |
370 | * to avoid wasting time on dma_mapping when it is not practical | |
371 | */ | |
2a3fffd4 | 372 | if (((size_t)tfr->tx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { |
3ecd37ed MS |
373 | dev_warn_once(&spi->dev, |
374 | "Unaligned spi tx-transfer bridging page\n"); | |
375 | return false; | |
376 | } | |
2a3fffd4 | 377 | if (((size_t)tfr->rx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { |
3ecd37ed | 378 | dev_warn_once(&spi->dev, |
2a3fffd4 | 379 | "Unaligned spi rx-transfer bridging page\n"); |
3ecd37ed MS |
380 | return false; |
381 | } | |
382 | ||
383 | /* return OK */ | |
384 | return true; | |
385 | } | |
386 | ||
29ad1a7a | 387 | static void bcm2835_dma_release(struct spi_master *master) |
3ecd37ed MS |
388 | { |
389 | if (master->dma_tx) { | |
390 | dmaengine_terminate_all(master->dma_tx); | |
391 | dma_release_channel(master->dma_tx); | |
392 | master->dma_tx = NULL; | |
393 | } | |
394 | if (master->dma_rx) { | |
395 | dmaengine_terminate_all(master->dma_rx); | |
396 | dma_release_channel(master->dma_rx); | |
397 | master->dma_rx = NULL; | |
398 | } | |
399 | } | |
400 | ||
29ad1a7a | 401 | static void bcm2835_dma_init(struct spi_master *master, struct device *dev) |
3ecd37ed MS |
402 | { |
403 | struct dma_slave_config slave_config; | |
404 | const __be32 *addr; | |
405 | dma_addr_t dma_reg_base; | |
406 | int ret; | |
407 | ||
408 | /* base address in dma-space */ | |
409 | addr = of_get_address(master->dev.of_node, 0, NULL, NULL); | |
410 | if (!addr) { | |
411 | dev_err(dev, "could not get DMA-register address - not using dma mode\n"); | |
412 | goto err; | |
413 | } | |
414 | dma_reg_base = be32_to_cpup(addr); | |
415 | ||
416 | /* get tx/rx dma */ | |
417 | master->dma_tx = dma_request_slave_channel(dev, "tx"); | |
418 | if (!master->dma_tx) { | |
419 | dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); | |
420 | goto err; | |
421 | } | |
422 | master->dma_rx = dma_request_slave_channel(dev, "rx"); | |
423 | if (!master->dma_rx) { | |
424 | dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); | |
425 | goto err_release; | |
426 | } | |
427 | ||
428 | /* configure DMAs */ | |
429 | slave_config.direction = DMA_MEM_TO_DEV; | |
430 | slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); | |
431 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
432 | ||
433 | ret = dmaengine_slave_config(master->dma_tx, &slave_config); | |
434 | if (ret) | |
435 | goto err_config; | |
436 | ||
437 | slave_config.direction = DMA_DEV_TO_MEM; | |
438 | slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); | |
439 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
440 | ||
441 | ret = dmaengine_slave_config(master->dma_rx, &slave_config); | |
442 | if (ret) | |
443 | goto err_config; | |
444 | ||
445 | /* all went well, so set can_dma */ | |
446 | master->can_dma = bcm2835_spi_can_dma; | |
447 | master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ | |
448 | /* need to do TX AND RX DMA, so we need dummy buffers */ | |
449 | master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; | |
450 | ||
451 | return; | |
452 | ||
453 | err_config: | |
454 | dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", | |
455 | ret); | |
456 | err_release: | |
457 | bcm2835_dma_release(master); | |
458 | err: | |
459 | return; | |
460 | } | |
461 | ||
a750b124 MS |
462 | static int bcm2835_spi_transfer_one_poll(struct spi_master *master, |
463 | struct spi_device *spi, | |
464 | struct spi_transfer *tfr, | |
465 | u32 cs, | |
0122a518 | 466 | unsigned long long xfer_time_us) |
a750b124 MS |
467 | { |
468 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
469 | unsigned long timeout; | |
470 | ||
471 | /* enable HW block without interrupts */ | |
472 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); | |
473 | ||
474 | /* fill in the fifo before timeout calculations | |
475 | * if we are interrupted here, then the data is | |
476 | * getting transferred by the HW while we are interrupted | |
477 | */ | |
478 | bcm2835_wr_fifo(bs); | |
479 | ||
480 | /* set the timeout */ | |
481 | timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; | |
482 | ||
483 | /* loop until finished the transfer */ | |
484 | while (bs->rx_len) { | |
485 | /* fill in tx fifo with remaining data */ | |
486 | bcm2835_wr_fifo(bs); | |
487 | ||
488 | /* read from fifo as much as possible */ | |
489 | bcm2835_rd_fifo(bs); | |
490 | ||
491 | /* if there is still data pending to read | |
492 | * then check the timeout | |
493 | */ | |
494 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
495 | dev_dbg_ratelimited(&spi->dev, | |
496 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
497 | jiffies - timeout, | |
498 | bs->tx_len, bs->rx_len); | |
499 | /* fall back to interrupt mode */ | |
500 | return bcm2835_spi_transfer_one_irq(master, spi, | |
501 | tfr, cs); | |
502 | } | |
503 | } | |
504 | ||
505 | /* Transfer complete - reset SPI HW */ | |
506 | bcm2835_spi_reset_hw(master); | |
507 | /* and return without waiting for completion */ | |
508 | return 0; | |
509 | } | |
510 | ||
e34ff011 MS |
511 | static int bcm2835_spi_transfer_one(struct spi_master *master, |
512 | struct spi_device *spi, | |
513 | struct spi_transfer *tfr) | |
f8043872 | 514 | { |
e34ff011 | 515 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
f8043872 | 516 | unsigned long spi_hz, clk_hz, cdiv; |
0122a518 MS |
517 | unsigned long spi_used_hz; |
518 | unsigned long long xfer_time_us; | |
e34ff011 | 519 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
f8043872 | 520 | |
e34ff011 | 521 | /* set clock */ |
f8043872 CB |
522 | spi_hz = tfr->speed_hz; |
523 | clk_hz = clk_get_rate(bs->clk); | |
524 | ||
525 | if (spi_hz >= clk_hz / 2) { | |
526 | cdiv = 2; /* clk_hz/2 is the fastest we can go */ | |
527 | } else if (spi_hz) { | |
210b4923 MS |
528 | /* CDIV must be a multiple of two */ |
529 | cdiv = DIV_ROUND_UP(clk_hz, spi_hz); | |
530 | cdiv += (cdiv % 2); | |
f8043872 CB |
531 | |
532 | if (cdiv >= 65536) | |
533 | cdiv = 0; /* 0 is the slowest we can go */ | |
342f948a | 534 | } else { |
f8043872 | 535 | cdiv = 0; /* 0 is the slowest we can go */ |
342f948a | 536 | } |
704f32d4 | 537 | spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); |
e34ff011 | 538 | bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); |
f8043872 | 539 | |
acace73d | 540 | /* handle all the 3-wire mode */ |
6935224d MS |
541 | if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf)) |
542 | cs |= BCM2835_SPI_CS_REN; | |
acace73d MS |
543 | else |
544 | cs &= ~BCM2835_SPI_CS_REN; | |
f8043872 | 545 | |
5c09e42f LW |
546 | /* |
547 | * The driver always uses software-controlled GPIO Chip Select. | |
548 | * Set the hardware-controlled native Chip Select to an invalid | |
549 | * value to prevent it from interfering. | |
e34ff011 | 550 | */ |
5c09e42f | 551 | cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; |
f8043872 | 552 | |
e34ff011 | 553 | /* set transmit buffers and length */ |
f8043872 CB |
554 | bs->tx_buf = tfr->tx_buf; |
555 | bs->rx_buf = tfr->rx_buf; | |
e34ff011 MS |
556 | bs->tx_len = tfr->len; |
557 | bs->rx_len = tfr->len; | |
f8043872 | 558 | |
704f32d4 | 559 | /* calculate the estimated time in us the transfer runs */ |
0122a518 | 560 | xfer_time_us = (unsigned long long)tfr->len |
704f32d4 | 561 | * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ |
0122a518 MS |
562 | * 1000000; |
563 | do_div(xfer_time_us, spi_used_hz); | |
e3a2be30 | 564 | |
704f32d4 MS |
565 | /* for short requests run polling*/ |
566 | if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) | |
567 | return bcm2835_spi_transfer_one_poll(master, spi, tfr, | |
568 | cs, xfer_time_us); | |
f8043872 | 569 | |
3ecd37ed MS |
570 | /* run in dma mode if conditions are right */ |
571 | if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) | |
572 | return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); | |
573 | ||
574 | /* run in interrupt-mode */ | |
704f32d4 | 575 | return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); |
f8043872 CB |
576 | } |
577 | ||
acace73d MS |
578 | static int bcm2835_spi_prepare_message(struct spi_master *master, |
579 | struct spi_message *msg) | |
580 | { | |
581 | struct spi_device *spi = msg->spi; | |
582 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
583 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); | |
584 | ||
585 | cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); | |
586 | ||
587 | if (spi->mode & SPI_CPOL) | |
588 | cs |= BCM2835_SPI_CS_CPOL; | |
589 | if (spi->mode & SPI_CPHA) | |
590 | cs |= BCM2835_SPI_CS_CPHA; | |
591 | ||
592 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
e34ff011 MS |
597 | static void bcm2835_spi_handle_err(struct spi_master *master, |
598 | struct spi_message *msg) | |
f8043872 | 599 | { |
3ecd37ed MS |
600 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
601 | ||
602 | /* if an error occurred and we have an active dma, then terminate */ | |
e82b0b38 | 603 | if (cmpxchg(&bs->dma_pending, true, false)) { |
3ecd37ed MS |
604 | dmaengine_terminate_all(master->dma_tx); |
605 | dmaengine_terminate_all(master->dma_rx); | |
3ecd37ed MS |
606 | } |
607 | /* and reset */ | |
e34ff011 | 608 | bcm2835_spi_reset_hw(master); |
f8043872 CB |
609 | } |
610 | ||
a30a555d MS |
611 | static int chip_match_name(struct gpio_chip *chip, void *data) |
612 | { | |
613 | return !strcmp(chip->label, data); | |
614 | } | |
615 | ||
e34ff011 MS |
616 | static int bcm2835_spi_setup(struct spi_device *spi) |
617 | { | |
a30a555d MS |
618 | int err; |
619 | struct gpio_chip *chip; | |
e34ff011 MS |
620 | /* |
621 | * sanity checking the native-chipselects | |
622 | */ | |
623 | if (spi->mode & SPI_NO_CS) | |
624 | return 0; | |
625 | if (gpio_is_valid(spi->cs_gpio)) | |
626 | return 0; | |
a30a555d MS |
627 | if (spi->chip_select > 1) { |
628 | /* error in the case of native CS requested with CS > 1 | |
629 | * officially there is a CS2, but it is not documented | |
630 | * which GPIO is connected with that... | |
631 | */ | |
632 | dev_err(&spi->dev, | |
633 | "setup: only two native chip-selects are supported\n"); | |
634 | return -EINVAL; | |
635 | } | |
636 | /* now translate native cs to GPIO */ | |
637 | ||
638 | /* get the gpio chip for the base */ | |
639 | chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); | |
640 | if (!chip) | |
e34ff011 MS |
641 | return 0; |
642 | ||
a30a555d MS |
643 | /* and calculate the real CS */ |
644 | spi->cs_gpio = chip->base + 8 - spi->chip_select; | |
645 | ||
646 | /* and set up the "mode" and level */ | |
647 | dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", | |
648 | spi->chip_select, spi->cs_gpio); | |
649 | ||
650 | /* set up GPIO as output and pull to the correct level */ | |
651 | err = gpio_direction_output(spi->cs_gpio, | |
652 | (spi->mode & SPI_CS_HIGH) ? 0 : 1); | |
653 | if (err) { | |
654 | dev_err(&spi->dev, | |
655 | "could not set CS%i gpio %i as output: %i", | |
656 | spi->chip_select, spi->cs_gpio, err); | |
657 | return err; | |
658 | } | |
a30a555d MS |
659 | |
660 | return 0; | |
f8043872 CB |
661 | } |
662 | ||
663 | static int bcm2835_spi_probe(struct platform_device *pdev) | |
664 | { | |
665 | struct spi_master *master; | |
666 | struct bcm2835_spi *bs; | |
667 | struct resource *res; | |
668 | int err; | |
669 | ||
670 | master = spi_alloc_master(&pdev->dev, sizeof(*bs)); | |
671 | if (!master) { | |
672 | dev_err(&pdev->dev, "spi_alloc_master() failed\n"); | |
673 | return -ENOMEM; | |
674 | } | |
675 | ||
676 | platform_set_drvdata(pdev, master); | |
677 | ||
678 | master->mode_bits = BCM2835_SPI_MODE_BITS; | |
c2b6a3a8 | 679 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
f8043872 | 680 | master->num_chipselect = 3; |
e34ff011 | 681 | master->setup = bcm2835_spi_setup; |
e34ff011 MS |
682 | master->transfer_one = bcm2835_spi_transfer_one; |
683 | master->handle_err = bcm2835_spi_handle_err; | |
acace73d | 684 | master->prepare_message = bcm2835_spi_prepare_message; |
f8043872 CB |
685 | master->dev.of_node = pdev->dev.of_node; |
686 | ||
687 | bs = spi_master_get_devdata(master); | |
688 | ||
f8043872 | 689 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2d6e75e8 LN |
690 | bs->regs = devm_ioremap_resource(&pdev->dev, res); |
691 | if (IS_ERR(bs->regs)) { | |
692 | err = PTR_ERR(bs->regs); | |
f8043872 CB |
693 | goto out_master_put; |
694 | } | |
695 | ||
696 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
697 | if (IS_ERR(bs->clk)) { | |
698 | err = PTR_ERR(bs->clk); | |
699 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
700 | goto out_master_put; | |
701 | } | |
702 | ||
ddf0e1c2 | 703 | bs->irq = platform_get_irq(pdev, 0); |
f8043872 CB |
704 | if (bs->irq <= 0) { |
705 | dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); | |
706 | err = bs->irq ? bs->irq : -ENODEV; | |
707 | goto out_master_put; | |
708 | } | |
709 | ||
710 | clk_prepare_enable(bs->clk); | |
711 | ||
ddf0e1c2 MS |
712 | bcm2835_dma_init(master, &pdev->dev); |
713 | ||
714 | /* initialise the hardware with the default polarities */ | |
715 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
716 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
717 | ||
08bc0544 | 718 | err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, |
342f948a | 719 | dev_name(&pdev->dev), master); |
f8043872 CB |
720 | if (err) { |
721 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
722 | goto out_clk_disable; | |
723 | } | |
724 | ||
247263db | 725 | err = devm_spi_register_master(&pdev->dev, master); |
f8043872 CB |
726 | if (err) { |
727 | dev_err(&pdev->dev, "could not register SPI master: %d\n", err); | |
08bc0544 | 728 | goto out_clk_disable; |
f8043872 CB |
729 | } |
730 | ||
731 | return 0; | |
732 | ||
f8043872 CB |
733 | out_clk_disable: |
734 | clk_disable_unprepare(bs->clk); | |
735 | out_master_put: | |
736 | spi_master_put(master); | |
737 | return err; | |
738 | } | |
739 | ||
740 | static int bcm2835_spi_remove(struct platform_device *pdev) | |
741 | { | |
e0b35b89 | 742 | struct spi_master *master = platform_get_drvdata(pdev); |
f8043872 CB |
743 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
744 | ||
f8043872 CB |
745 | /* Clear FIFOs, and disable the HW block */ |
746 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
747 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
748 | ||
749 | clk_disable_unprepare(bs->clk); | |
f8043872 | 750 | |
3ecd37ed MS |
751 | bcm2835_dma_release(master); |
752 | ||
f8043872 CB |
753 | return 0; |
754 | } | |
755 | ||
756 | static const struct of_device_id bcm2835_spi_match[] = { | |
757 | { .compatible = "brcm,bcm2835-spi", }, | |
758 | {} | |
759 | }; | |
760 | MODULE_DEVICE_TABLE(of, bcm2835_spi_match); | |
761 | ||
762 | static struct platform_driver bcm2835_spi_driver = { | |
763 | .driver = { | |
764 | .name = DRV_NAME, | |
f8043872 CB |
765 | .of_match_table = bcm2835_spi_match, |
766 | }, | |
767 | .probe = bcm2835_spi_probe, | |
768 | .remove = bcm2835_spi_remove, | |
769 | }; | |
770 | module_platform_driver(bcm2835_spi_driver); | |
771 | ||
772 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); | |
773 | MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); | |
22bf6cd2 | 774 | MODULE_LICENSE("GPL"); |