Commit | Line | Data |
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f8043872 CB |
1 | /* |
2 | * Driver for Broadcom BCM2835 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2012 Chris Boot | |
5 | * Copyright (C) 2013 Stephen Warren | |
e34ff011 | 6 | * Copyright (C) 2015 Martin Sperl |
f8043872 CB |
7 | * |
8 | * This driver is inspired by: | |
9 | * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> | |
10 | * spi-atmel.c, Copyright (C) 2006 Atmel Corporation | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
f8043872 CB |
21 | */ |
22 | ||
23 | #include <linux/clk.h> | |
24 | #include <linux/completion.h> | |
25 | #include <linux/delay.h> | |
3ecd37ed MS |
26 | #include <linux/dma-mapping.h> |
27 | #include <linux/dmaengine.h> | |
f8043872 CB |
28 | #include <linux/err.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/of.h> | |
3ecd37ed | 34 | #include <linux/of_address.h> |
f8043872 | 35 | #include <linux/of_device.h> |
3ecd37ed MS |
36 | #include <linux/of_gpio.h> |
37 | #include <linux/of_irq.h> | |
f8043872 CB |
38 | #include <linux/spi/spi.h> |
39 | ||
40 | /* SPI register offsets */ | |
41 | #define BCM2835_SPI_CS 0x00 | |
42 | #define BCM2835_SPI_FIFO 0x04 | |
43 | #define BCM2835_SPI_CLK 0x08 | |
44 | #define BCM2835_SPI_DLEN 0x0c | |
45 | #define BCM2835_SPI_LTOH 0x10 | |
46 | #define BCM2835_SPI_DC 0x14 | |
47 | ||
48 | /* Bitfields in CS */ | |
49 | #define BCM2835_SPI_CS_LEN_LONG 0x02000000 | |
50 | #define BCM2835_SPI_CS_DMA_LEN 0x01000000 | |
51 | #define BCM2835_SPI_CS_CSPOL2 0x00800000 | |
52 | #define BCM2835_SPI_CS_CSPOL1 0x00400000 | |
53 | #define BCM2835_SPI_CS_CSPOL0 0x00200000 | |
54 | #define BCM2835_SPI_CS_RXF 0x00100000 | |
55 | #define BCM2835_SPI_CS_RXR 0x00080000 | |
56 | #define BCM2835_SPI_CS_TXD 0x00040000 | |
57 | #define BCM2835_SPI_CS_RXD 0x00020000 | |
58 | #define BCM2835_SPI_CS_DONE 0x00010000 | |
59 | #define BCM2835_SPI_CS_LEN 0x00002000 | |
60 | #define BCM2835_SPI_CS_REN 0x00001000 | |
61 | #define BCM2835_SPI_CS_ADCS 0x00000800 | |
62 | #define BCM2835_SPI_CS_INTR 0x00000400 | |
63 | #define BCM2835_SPI_CS_INTD 0x00000200 | |
64 | #define BCM2835_SPI_CS_DMAEN 0x00000100 | |
65 | #define BCM2835_SPI_CS_TA 0x00000080 | |
66 | #define BCM2835_SPI_CS_CSPOL 0x00000040 | |
67 | #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 | |
68 | #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 | |
69 | #define BCM2835_SPI_CS_CPOL 0x00000008 | |
70 | #define BCM2835_SPI_CS_CPHA 0x00000004 | |
71 | #define BCM2835_SPI_CS_CS_10 0x00000002 | |
72 | #define BCM2835_SPI_CS_CS_01 0x00000001 | |
73 | ||
2e0733bc LW |
74 | #define BCM2835_SPI_FIFO_SIZE 64 |
75 | #define BCM2835_SPI_FIFO_SIZE_3_4 48 | |
704f32d4 | 76 | #define BCM2835_SPI_POLLING_LIMIT_US 30 |
a750b124 | 77 | #define BCM2835_SPI_POLLING_JIFFIES 2 |
3ecd37ed | 78 | #define BCM2835_SPI_DMA_MIN_LENGTH 96 |
6935224d MS |
79 | #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
80 | | SPI_NO_CS | SPI_3WIRE) | |
f8043872 CB |
81 | |
82 | #define DRV_NAME "spi-bcm2835" | |
83 | ||
acf0f856 LW |
84 | /** |
85 | * struct bcm2835_spi - BCM2835 SPI controller | |
86 | * @regs: base address of register map | |
87 | * @clk: core clock, divided to calculate serial clock | |
88 | * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full | |
3bd7f658 | 89 | * @tfr: SPI transfer currently processed |
acf0f856 LW |
90 | * @tx_buf: pointer whence next transmitted byte is read |
91 | * @rx_buf: pointer where next received byte is written | |
92 | * @tx_len: remaining bytes to transmit | |
93 | * @rx_len: remaining bytes to receive | |
3bd7f658 LW |
94 | * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's |
95 | * length is not a multiple of 4 (to overcome hardware limitation) | |
96 | * @rx_prologue: bytes received without DMA if first RX sglist entry's | |
97 | * length is not a multiple of 4 (to overcome hardware limitation) | |
98 | * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry | |
acf0f856 LW |
99 | * @dma_pending: whether a DMA transfer is in progress |
100 | */ | |
f8043872 CB |
101 | struct bcm2835_spi { |
102 | void __iomem *regs; | |
103 | struct clk *clk; | |
104 | int irq; | |
3bd7f658 | 105 | struct spi_transfer *tfr; |
f8043872 CB |
106 | const u8 *tx_buf; |
107 | u8 *rx_buf; | |
e34ff011 MS |
108 | int tx_len; |
109 | int rx_len; | |
3bd7f658 LW |
110 | int tx_prologue; |
111 | int rx_prologue; | |
b31a9299 | 112 | unsigned int tx_spillover; |
29bdedfd | 113 | unsigned int dma_pending; |
f8043872 CB |
114 | }; |
115 | ||
116 | static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) | |
117 | { | |
118 | return readl(bs->regs + reg); | |
119 | } | |
120 | ||
121 | static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) | |
122 | { | |
123 | writel(val, bs->regs + reg); | |
124 | } | |
125 | ||
4adf3129 | 126 | static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
127 | { |
128 | u8 byte; | |
129 | ||
e34ff011 MS |
130 | while ((bs->rx_len) && |
131 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { | |
f8043872 CB |
132 | byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); |
133 | if (bs->rx_buf) | |
134 | *bs->rx_buf++ = byte; | |
e34ff011 | 135 | bs->rx_len--; |
f8043872 CB |
136 | } |
137 | } | |
138 | ||
4adf3129 | 139 | static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
140 | { |
141 | u8 byte; | |
142 | ||
e34ff011 | 143 | while ((bs->tx_len) && |
4adf3129 | 144 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { |
f8043872 CB |
145 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; |
146 | bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); | |
e34ff011 | 147 | bs->tx_len--; |
f8043872 CB |
148 | } |
149 | } | |
150 | ||
3bd7f658 LW |
151 | /** |
152 | * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO | |
153 | * @bs: BCM2835 SPI controller | |
154 | * @count: bytes to read from RX FIFO | |
155 | * | |
156 | * The caller must ensure that @bs->rx_len is greater than or equal to @count, | |
157 | * that the RX FIFO contains at least @count bytes and that the DMA Enable flag | |
158 | * in the CS register is set (such that a read from the FIFO register receives | |
b31a9299 | 159 | * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL. |
3bd7f658 LW |
160 | */ |
161 | static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count) | |
162 | { | |
163 | u32 val; | |
b31a9299 | 164 | int len; |
3bd7f658 LW |
165 | |
166 | bs->rx_len -= count; | |
167 | ||
168 | while (count > 0) { | |
169 | val = bcm2835_rd(bs, BCM2835_SPI_FIFO); | |
b31a9299 LW |
170 | len = min(count, 4); |
171 | memcpy(bs->rx_buf, &val, len); | |
172 | bs->rx_buf += len; | |
3bd7f658 LW |
173 | count -= 4; |
174 | } | |
175 | } | |
176 | ||
177 | /** | |
178 | * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO | |
179 | * @bs: BCM2835 SPI controller | |
180 | * @count: bytes to write to TX FIFO | |
181 | * | |
182 | * The caller must ensure that @bs->tx_len is greater than or equal to @count, | |
183 | * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag | |
184 | * in the CS register is set (such that a write to the FIFO register transmits | |
185 | * 32-bit instead of just 8-bit). | |
186 | */ | |
187 | static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count) | |
188 | { | |
189 | u32 val; | |
b31a9299 | 190 | int len; |
3bd7f658 LW |
191 | |
192 | bs->tx_len -= count; | |
193 | ||
194 | while (count > 0) { | |
195 | if (bs->tx_buf) { | |
b31a9299 | 196 | len = min(count, 4); |
3bd7f658 LW |
197 | memcpy(&val, bs->tx_buf, len); |
198 | bs->tx_buf += len; | |
199 | } else { | |
200 | val = 0; | |
201 | } | |
202 | bcm2835_wr(bs, BCM2835_SPI_FIFO, val); | |
203 | count -= 4; | |
204 | } | |
205 | } | |
206 | ||
207 | /** | |
208 | * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty | |
209 | * @bs: BCM2835 SPI controller | |
b31a9299 LW |
210 | * |
211 | * The caller must ensure that the RX FIFO can accommodate as many bytes | |
212 | * as have been written to the TX FIFO: Transmission is halted once the | |
213 | * RX FIFO is full, causing this function to spin forever. | |
3bd7f658 LW |
214 | */ |
215 | static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs) | |
216 | { | |
217 | while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE)) | |
218 | cpu_relax(); | |
219 | } | |
220 | ||
2e0733bc LW |
221 | /** |
222 | * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO | |
223 | * @bs: BCM2835 SPI controller | |
224 | * @count: bytes available for reading in RX FIFO | |
225 | */ | |
226 | static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count) | |
227 | { | |
228 | u8 val; | |
229 | ||
230 | count = min(count, bs->rx_len); | |
231 | bs->rx_len -= count; | |
232 | ||
233 | while (count) { | |
234 | val = bcm2835_rd(bs, BCM2835_SPI_FIFO); | |
235 | if (bs->rx_buf) | |
236 | *bs->rx_buf++ = val; | |
237 | count--; | |
238 | } | |
239 | } | |
240 | ||
241 | /** | |
242 | * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO | |
243 | * @bs: BCM2835 SPI controller | |
244 | * @count: bytes available for writing in TX FIFO | |
245 | */ | |
246 | static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count) | |
247 | { | |
248 | u8 val; | |
249 | ||
250 | count = min(count, bs->tx_len); | |
251 | bs->tx_len -= count; | |
252 | ||
253 | while (count) { | |
254 | val = bs->tx_buf ? *bs->tx_buf++ : 0; | |
255 | bcm2835_wr(bs, BCM2835_SPI_FIFO, val); | |
256 | count--; | |
257 | } | |
258 | } | |
259 | ||
e34ff011 MS |
260 | static void bcm2835_spi_reset_hw(struct spi_master *master) |
261 | { | |
262 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
263 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); | |
264 | ||
265 | /* Disable SPI interrupts and transfer */ | |
266 | cs &= ~(BCM2835_SPI_CS_INTR | | |
267 | BCM2835_SPI_CS_INTD | | |
3ecd37ed | 268 | BCM2835_SPI_CS_DMAEN | |
e34ff011 MS |
269 | BCM2835_SPI_CS_TA); |
270 | /* and reset RX/TX FIFOS */ | |
271 | cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; | |
272 | ||
273 | /* and reset the SPI_HW */ | |
274 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
3ecd37ed MS |
275 | /* as well as DLEN */ |
276 | bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); | |
e34ff011 MS |
277 | } |
278 | ||
f8043872 CB |
279 | static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) |
280 | { | |
281 | struct spi_master *master = dev_id; | |
282 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
2e0733bc LW |
283 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
284 | ||
285 | /* | |
286 | * An interrupt is signaled either if DONE is set (TX FIFO empty) | |
287 | * or if RXR is set (RX FIFO >= ¾ full). | |
288 | */ | |
289 | if (cs & BCM2835_SPI_CS_RXF) | |
290 | bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
291 | else if (cs & BCM2835_SPI_CS_RXR) | |
292 | bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4); | |
293 | ||
294 | if (bs->tx_len && cs & BCM2835_SPI_CS_DONE) | |
295 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
f8043872 | 296 | |
4adf3129 MS |
297 | /* Read as many bytes as possible from FIFO */ |
298 | bcm2835_rd_fifo(bs); | |
e34ff011 MS |
299 | /* Write as many bytes as possible to FIFO */ |
300 | bcm2835_wr_fifo(bs); | |
301 | ||
56c17234 | 302 | if (!bs->rx_len) { |
e34ff011 MS |
303 | /* Transfer complete - reset SPI HW */ |
304 | bcm2835_spi_reset_hw(master); | |
305 | /* wake up the framework */ | |
306 | complete(&master->xfer_completion); | |
f8043872 CB |
307 | } |
308 | ||
4adf3129 | 309 | return IRQ_HANDLED; |
f8043872 CB |
310 | } |
311 | ||
704f32d4 MS |
312 | static int bcm2835_spi_transfer_one_irq(struct spi_master *master, |
313 | struct spi_device *spi, | |
314 | struct spi_transfer *tfr, | |
2e0733bc | 315 | u32 cs, bool fifo_empty) |
704f32d4 MS |
316 | { |
317 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
318 | ||
704f32d4 | 319 | /* |
5c09e42f LW |
320 | * Enable HW block, but with interrupts still disabled. |
321 | * Otherwise the empty TX FIFO would immediately trigger an interrupt. | |
704f32d4 | 322 | */ |
5c09e42f LW |
323 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); |
324 | ||
325 | /* fill TX FIFO as much as possible */ | |
2e0733bc LW |
326 | if (fifo_empty) |
327 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
5c09e42f LW |
328 | bcm2835_wr_fifo(bs); |
329 | ||
330 | /* enable interrupts */ | |
704f32d4 MS |
331 | cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; |
332 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
333 | ||
334 | /* signal that we need to wait for completion */ | |
335 | return 1; | |
336 | } | |
337 | ||
3ecd37ed MS |
338 | /* |
339 | * DMA support | |
340 | * | |
341 | * this implementation has currently a few issues in so far as it does | |
342 | * not work arrount limitations of the HW. | |
343 | * | |
344 | * the main one being that DMA transfers are limited to 16 bit | |
345 | * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN | |
346 | * | |
3ecd37ed MS |
347 | * there may be a few more border-cases we may need to address as well |
348 | * but unfortunately this would mean splitting up the scatter-gather | |
349 | * list making it slightly unpractical... | |
350 | */ | |
3bd7f658 LW |
351 | |
352 | /** | |
353 | * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA | |
354 | * @master: SPI master | |
355 | * @tfr: SPI transfer | |
356 | * @bs: BCM2835 SPI controller | |
357 | * @cs: CS register | |
358 | * | |
359 | * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks. | |
360 | * Only the final write access is permitted to transmit less than 4 bytes, the | |
361 | * SPI controller deduces its intended size from the DLEN register. | |
362 | * | |
363 | * If a TX or RX sglist contains multiple entries, one per page, and the first | |
364 | * entry starts in the middle of a page, that first entry's length may not be | |
365 | * a multiple of 4. Subsequent entries are fine because they span an entire | |
366 | * page, hence do have a length that's a multiple of 4. | |
367 | * | |
368 | * This cannot happen with kmalloc'ed buffers (which is what most clients use) | |
369 | * because they are contiguous in physical memory and therefore not split on | |
370 | * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed | |
371 | * buffers. | |
372 | * | |
373 | * The DMA engine is incapable of combining sglist entries into a continuous | |
374 | * stream of 4 byte chunks, it treats every entry separately: A TX entry is | |
375 | * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX | |
376 | * entry is rounded up by throwing away received bytes. | |
377 | * | |
378 | * Overcome this limitation by transferring the first few bytes without DMA: | |
379 | * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42, | |
380 | * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO. | |
381 | * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with | |
382 | * the rest of the first RX sglist entry it makes up a multiple of 4 bytes. | |
383 | * | |
384 | * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1, | |
385 | * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO. | |
386 | * Caution, the additional 4 bytes spill over to the second TX sglist entry | |
387 | * if the length of the first is *exactly* 1. | |
388 | * | |
389 | * At most 6 bytes are written and at most 3 bytes read. Do we know the | |
390 | * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH. | |
391 | * | |
392 | * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width | |
393 | * by the DMA engine. Toggling the DMA Enable flag in the CS register switches | |
394 | * the width but also garbles the FIFO's contents. The prologue must therefore | |
395 | * be transmitted in 32-bit width to ensure that the following DMA transfer can | |
396 | * pick up the residue in the RX FIFO in ungarbled form. | |
397 | */ | |
398 | static void bcm2835_spi_transfer_prologue(struct spi_master *master, | |
399 | struct spi_transfer *tfr, | |
400 | struct bcm2835_spi *bs, | |
401 | u32 cs) | |
402 | { | |
403 | int tx_remaining; | |
404 | ||
405 | bs->tfr = tfr; | |
406 | bs->tx_prologue = 0; | |
407 | bs->rx_prologue = 0; | |
408 | bs->tx_spillover = false; | |
409 | ||
410 | if (!sg_is_last(&tfr->tx_sg.sgl[0])) | |
411 | bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3; | |
412 | ||
413 | if (!sg_is_last(&tfr->rx_sg.sgl[0])) { | |
414 | bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3; | |
415 | ||
416 | if (bs->rx_prologue > bs->tx_prologue) { | |
417 | if (sg_is_last(&tfr->tx_sg.sgl[0])) { | |
418 | bs->tx_prologue = bs->rx_prologue; | |
419 | } else { | |
420 | bs->tx_prologue += 4; | |
421 | bs->tx_spillover = | |
422 | !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3); | |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */ | |
428 | if (!bs->tx_prologue) | |
429 | return; | |
430 | ||
431 | /* Write and read RX prologue. Adjust first entry in RX sglist. */ | |
432 | if (bs->rx_prologue) { | |
433 | bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue); | |
434 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA | |
435 | | BCM2835_SPI_CS_DMAEN); | |
436 | bcm2835_wr_fifo_count(bs, bs->rx_prologue); | |
437 | bcm2835_wait_tx_fifo_empty(bs); | |
438 | bcm2835_rd_fifo_count(bs, bs->rx_prologue); | |
439 | bcm2835_spi_reset_hw(master); | |
440 | ||
b31a9299 LW |
441 | dma_sync_single_for_device(master->dma_rx->device->dev, |
442 | sg_dma_address(&tfr->rx_sg.sgl[0]), | |
443 | bs->rx_prologue, DMA_FROM_DEVICE); | |
3bd7f658 | 444 | |
b31a9299 LW |
445 | sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; |
446 | sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; | |
3bd7f658 LW |
447 | } |
448 | ||
449 | /* | |
450 | * Write remaining TX prologue. Adjust first entry in TX sglist. | |
451 | * Also adjust second entry if prologue spills over to it. | |
452 | */ | |
453 | tx_remaining = bs->tx_prologue - bs->rx_prologue; | |
454 | if (tx_remaining) { | |
455 | bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining); | |
456 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA | |
457 | | BCM2835_SPI_CS_DMAEN); | |
458 | bcm2835_wr_fifo_count(bs, tx_remaining); | |
459 | bcm2835_wait_tx_fifo_empty(bs); | |
460 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX); | |
461 | } | |
462 | ||
463 | if (likely(!bs->tx_spillover)) { | |
b31a9299 LW |
464 | sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; |
465 | sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; | |
3bd7f658 | 466 | } else { |
b31a9299 LW |
467 | sg_dma_len(&tfr->tx_sg.sgl[0]) = 0; |
468 | sg_dma_address(&tfr->tx_sg.sgl[1]) += 4; | |
469 | sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4; | |
3bd7f658 LW |
470 | } |
471 | } | |
472 | ||
473 | /** | |
474 | * bcm2835_spi_undo_prologue() - reconstruct original sglist state | |
475 | * @bs: BCM2835 SPI controller | |
476 | * | |
477 | * Undo changes which were made to an SPI transfer's sglist when transmitting | |
478 | * the prologue. This is necessary to ensure the same memory ranges are | |
479 | * unmapped that were originally mapped. | |
480 | */ | |
481 | static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs) | |
482 | { | |
483 | struct spi_transfer *tfr = bs->tfr; | |
484 | ||
485 | if (!bs->tx_prologue) | |
486 | return; | |
487 | ||
488 | if (bs->rx_prologue) { | |
b31a9299 LW |
489 | sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; |
490 | sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; | |
3bd7f658 LW |
491 | } |
492 | ||
493 | if (likely(!bs->tx_spillover)) { | |
b31a9299 LW |
494 | sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; |
495 | sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; | |
3bd7f658 | 496 | } else { |
b31a9299 LW |
497 | sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4; |
498 | sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4; | |
499 | sg_dma_len(&tfr->tx_sg.sgl[1]) += 4; | |
3bd7f658 LW |
500 | } |
501 | } | |
502 | ||
3ecd37ed MS |
503 | static void bcm2835_spi_dma_done(void *data) |
504 | { | |
505 | struct spi_master *master = data; | |
506 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
507 | ||
508 | /* reset fifo and HW */ | |
509 | bcm2835_spi_reset_hw(master); | |
510 | ||
511 | /* and terminate tx-dma as we do not have an irq for it | |
512 | * because when the rx dma will terminate and this callback | |
513 | * is called the tx-dma must have finished - can't get to this | |
514 | * situation otherwise... | |
515 | */ | |
e82b0b38 | 516 | if (cmpxchg(&bs->dma_pending, true, false)) { |
2527704d | 517 | dmaengine_terminate_async(master->dma_tx); |
3bd7f658 | 518 | bcm2835_spi_undo_prologue(bs); |
e82b0b38 | 519 | } |
3ecd37ed MS |
520 | |
521 | /* and mark as completed */; | |
522 | complete(&master->xfer_completion); | |
523 | } | |
524 | ||
525 | static int bcm2835_spi_prepare_sg(struct spi_master *master, | |
526 | struct spi_transfer *tfr, | |
527 | bool is_tx) | |
528 | { | |
529 | struct dma_chan *chan; | |
530 | struct scatterlist *sgl; | |
531 | unsigned int nents; | |
532 | enum dma_transfer_direction dir; | |
533 | unsigned long flags; | |
534 | ||
535 | struct dma_async_tx_descriptor *desc; | |
536 | dma_cookie_t cookie; | |
537 | ||
538 | if (is_tx) { | |
539 | dir = DMA_MEM_TO_DEV; | |
540 | chan = master->dma_tx; | |
541 | nents = tfr->tx_sg.nents; | |
542 | sgl = tfr->tx_sg.sgl; | |
543 | flags = 0 /* no tx interrupt */; | |
544 | ||
545 | } else { | |
546 | dir = DMA_DEV_TO_MEM; | |
547 | chan = master->dma_rx; | |
548 | nents = tfr->rx_sg.nents; | |
549 | sgl = tfr->rx_sg.sgl; | |
550 | flags = DMA_PREP_INTERRUPT; | |
551 | } | |
552 | /* prepare the channel */ | |
553 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
554 | if (!desc) | |
555 | return -EINVAL; | |
556 | ||
557 | /* set callback for rx */ | |
558 | if (!is_tx) { | |
559 | desc->callback = bcm2835_spi_dma_done; | |
560 | desc->callback_param = master; | |
561 | } | |
562 | ||
563 | /* submit it to DMA-engine */ | |
564 | cookie = dmaengine_submit(desc); | |
565 | ||
566 | return dma_submit_error(cookie); | |
567 | } | |
568 | ||
3ecd37ed MS |
569 | static int bcm2835_spi_transfer_one_dma(struct spi_master *master, |
570 | struct spi_device *spi, | |
571 | struct spi_transfer *tfr, | |
572 | u32 cs) | |
573 | { | |
574 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
575 | int ret; | |
576 | ||
3bd7f658 LW |
577 | /* |
578 | * Transfer first few bytes without DMA if length of first TX or RX | |
579 | * sglist entry is not a multiple of 4 bytes (hardware limitation). | |
580 | */ | |
581 | bcm2835_spi_transfer_prologue(master, tfr, bs, cs); | |
3ecd37ed MS |
582 | |
583 | /* setup tx-DMA */ | |
584 | ret = bcm2835_spi_prepare_sg(master, tfr, true); | |
585 | if (ret) | |
3bd7f658 | 586 | goto err_reset_hw; |
3ecd37ed MS |
587 | |
588 | /* start TX early */ | |
589 | dma_async_issue_pending(master->dma_tx); | |
590 | ||
591 | /* mark as dma pending */ | |
592 | bs->dma_pending = 1; | |
593 | ||
594 | /* set the DMA length */ | |
3bd7f658 | 595 | bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len); |
3ecd37ed MS |
596 | |
597 | /* start the HW */ | |
598 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
599 | cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); | |
600 | ||
601 | /* setup rx-DMA late - to run transfers while | |
602 | * mapping of the rx buffers still takes place | |
603 | * this saves 10us or more. | |
604 | */ | |
605 | ret = bcm2835_spi_prepare_sg(master, tfr, false); | |
606 | if (ret) { | |
607 | /* need to reset on errors */ | |
2527704d | 608 | dmaengine_terminate_sync(master->dma_tx); |
dbc94411 | 609 | bs->dma_pending = false; |
3bd7f658 | 610 | goto err_reset_hw; |
3ecd37ed MS |
611 | } |
612 | ||
613 | /* start rx dma late */ | |
614 | dma_async_issue_pending(master->dma_rx); | |
615 | ||
616 | /* wait for wakeup in framework */ | |
617 | return 1; | |
3bd7f658 LW |
618 | |
619 | err_reset_hw: | |
620 | bcm2835_spi_reset_hw(master); | |
621 | bcm2835_spi_undo_prologue(bs); | |
622 | return ret; | |
3ecd37ed MS |
623 | } |
624 | ||
625 | static bool bcm2835_spi_can_dma(struct spi_master *master, | |
626 | struct spi_device *spi, | |
627 | struct spi_transfer *tfr) | |
628 | { | |
3ecd37ed MS |
629 | /* we start DMA efforts only on bigger transfers */ |
630 | if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) | |
631 | return false; | |
632 | ||
633 | /* BCM2835_SPI_DLEN has defined a max transfer size as | |
634 | * 16 bit, so max is 65535 | |
635 | * we can revisit this by using an alternative transfer | |
636 | * method - ideally this would get done without any more | |
637 | * interaction... | |
638 | */ | |
639 | if (tfr->len > 65535) { | |
640 | dev_warn_once(&spi->dev, | |
641 | "transfer size of %d too big for dma-transfer\n", | |
642 | tfr->len); | |
643 | return false; | |
644 | } | |
645 | ||
3ecd37ed MS |
646 | /* return OK */ |
647 | return true; | |
648 | } | |
649 | ||
29ad1a7a | 650 | static void bcm2835_dma_release(struct spi_master *master) |
3ecd37ed MS |
651 | { |
652 | if (master->dma_tx) { | |
2527704d | 653 | dmaengine_terminate_sync(master->dma_tx); |
3ecd37ed MS |
654 | dma_release_channel(master->dma_tx); |
655 | master->dma_tx = NULL; | |
656 | } | |
657 | if (master->dma_rx) { | |
2527704d | 658 | dmaengine_terminate_sync(master->dma_rx); |
3ecd37ed MS |
659 | dma_release_channel(master->dma_rx); |
660 | master->dma_rx = NULL; | |
661 | } | |
662 | } | |
663 | ||
29ad1a7a | 664 | static void bcm2835_dma_init(struct spi_master *master, struct device *dev) |
3ecd37ed MS |
665 | { |
666 | struct dma_slave_config slave_config; | |
667 | const __be32 *addr; | |
668 | dma_addr_t dma_reg_base; | |
669 | int ret; | |
670 | ||
671 | /* base address in dma-space */ | |
672 | addr = of_get_address(master->dev.of_node, 0, NULL, NULL); | |
673 | if (!addr) { | |
674 | dev_err(dev, "could not get DMA-register address - not using dma mode\n"); | |
675 | goto err; | |
676 | } | |
677 | dma_reg_base = be32_to_cpup(addr); | |
678 | ||
679 | /* get tx/rx dma */ | |
680 | master->dma_tx = dma_request_slave_channel(dev, "tx"); | |
681 | if (!master->dma_tx) { | |
682 | dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); | |
683 | goto err; | |
684 | } | |
685 | master->dma_rx = dma_request_slave_channel(dev, "rx"); | |
686 | if (!master->dma_rx) { | |
687 | dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); | |
688 | goto err_release; | |
689 | } | |
690 | ||
691 | /* configure DMAs */ | |
692 | slave_config.direction = DMA_MEM_TO_DEV; | |
693 | slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); | |
694 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
695 | ||
696 | ret = dmaengine_slave_config(master->dma_tx, &slave_config); | |
697 | if (ret) | |
698 | goto err_config; | |
699 | ||
700 | slave_config.direction = DMA_DEV_TO_MEM; | |
701 | slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); | |
702 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
703 | ||
704 | ret = dmaengine_slave_config(master->dma_rx, &slave_config); | |
705 | if (ret) | |
706 | goto err_config; | |
707 | ||
708 | /* all went well, so set can_dma */ | |
709 | master->can_dma = bcm2835_spi_can_dma; | |
710 | master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ | |
711 | /* need to do TX AND RX DMA, so we need dummy buffers */ | |
712 | master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; | |
713 | ||
714 | return; | |
715 | ||
716 | err_config: | |
717 | dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", | |
718 | ret); | |
719 | err_release: | |
720 | bcm2835_dma_release(master); | |
721 | err: | |
722 | return; | |
723 | } | |
724 | ||
a750b124 MS |
725 | static int bcm2835_spi_transfer_one_poll(struct spi_master *master, |
726 | struct spi_device *spi, | |
727 | struct spi_transfer *tfr, | |
728 | u32 cs, | |
0122a518 | 729 | unsigned long long xfer_time_us) |
a750b124 MS |
730 | { |
731 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
732 | unsigned long timeout; | |
733 | ||
734 | /* enable HW block without interrupts */ | |
735 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); | |
736 | ||
737 | /* fill in the fifo before timeout calculations | |
738 | * if we are interrupted here, then the data is | |
739 | * getting transferred by the HW while we are interrupted | |
740 | */ | |
2e0733bc | 741 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); |
a750b124 MS |
742 | |
743 | /* set the timeout */ | |
744 | timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; | |
745 | ||
746 | /* loop until finished the transfer */ | |
747 | while (bs->rx_len) { | |
748 | /* fill in tx fifo with remaining data */ | |
749 | bcm2835_wr_fifo(bs); | |
750 | ||
751 | /* read from fifo as much as possible */ | |
752 | bcm2835_rd_fifo(bs); | |
753 | ||
754 | /* if there is still data pending to read | |
755 | * then check the timeout | |
756 | */ | |
757 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
758 | dev_dbg_ratelimited(&spi->dev, | |
759 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
760 | jiffies - timeout, | |
761 | bs->tx_len, bs->rx_len); | |
762 | /* fall back to interrupt mode */ | |
763 | return bcm2835_spi_transfer_one_irq(master, spi, | |
2e0733bc | 764 | tfr, cs, false); |
a750b124 MS |
765 | } |
766 | } | |
767 | ||
768 | /* Transfer complete - reset SPI HW */ | |
769 | bcm2835_spi_reset_hw(master); | |
770 | /* and return without waiting for completion */ | |
771 | return 0; | |
772 | } | |
773 | ||
e34ff011 MS |
774 | static int bcm2835_spi_transfer_one(struct spi_master *master, |
775 | struct spi_device *spi, | |
776 | struct spi_transfer *tfr) | |
f8043872 | 777 | { |
e34ff011 | 778 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
f8043872 | 779 | unsigned long spi_hz, clk_hz, cdiv; |
0122a518 MS |
780 | unsigned long spi_used_hz; |
781 | unsigned long long xfer_time_us; | |
e34ff011 | 782 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
f8043872 | 783 | |
e34ff011 | 784 | /* set clock */ |
f8043872 CB |
785 | spi_hz = tfr->speed_hz; |
786 | clk_hz = clk_get_rate(bs->clk); | |
787 | ||
788 | if (spi_hz >= clk_hz / 2) { | |
789 | cdiv = 2; /* clk_hz/2 is the fastest we can go */ | |
790 | } else if (spi_hz) { | |
210b4923 MS |
791 | /* CDIV must be a multiple of two */ |
792 | cdiv = DIV_ROUND_UP(clk_hz, spi_hz); | |
793 | cdiv += (cdiv % 2); | |
f8043872 CB |
794 | |
795 | if (cdiv >= 65536) | |
796 | cdiv = 0; /* 0 is the slowest we can go */ | |
342f948a | 797 | } else { |
f8043872 | 798 | cdiv = 0; /* 0 is the slowest we can go */ |
342f948a | 799 | } |
704f32d4 | 800 | spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); |
e34ff011 | 801 | bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); |
f8043872 | 802 | |
acace73d | 803 | /* handle all the 3-wire mode */ |
6935224d MS |
804 | if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf)) |
805 | cs |= BCM2835_SPI_CS_REN; | |
acace73d MS |
806 | else |
807 | cs &= ~BCM2835_SPI_CS_REN; | |
f8043872 | 808 | |
5c09e42f LW |
809 | /* |
810 | * The driver always uses software-controlled GPIO Chip Select. | |
811 | * Set the hardware-controlled native Chip Select to an invalid | |
812 | * value to prevent it from interfering. | |
e34ff011 | 813 | */ |
5c09e42f | 814 | cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; |
f8043872 | 815 | |
e34ff011 | 816 | /* set transmit buffers and length */ |
f8043872 CB |
817 | bs->tx_buf = tfr->tx_buf; |
818 | bs->rx_buf = tfr->rx_buf; | |
e34ff011 MS |
819 | bs->tx_len = tfr->len; |
820 | bs->rx_len = tfr->len; | |
f8043872 | 821 | |
704f32d4 | 822 | /* calculate the estimated time in us the transfer runs */ |
0122a518 | 823 | xfer_time_us = (unsigned long long)tfr->len |
704f32d4 | 824 | * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ |
0122a518 MS |
825 | * 1000000; |
826 | do_div(xfer_time_us, spi_used_hz); | |
e3a2be30 | 827 | |
704f32d4 MS |
828 | /* for short requests run polling*/ |
829 | if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) | |
830 | return bcm2835_spi_transfer_one_poll(master, spi, tfr, | |
831 | cs, xfer_time_us); | |
f8043872 | 832 | |
3ecd37ed MS |
833 | /* run in dma mode if conditions are right */ |
834 | if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) | |
835 | return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); | |
836 | ||
837 | /* run in interrupt-mode */ | |
2e0733bc | 838 | return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs, true); |
f8043872 CB |
839 | } |
840 | ||
acace73d MS |
841 | static int bcm2835_spi_prepare_message(struct spi_master *master, |
842 | struct spi_message *msg) | |
843 | { | |
844 | struct spi_device *spi = msg->spi; | |
845 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
846 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); | |
847 | ||
848 | cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); | |
849 | ||
850 | if (spi->mode & SPI_CPOL) | |
851 | cs |= BCM2835_SPI_CS_CPOL; | |
852 | if (spi->mode & SPI_CPHA) | |
853 | cs |= BCM2835_SPI_CS_CPHA; | |
854 | ||
855 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
e34ff011 MS |
860 | static void bcm2835_spi_handle_err(struct spi_master *master, |
861 | struct spi_message *msg) | |
f8043872 | 862 | { |
3ecd37ed MS |
863 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
864 | ||
865 | /* if an error occurred and we have an active dma, then terminate */ | |
e82b0b38 | 866 | if (cmpxchg(&bs->dma_pending, true, false)) { |
2527704d LW |
867 | dmaengine_terminate_sync(master->dma_tx); |
868 | dmaengine_terminate_sync(master->dma_rx); | |
3bd7f658 | 869 | bcm2835_spi_undo_prologue(bs); |
3ecd37ed MS |
870 | } |
871 | /* and reset */ | |
e34ff011 | 872 | bcm2835_spi_reset_hw(master); |
f8043872 CB |
873 | } |
874 | ||
a30a555d MS |
875 | static int chip_match_name(struct gpio_chip *chip, void *data) |
876 | { | |
877 | return !strcmp(chip->label, data); | |
878 | } | |
879 | ||
e34ff011 MS |
880 | static int bcm2835_spi_setup(struct spi_device *spi) |
881 | { | |
a30a555d MS |
882 | int err; |
883 | struct gpio_chip *chip; | |
e34ff011 MS |
884 | /* |
885 | * sanity checking the native-chipselects | |
886 | */ | |
887 | if (spi->mode & SPI_NO_CS) | |
888 | return 0; | |
889 | if (gpio_is_valid(spi->cs_gpio)) | |
890 | return 0; | |
a30a555d MS |
891 | if (spi->chip_select > 1) { |
892 | /* error in the case of native CS requested with CS > 1 | |
893 | * officially there is a CS2, but it is not documented | |
894 | * which GPIO is connected with that... | |
895 | */ | |
896 | dev_err(&spi->dev, | |
897 | "setup: only two native chip-selects are supported\n"); | |
898 | return -EINVAL; | |
899 | } | |
900 | /* now translate native cs to GPIO */ | |
901 | ||
902 | /* get the gpio chip for the base */ | |
903 | chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); | |
904 | if (!chip) | |
e34ff011 MS |
905 | return 0; |
906 | ||
a30a555d MS |
907 | /* and calculate the real CS */ |
908 | spi->cs_gpio = chip->base + 8 - spi->chip_select; | |
909 | ||
910 | /* and set up the "mode" and level */ | |
911 | dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", | |
912 | spi->chip_select, spi->cs_gpio); | |
913 | ||
914 | /* set up GPIO as output and pull to the correct level */ | |
915 | err = gpio_direction_output(spi->cs_gpio, | |
916 | (spi->mode & SPI_CS_HIGH) ? 0 : 1); | |
917 | if (err) { | |
918 | dev_err(&spi->dev, | |
919 | "could not set CS%i gpio %i as output: %i", | |
920 | spi->chip_select, spi->cs_gpio, err); | |
921 | return err; | |
922 | } | |
a30a555d MS |
923 | |
924 | return 0; | |
f8043872 CB |
925 | } |
926 | ||
927 | static int bcm2835_spi_probe(struct platform_device *pdev) | |
928 | { | |
929 | struct spi_master *master; | |
930 | struct bcm2835_spi *bs; | |
931 | struct resource *res; | |
932 | int err; | |
933 | ||
934 | master = spi_alloc_master(&pdev->dev, sizeof(*bs)); | |
935 | if (!master) { | |
936 | dev_err(&pdev->dev, "spi_alloc_master() failed\n"); | |
937 | return -ENOMEM; | |
938 | } | |
939 | ||
940 | platform_set_drvdata(pdev, master); | |
941 | ||
942 | master->mode_bits = BCM2835_SPI_MODE_BITS; | |
c2b6a3a8 | 943 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
f8043872 | 944 | master->num_chipselect = 3; |
e34ff011 | 945 | master->setup = bcm2835_spi_setup; |
e34ff011 MS |
946 | master->transfer_one = bcm2835_spi_transfer_one; |
947 | master->handle_err = bcm2835_spi_handle_err; | |
acace73d | 948 | master->prepare_message = bcm2835_spi_prepare_message; |
f8043872 CB |
949 | master->dev.of_node = pdev->dev.of_node; |
950 | ||
951 | bs = spi_master_get_devdata(master); | |
952 | ||
f8043872 | 953 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2d6e75e8 LN |
954 | bs->regs = devm_ioremap_resource(&pdev->dev, res); |
955 | if (IS_ERR(bs->regs)) { | |
956 | err = PTR_ERR(bs->regs); | |
f8043872 CB |
957 | goto out_master_put; |
958 | } | |
959 | ||
960 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
961 | if (IS_ERR(bs->clk)) { | |
962 | err = PTR_ERR(bs->clk); | |
963 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
964 | goto out_master_put; | |
965 | } | |
966 | ||
ddf0e1c2 | 967 | bs->irq = platform_get_irq(pdev, 0); |
f8043872 CB |
968 | if (bs->irq <= 0) { |
969 | dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); | |
970 | err = bs->irq ? bs->irq : -ENODEV; | |
971 | goto out_master_put; | |
972 | } | |
973 | ||
974 | clk_prepare_enable(bs->clk); | |
975 | ||
ddf0e1c2 MS |
976 | bcm2835_dma_init(master, &pdev->dev); |
977 | ||
978 | /* initialise the hardware with the default polarities */ | |
979 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
980 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
981 | ||
08bc0544 | 982 | err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, |
342f948a | 983 | dev_name(&pdev->dev), master); |
f8043872 CB |
984 | if (err) { |
985 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
986 | goto out_clk_disable; | |
987 | } | |
988 | ||
247263db | 989 | err = devm_spi_register_master(&pdev->dev, master); |
f8043872 CB |
990 | if (err) { |
991 | dev_err(&pdev->dev, "could not register SPI master: %d\n", err); | |
08bc0544 | 992 | goto out_clk_disable; |
f8043872 CB |
993 | } |
994 | ||
995 | return 0; | |
996 | ||
f8043872 CB |
997 | out_clk_disable: |
998 | clk_disable_unprepare(bs->clk); | |
999 | out_master_put: | |
1000 | spi_master_put(master); | |
1001 | return err; | |
1002 | } | |
1003 | ||
1004 | static int bcm2835_spi_remove(struct platform_device *pdev) | |
1005 | { | |
e0b35b89 | 1006 | struct spi_master *master = platform_get_drvdata(pdev); |
f8043872 CB |
1007 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
1008 | ||
f8043872 CB |
1009 | /* Clear FIFOs, and disable the HW block */ |
1010 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
1011 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
1012 | ||
1013 | clk_disable_unprepare(bs->clk); | |
f8043872 | 1014 | |
3ecd37ed MS |
1015 | bcm2835_dma_release(master); |
1016 | ||
f8043872 CB |
1017 | return 0; |
1018 | } | |
1019 | ||
1020 | static const struct of_device_id bcm2835_spi_match[] = { | |
1021 | { .compatible = "brcm,bcm2835-spi", }, | |
1022 | {} | |
1023 | }; | |
1024 | MODULE_DEVICE_TABLE(of, bcm2835_spi_match); | |
1025 | ||
1026 | static struct platform_driver bcm2835_spi_driver = { | |
1027 | .driver = { | |
1028 | .name = DRV_NAME, | |
f8043872 CB |
1029 | .of_match_table = bcm2835_spi_match, |
1030 | }, | |
1031 | .probe = bcm2835_spi_probe, | |
1032 | .remove = bcm2835_spi_remove, | |
1033 | }; | |
1034 | module_platform_driver(bcm2835_spi_driver); | |
1035 | ||
1036 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); | |
1037 | MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); | |
22bf6cd2 | 1038 | MODULE_LICENSE("GPL"); |